JPS61188978A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61188978A JPS61188978A JP60029725A JP2972585A JPS61188978A JP S61188978 A JPS61188978 A JP S61188978A JP 60029725 A JP60029725 A JP 60029725A JP 2972585 A JP2972585 A JP 2972585A JP S61188978 A JPS61188978 A JP S61188978A
- Authority
- JP
- Japan
- Prior art keywords
- magnetic field
- insulating film
- layer
- interlaminar insulating
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 238000001514 detection method Methods 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000005224 laser annealing Methods 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 230000003213 activating effect Effects 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 33
- 238000000034 method Methods 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- -1 l'lo or W Chemical compound 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に３次元構造の半導体装置にか
かり、絶縁層を介して積層形成された２層の半導体回路
間の結合方法の改善に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, particularly semiconductor devices with a three-dimensional structure, and improves a method for coupling two layers of semiconductor circuits stacked with an insulating layer interposed therebetween. Regarding.
半導体装置の高集積化、高速化及び多機能化を目的とし
て、能動素子を有する回路を層状に立体集積化する３次
元構造が開発されつつある。2. Description of the Related Art A three-dimensional structure in which circuits including active elements are three-dimensionally integrated in layers is being developed for the purpose of increasing the integration, speed, and multifunctionality of semiconductor devices.
この３次元構造の半導体装置については解決すべき問題
点が多く残されているが、異なる半導体眉間の回路結合
方法についても新しい手段が要望されている。Although many problems remain to be solved regarding this three-dimensionally structured semiconductor device, there is also a need for new means for connecting circuits between the eyebrows of different semiconductors.
３次元構造の半導体装置については既に種々の発表がな
されているが、例えば本発明者等は先に下記の積層ＣＭ
ＯＳ構造のインバータによる７段リング発振器を発表し
ている。Various announcements have already been made regarding semiconductor devices with a three-dimensional structure, but for example, the present inventors have previously developed the following multilayer CM.
We have announced a 7-stage ring oscillator using an inverter with an OS structure.
Ｎ、５ａｓａｋｉ ｅｔ ａｌ、＋ Ｓｕｐｐｌｅｍｅ
ｎｔ ｔｏ ｔｈｅ ＥｘｔｅｎｄｅｄＡｂｓｔｒａｃ
ｔｓ ｏｆ ｔｈｅ １５ｔｈ ｃｏｎｆ、 ｏｎ ｔ
ｈｅ ＣＳＳＤＭ（ＴＣ５５Ｄ、 Ａｕｇ、１９８３）
、 Ｎｏ、Ａ−３−７１ＮＳ、Ｋａｗａｍｕｒａ ｅ
ｔ ａｌ、、 Ｔｅｃｈ、 Ｄｉｇｅｓｔ ｏ
ｆ ＩＥＥＨＩＥＤＭ（Ｗａｓｈｉｎｇｔｏｎ Ｄ、
Ｃ，、Ｄｅｃ、１９８３）、 ｐ、３６４−第４図はこ
の積層ＣＭＯ５構造の模式側断面図である。同図におい
て、３１はｎ型シリコン（Ｓｉ）基板、３２はｐ＋型ソ
ース及びドレイン領域、３３は二酸化シリコン（Ｓｉ（
ｈ）膜、３４はＳｉゲート電極であり、これらによりＰ
ＭＯＳ ＦＥＴ （電界効果トランジスタ）が構成され
、燐シリケートガラス（ＰＳＧ）層間絶縁膜３５が形成
される。N, 5asaki et al, + Suppleme
nt to the Extended Abstract
ts of the 15th conf, on t
he CSSDM (TC55D, Aug, 1983)
, No.A-3-71NS, Kawamura e
tal,, Tech, Digest o
f IEEHIEDM (Washington D,
C., Dec. 1983), p. 364--FIG. 4 is a schematic side sectional view of this laminated CMO5 structure. In the figure, 31 is an n-type silicon (Si) substrate, 32 is a p+ type source and drain region, and 33 is a silicon dioxide (Si) substrate.
h) The film 34 is a Si gate electrode, which allows P
A MOS FET (field effect transistor) is constructed, and a phosphorous silicate glass (PSG) interlayer insulating film 35 is formed.
更に、３７は多結晶シリコン（ｐｏｌｙ−５ｉ）膜を例
えばアルゴン（＾ｒ）レーザ照射により単結晶化した後
に島状に分離したｐ型領域、３８はこれに形成したｎ＋
型ソース、ドレイン領域、３９はＳｉＯ２膜、４０はＳ
ｉゲート電極であり、これらによりＮＭＯＳ ＦＥＴが
構成される。Further, 37 is a p-type region separated into islands after a polycrystalline silicon (poly-5i) film is single-crystalized by irradiation with an argon (^r) laser, and 38 is an n+ region formed thereon.
type source and drain regions, 39 is a SiO2 film, 40 is S
This is the i-gate electrode, and these constitute an NMOS FET.
このＰＭＯＳ ＦＥＴ、 ＮＭＯＳ ＰＥＴ画素子間に
例えばアルミニウム（Ａり配線４１を配設して、積Ｆ！
ＣＭＯ５構造のインバータを形成している。For example, an aluminum wiring 41 is arranged between the PMOS FET and NMOS PET pixel elements, and the product F!
An inverter with a CMO5 structure is formed.
前記例の如く層間絶縁膜に被覆された半導体素子、配線
等への配線接続方法としては、絶縁膜に接続位置でコン
タクトホールを形成し、例えばＡＩ等の金属もしくは多
結晶Ｓｉ等を用いてソース、ドレイン領域等に接続する
方法が従来行われている。As a method for connecting wiring to a semiconductor element, wiring, etc. covered with an interlayer insulating film as in the above example, a contact hole is formed in the insulating film at the connection position, and a source is formed using a metal such as AI or polycrystalline Si. , a method of connecting to a drain region, etc. has been conventionally used.
しかしながら例えば前記例において、ＰＭＯＳ ＦＥＴ
素子のコンタクトホールは深く導電材料の充填が困難で
、ソース、ドレイン領域３２との接触抵抗の信頼性が劣
化する虞があるばかりでな（、ＮＭＯＳ ＦＥＴ素子の
コンタクトホールとは深さに差があり層上に大きい凹凸
が発生する。However, for example, in the above example, the PMOS FET
The contact hole of the element is deep and difficult to fill with a conductive material, which not only risks deteriorating the reliability of the contact resistance with the source and drain regions 32 (there is a difference in depth from the contact hole of an NMOS FET element). Large irregularities occur on the dovetail layer.
３次元構造の配線技術として、深い接続では中間の導体
層で位置をずらして中継するなどの方法が行われている
が、従来のこれらの層間接続構造では信頼性の低下、凹
凸の発生が避けられず、平坦化技術も開発が進められて
いるものの多層積層は極めて困難である。As a wiring technology for three-dimensional structures, methods such as shifting the position and relaying in the middle conductor layer are used for deep connections, but with these conventional interlayer connection structures, it is difficult to avoid a decrease in reliability and the occurrence of unevenness. However, although planarization technology is being developed, multilayer stacking is extremely difficult.
３次元構造により高集積度の半導体装置を形成するにあ
たって、その信頼性を確保することが最重要条件である
が、従来の眉間絶縁膜にコンタクトホールを形成し金属
等を用いて眉間を接続する方法は信頌性劣化の虞が少な
くない。When forming a highly integrated semiconductor device using a three-dimensional structure, ensuring its reliability is the most important condition.Contact holes are formed in the conventional glabella insulating film and the glabella is connected using metal, etc. There is a considerable risk that this method may deteriorate its credibility.
また積層する各層の平坦化は、信頼性の高い３次元構造
を実現するために極めて重要であるが、この従来の接続
方法では凹凸の発生が大きく、その上層の平坦化が甚だ
困難であり、３次元構造を開発する際の大きい問題点の
−っである。Furthermore, planarization of each laminated layer is extremely important in order to realize a highly reliable three-dimensional structure, but this conventional connection method causes large unevenness, making it extremely difficult to planarize the upper layer. This is one of the major problems when developing three-dimensional structures.
この問題点に対処するために、信頼性が高く平坦化が容
易な新しい層間接続方法が強く要望されている。To address this problem, there is a strong need for a new interlayer connection method that is highly reliable and easy to planarize.
前記問題点は、第１の半導体層と第２の半導体層とが絶
縁層を介して積層して設けられ、該第１の半導体層に磁
界生成手段を有する回路が設けられ、かつ該第２の半導
体層に該磁界生成手段による磁界の検知手段を有する回
路が設けられてなる本発明による半導体装置により解決
される。The problem is that a first semiconductor layer and a second semiconductor layer are stacked with an insulating layer interposed therebetween, a circuit having a magnetic field generating means is provided in the first semiconductor layer, and the second semiconductor layer is provided with a circuit having a magnetic field generating means. This problem is solved by a semiconductor device according to the present invention, which includes a semiconductor layer provided with a circuit having means for detecting a magnetic field generated by the magnetic field generating means.
本発明は眉間絶縁膜を挟む一方の回路に磁界生成手段を
、他方の回路にこの磁界生成手段による磁界を層間絶縁
膜を介して検知する手段を設けて、この両回路間の信号
伝達を磁界によって行う。The present invention provides a magnetic field generating means in one circuit sandwiching the glabella insulating film, and a means for detecting the magnetic field generated by the magnetic field generating means via an interlayer insulating film in the other circuit, and the signal transmission between the two circuits is performed using the magnetic field. done by.
この構造によれば、深いエツチング、金属層形成等のプ
ロセスは必要なく、若干の凹凸を生じても各層の平坦化
は甚だ容易であり、高い信頼性が確保されて、積層数を
増加し集積度を向上することが可能となる。According to this structure, processes such as deep etching and metal layer formation are not required, and even if slight irregularities occur, it is extremely easy to flatten each layer. High reliability is ensured, and the number of laminated layers can be increased and integrated. It becomes possible to improve the degree of
［実施例〕 以下本発明を実施例により具体的に説明する。[Example〕 The present invention will be specifically explained below using examples.
第１図は３次元構造の半導体装置の本発明による信号伝
達部分の第１の実施例を示し、同図（ａｌはその磁界発
生コイルの平面図、同図（ｂ）はその磁界検知部の平面
図、同図（Ｃ）は前記両者からなる信号伝達部分のＸ−
Ｘ側断面図である。また第２図（ａ）乃至（Ｃ）は本実
施例の磁界検知部の単結晶島状領域の製造方法の例を示
す工程順平面図である。FIG. 1 shows a first embodiment of a signal transmission part according to the present invention of a three-dimensional semiconductor device, in which (al is a plan view of its magnetic field generating coil, and FIG. The plan view (C) is the X-
It is an X side sectional view. Further, FIGS. 2(a) to 2(C) are step-by-step plan views showing an example of a method for manufacturing the single-crystal island region of the magnetic field sensing portion of this embodiment.
本実施例ではまず第１のＳｉ層１上に、この層の回路か
ら電流が供給される磁界発生コイル２を設けている。こ
の磁界発生コイル２は、例えば図示の如く１辺の長さ約
１５μｍの正方形とその接続部分を、厚さ約０ 、５
ａｍ、幅約１−の断面積で形成している。この材料には
例えばアルミニウム（ＡＩ）、モリブデン（Ｍｏ）、タ
ングステン（Ｗ）等の金属、ｌ’ｌｏ、Ｗ等のシリサイ
ド、Ｓｉなど従来と同様の導電材料を用いることができ
る。In this embodiment, first, a magnetic field generating coil 2 is provided on a first Si layer 1 to which a current is supplied from a circuit in this layer. For example, as shown in the figure, this magnetic field generating coil 2 is made of a square with a side length of about 15 μm and a connecting portion thereof with a thickness of about 0.5 μm.
am, and has a cross-sectional area of approximately 1- width. As this material, a conventional conductive material such as metal such as aluminum (AI), molybdenum (Mo), or tungsten (W), silicide such as l'lo or W, or Si can be used.
この磁界発生コイル２等の上に、眉間絶縁膜３が例えば
二酸化シリコン（ＳｉＯ□）を用いて、厚さ約０．５μ
ｍ程度に設けられる。On this magnetic field generating coil 2, etc., a glabellar insulating film 3 is made of, for example, silicon dioxide (SiO□) and has a thickness of about 0.5 μm.
It is provided about m.
磁界検知部はこの層間絶縁膜３上に例えば下記の如く形
成される。すなわち例えばシラン（ＳｉＨ＜）の熱分解
法により全面に多結晶Ｓｉ層を厚さ０．４〜０．５μｍ
程度に形成し、レーザアニール法等によりこれを単結晶
化した後に、第２図ｔａ＋のパターン４の如く島状にパ
ターニングし、次いで例えば温度９５０℃程度のドライ
熱酸化法により、その表面に５ｉ０２膜５ （第１図（
Ｃ））を形成する。The magnetic field detection section is formed on this interlayer insulating film 3, for example, as described below. That is, for example, a polycrystalline Si layer with a thickness of 0.4 to 0.5 μm is formed on the entire surface by the thermal decomposition method of silane (SiH<).
After crystallizing it into a single crystal by a laser annealing method or the like, it is patterned into an island shape as shown in pattern 4 in ta+ in FIG. Membrane 5 (Fig. 1 (
C)) to form.
このパターン４上に第２図（ｂｌの如くマスク６を設け
て、例えば砒素（Ａｓ）をエネルギー１００ｋｅＶ程度
Ｔ： ト−スｉ１３ Ｘ １０１５ｃｍ−２程度にイオ
ン注入し、温度９００℃、時間２０分程度の活性化熱処
理を行い、第２図（Ｃ）の如くいずれも１型のＦＥＴ素
子のソース領域８及びドレイン領域９．２個の検出端子
領域１０及び１１を形成する。なおイオン注入が行われ
ない領域７はチャネル領域であり、本実施例では例えば
チャネル幅約１０−、チャネル長約２ｏｌｌｒｎとして
いる。A mask 6 is provided on this pattern 4 as shown in FIG. 2 (bl), and ions of, for example, arsenic (As) are implanted at an energy of about 100 keV (T: 13×1015 cm−2) at a temperature of 900° C. for 20 minutes. Activation heat treatment is performed to form a source region 8 and a drain region 9, and two detection terminal regions 10 and 11 of a type 1 FET element as shown in FIG. 2(C). The region 7 that is not covered is a channel region, and in this embodiment, the channel width is about 10 - and the channel length is about 2 ollrn, for example.
再び多結晶Ｓｉ層を厚さ０．４−程度に形成しパターニ
ングを行って、第１図（ｂ）の如くゲート電極１２を形
成することにより、５ＯＩ（ｓｉｌｉｃｏｎ ｏｎ １
ｎｓｕｌａ−ｔｏｒ）構造のｎチャネルＳｉデー８ＭＯ
５ＦＥＴ素子が完成する。A polycrystalline Si layer is again formed to a thickness of about 0.4 mm and patterned to form a gate electrode 12 as shown in FIG.
n-channel Si-day 8MO with (nsula-tor) structure
The 5FET element is completed.
本実施例において、磁界発生コイル２に１００μＡの電
流を流して磁界を発生させ、その上層のＦＥＴ素子のド
レイン電流を１００μＡ流せば、検出端子１０と１１の
間に約０．１ｍＶの起電力がホール効果によって得られ
る。この電圧を、このＭＯＳ ＦＥＴ素子と同一層に形
成された差動増幅器等に人力してこの層の後段の回路に
伝達する。In this embodiment, if a current of 100 μA is passed through the magnetic field generating coil 2 to generate a magnetic field, and a drain current of 100 μA is passed through the FET element in the upper layer, an electromotive force of about 0.1 mV is generated between the detection terminals 10 and 11. Obtained by the Hall effect. This voltage is manually applied to a differential amplifier or the like formed in the same layer as this MOS FET element and transmitted to the circuit at the subsequent stage of this layer.
なお本実施例では磁界発生コイル２を下層に、磁界検知
素子であるＭＯＳ ＦＥＴ素子を上層に配置しているが
、逆に上層に磁界発生コイル、下層に磁界検知素子を設
けることも可能であることは明らかである。In this embodiment, the magnetic field generating coil 2 is arranged in the lower layer and the MOS FET element as the magnetic field sensing element is arranged in the upper layer, but it is also possible to arrange the magnetic field generating coil 2 in the upper layer and the magnetic field sensing element in the lower layer. That is clear.
第３図は本発明の第２の実施例の磁界検知素子の平面図
であり、この磁界検知素子が前記第１の実施例の磁界検
知素子と同じ位置に形成される。FIG. 3 is a plan view of a magnetic field sensing element according to a second embodiment of the present invention, and this magnetic field sensing element is formed at the same position as the magnetic field sensing element of the first embodiment.
本実施例では検出端子１３及び１４がドレインを兼ね、
検出端子１３と１４の間の電流分配率がホール効果によ
り磁界に従って定まる。すなわち前記第１の実施例では
磁界検知素子から電圧を取り出したのに対して、木筆２
の実施例では磁界検知素子から電流を取り出している。In this embodiment, the detection terminals 13 and 14 also serve as drains,
The current distribution ratio between the detection terminals 13 and 14 is determined by the Hall effect according to the magnetic field. In other words, in the first embodiment, the voltage was extracted from the magnetic field sensing element, whereas the voltage was extracted from the magnetic field sensing element.
In the embodiment, current is taken out from the magnetic field sensing element.
以上説明した実施例に見られる様に、本発明による眉間
信号伝達構造では積層された複数の層を縦貫する製造プ
ロセスは必要なく、製造プロセスの安定とその信頼性の
確保が容易である。また各層の凹凸も軽減され、この点
からも信頼性が向上し多数の層の積層が容易となる。As seen in the embodiments described above, the glabellar signal transmission structure according to the present invention does not require a manufacturing process that vertically traverses a plurality of laminated layers, making it easy to ensure the stability of the manufacturing process and its reliability. Furthermore, the unevenness of each layer is reduced, which also improves reliability and facilitates lamination of a large number of layers.
以上説明した如く本発明によれば、３次元構造の半導体
装置の異なる半導体層間の回路の結合に高い信頼性が確
保され、かつ各層の凹凸が軽減され平坦化も容易となり
、積層数を増加し集積度を向上することが可能となるな
ど、３次元構造の半導体装置の進歩に大きい効果が得ら
れる。As explained above, according to the present invention, high reliability is ensured in the circuit coupling between different semiconductor layers of a three-dimensional semiconductor device, the unevenness of each layer is reduced, flattening is facilitated, and the number of laminated layers is increased. This has great effects on the advancement of three-dimensionally structured semiconductor devices, such as making it possible to improve the degree of integration.
第１図は３次元構造の半導体装置の信号伝達部分の第１
の実施例を示し、
第１図ｆａ）はその磁界発生コイルの平面図、第１図（
ｂ）はその磁界検知部の平面図、第１図ｆｃ）は前記両
者からなる信号伝達部分の側断面図、
第２図（ａｌ乃至（Ｃ１は該磁界検知部の単結晶島状領
域の工程順平面図、
第３図は第２の実施例の磁界検知部の平面図、第４図は
従来技術による積層ＣＭＯＳ構造のインバータの模式側
断面図である。
図において、
１は第１の５ｉｉｉ、 ２は磁界発生コイル、
３は層間絶縁膜、 ５は５ｉＯｚ膜、７はチャネ
ル領域、 ８はソース領域、９はドレイン領域、
１Ｏ１１１，１３及び１４は検出端子、１２はゲート電
極を示す。Figure 1 shows the first signal transmission part of a three-dimensional semiconductor device.
Fig. 1fa) is a plan view of the magnetic field generating coil, and Fig. 1(fa) is a plan view of the magnetic field generating coil.
b) is a plan view of the magnetic field detection section, FIG. 3 is a plan view of the magnetic field detection section of the second embodiment, and FIG. 4 is a schematic side sectional view of an inverter with a stacked CMOS structure according to the prior art. In the figures, 1 is the first 5iii , 2 is a magnetic field generating coil,
3 is an interlayer insulating film, 5 is a 5iOz film, 7 is a channel region, 8 is a source region, 9 is a drain region, 1O111, 13 and 14 are detection terminals, and 12 is a gate electrode.
Claims (1)
積層して設けられ、該第１の半導体層に磁界生成手段を
有する回路が設けられ、かつ該第２の半導体層に該磁界
生成手段による磁界の検知手段を有する回路が設けられ
てなることを特徴とする半導体装置。A first semiconductor layer and a second semiconductor layer are provided in a stacked manner with an insulating layer interposed therebetween, a circuit having a magnetic field generating means is provided in the first semiconductor layer, and a circuit having a magnetic field generating means is provided in the second semiconductor layer. 1. A semiconductor device comprising a circuit having means for detecting a magnetic field generated by means for generating a magnetic field.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60029725A JPH065795B2 (en) | 1985-02-18 | 1985-02-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60029725A JPH065795B2 (en) | 1985-02-18 | 1985-02-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61188978A true JPS61188978A (en) | 1986-08-22 |
| JPH065795B2 JPH065795B2 (en) | 1994-01-19 |
Family
ID=12284082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60029725A Expired - Fee Related JPH065795B2 (en) | 1985-02-18 | 1985-02-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065795B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330646A (en) * | 1995-03-30 | 1996-12-13 | Toshiba Corp | Lateral hall element |
| EP0855741A1 (en) * | 1997-01-17 | 1998-07-29 | Lucent Technologies Inc. | Component arrangement having magnetic field controlled transistor |
| JP2001230467A (en) * | 1999-12-09 | 2001-08-24 | Sanken Electric Co Ltd | Current detector provided with hall element |
| US7473656B2 (en) * | 2003-10-23 | 2009-01-06 | International Business Machines Corporation | Method for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks |
-
1985
- 1985-02-18 JP JP60029725A patent/JPH065795B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08330646A (en) * | 1995-03-30 | 1996-12-13 | Toshiba Corp | Lateral hall element |
| EP0855741A1 (en) * | 1997-01-17 | 1998-07-29 | Lucent Technologies Inc. | Component arrangement having magnetic field controlled transistor |
| US5872384A (en) * | 1997-01-17 | 1999-02-16 | Lucent Technologies Inc. | Component arrangement having magnetic field controlled transistor |
| JP2001230467A (en) * | 1999-12-09 | 2001-08-24 | Sanken Electric Co Ltd | Current detector provided with hall element |
| US7473656B2 (en) * | 2003-10-23 | 2009-01-06 | International Business Machines Corporation | Method for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks |
| US8105445B2 (en) | 2003-10-23 | 2012-01-31 | International Business Machines Corporation | Method and apparatus for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks |
| US8470092B2 (en) | 2003-10-23 | 2013-06-25 | International Business Machines Corporation | Method and apparatus for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065795B2 (en) | 1994-01-19 |
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