JPS61187276A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To make the titled device to correspond to voltage applied on rewriting work rapidly, and to hold written contents stably by interposing an insulating film displaying current characteristics depending upon the direction of applied voltage between a floating gate and a drain high-concentration impurity region. CONSTITUTION:A LOCOS region 29 and a protective film 21 are formed to a P-type silicon substrate 20, an opening is bored to one part of the protective film 21 and a thin oxide film 22 is shaped through thermal oxidation, and an impurity is introduced to an oxide film 22 section while using a resist 28 as a mask. The concentration distribution of the impurity in the thin insulating film 22 is increased with an approach to an N<+> region 23 formed to the surface of the semiconductor substrate and made the highest in a section brought into contact with the N<+> region 23 by selecting energy on the implantation of ions within the extent of a projection range at that time. A floating gate 24, an insulating film 25, a control gate 26, a gate electrode 27, N<+> regions 23a-23c as a source or a drain, Al wirings, etc. are shaped. Accordingly, memory contents can be rewritten at low voltage, and written contents can be held stably.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate, and particularly to an electrically rewritable memory device.

<Summary of the Invention> The present invention provides an electrically rewritable nonvolatile memory element in which a floating gate and a control gate are provided on a semiconductor substrate with an insulating film interposed therebetween. The distribution of the impurity in the insulating film is changed by increasing the barrier height on the side in contact with the floating gate and lowering the barrier height on the side in contact with the n layer of the semiconductor substrate to obtain good memory retention characteristics. It also makes carrier movement easier during writing and erasing.

<Prior Art> A semiconductor device having a cross-sectional structure shown in FIG. 3 is known as an electrically rewritable nonvolatile memory device having a floating gate.

In the figure, a transistor TM and a selection transistor Ts are formed on the same semiconductor substrate in close proximity to each other.
On a p-type silicon substrate 10 having an LOGO5 region formed of a thick oxide film, an n+ layer region 11allb, which becomes the source and drain of each transistor, is formed.
llc has been formed.

An insulating film is formed to cover the semiconductor substrate IO, and in the memory transistor section M, a floating gate 16 is formed on the insulating film 13, and a control gate 17 is formed on the insulating film 15 in order. A gate electrode 18 is stacked on the gate insulating film 14 at the transistor 215 portion.

The floating gate 16 and control gate 17 constituting the memory transistor TM are formed not only to cover the channel region of the transistor, but also to cover a part of the drain region 11b of the silicon substrate.

The insulating film 12 interposed in the portion where the extended portion of the floating gate 16 covers the drain region 11b is formed in advance to have a thin film thickness in order to facilitate data writing and erasing operations.

That is, rewriting data to the storage device is performed by applying a high voltage to the gate electrode 18 of the selection transistor Ts to rewrite the data in the n-layer region 11.
With conduction established between the a and n regions 11b, a high voltage is applied to the control gate 17 or the drain layer region 11a, and a voltage is applied between the floating gate 16 and the n layer region 11b.
A current is passed through the thin insulating film 12 to inject or drain carriers into the floating gate 16 to perform a memory function.

<Problems to be Solved by the Invention> In the semiconductor memory device having the above element structure, a sufficient current flows through the thin insulating film 12 when high voltage is applied when rewriting the memory contents, and the memory contents do not change at other times. It is necessary to ensure the reliability of the insulating film 12.

Here, the thin insulating film 12 is formed on the semiconductor substrate 10 in the layer region 11b.
The film quality is uniform. However, if this homogeneous insulating film has a high barrier height to allow current to flow, the memory retention characteristics are good, but high voltage is required for writing and erasing, and if the barrier height is lowered, the memory retention characteristics deteriorate. However, it was very difficult to obtain a suitable insulating film.

<Means to solve the problem> In order to eliminate the drawbacks of the above conventional memory device,
With regard to an insulating film formed interposed between a floating gate of a memory transistor portion and a semiconductor substrate, the barrier height of the insulating film is high on the side in contact with the floating gate and on the side in contact with the n+ layer region 11b of the semiconductor substrate. Form low. Such barrier height control is performed by introducing impurities using ion implantation technology.

<Function> The insulating film under the floating gate can be stably maintained because the barrier height against carrier movement is low on the side in contact with the n+ layer region and high on the side in contact with the floating gate.

<Example> FIGS. 1(a), 1(b) and 1(c) are cross-sectional views for explaining the manufacturing process of a semiconductor device according to the present invention.

A LOGO5 region 29 made of a thick oxide film is formed on the p-type silicon substrate 20 surrounding the device region, and a protective film 21 made of a relatively thin oxide film is formed to cover the device region having a substantially flat surface. Ru. The protective film 21 is formed with an opening in a part to form a thin oxide film that allows current to flow when rewriting the memory contents, and is newly formed with a film thickness of 100 to 150 A by thermal oxidation at, for example, 950°C. thin oxide film 2
2 is formed.

A resist 28 is applied leaving the thin oxide film 22 and its surroundings, and using the resist 28 as a mask, arsenic or phosphorus is introduced as an impurity into the thin oxide film 22 by ion implantation technology. In this ion implantation process, in order to adjust the impurity distribution in the oxide film 22 to a desired distribution, the projection range RP is set to 1 to 5 of the thin oxide film 22.
Injected with double energy. Impurities are introduced into the region not covered by the resist 28 by the ion implantation, but by selecting the energy during ion implantation within the above projection range, the impurity concentration distribution within the thin insulating film 22 can be adjusted to the surface of the semiconductor substrate. n10 area 2 to be formed
3, and becomes highest in the part in contact with the n region 23. After the above ion implantation process, heat treatment is performed in an inert gas to recover the damage caused in the ion implantation process, and the desired impurity is Forms concentration distribution.

Figure 2 shows the amount of arsenic implanted and the barrier height of the oxide film when ions are implanted using arsenic as an impurity and setting the Rp/SiO2 film thickness to 22. An inverted curve B that is in contact with is shown below. This tendency was also confirmed in devices in which phosphorus was ion-implanted as an impurity.

As is clear from the figure, the barrier height on the n0 region side decreases as the amount of arsenic implanted increases, indicating that rewriting can be easily performed, and the barrier height on the floating gate side reaches a high trench, indicating that the memory retention characteristics Demonstrate excellence in

The n+ region 23 formed as a semiconductor region in the step of ion implantation into the thin oxide film 22 forms an integral impurity region continuous with the n+ region formed in a later step.

After the ion implantation process has been completed, a polysilicon layer 24 is formed on the semiconductor substrate to serve as a floating gate, as shown in FIG. .

Further, n+ regions 23a, 2g'b, and 23c, which serve as sources or drains, are formed on the semiconductor substrate, and conduct holes, Al wiring, etc. are formed using conventionally known techniques, and the first
A nonvolatile semiconductor device shown in FIG. 3(c) is obtained.

In order to facilitate writing and erasing into the memory element, it is important for the impurity distribution in the thin oxide film 22 to have a concentration higher than 2 orders of magnitude on the layer region side of the substrate. By setting the ratio of the projection range RP in the range of 1:1 to 5, an impurity distribution that satisfies the above conditions can be obtained. <Effects of the Invention> According to the present invention, an electrically rewritable non-volatile semiconductor In the device, the memory contents can be rewritten with low voltage, and the written contents can be reliably and stably retained, making it easier to handle nonvolatile semiconductor memory devices and improving operational reliability. can be increased.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) are cross-sectional views for explaining one embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the amount of impurity implanted and the barrier height in the same embodiment, and FIG. FIG. 3 is a sectional view showing a conventional device. TM: memory transistor, Ts: selection transistor, 20+p type silicon substrate, 21a, 21b. 21c: n+ region 22: thin oxide film, 24: floating gate, 26 control gate. Agent Patent attorney Aihiko Fuku (and 2 others) (A, l)
;n'i, L6. ．． +t Procedural amendment December 19, 1985

Claims (4)

[Claims] 1. In a memory device comprising an electrically rewritable nonvolatile memory element formed by stacking a floating gate and a control gate on a semiconductor substrate with an insulating film interposed therebetween, the floating gate is formed between the source and drain of the semiconductor substrate. A non-volatile semiconductor characterized by comprising an insulating film covering a part of the channel region and the drain high concentration impurity region and interposing between the floating gate and the drain high concentration impurity region exhibiting current characteristics dependent on the direction of applied voltage. Storage device. 2. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the insulating film is formed by introducing impurities at a gradient in concentration after being formed on the semiconductor substrate. 3. 3. The nonvolatile semiconductor memory device according to claim 2, wherein the insulator is made of SiO_2, and impurities are ion-implanted with an energy of 1 to 5 times the thickness of the SiO_2 film in a projection range (R_p). . 4. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said impurity is arsenic or phosphorus.