KR100558541B1 - Eeprom Manufacturing Method - Google Patents

Abstract

The present invention discloses a process for the preparation of ypyrom. According to this, after the gate oxide film of the sense transistor is formed in the active region of the silicon substrate, first ion implantation is performed on the entire surface of the active region to adjust the threshold voltage of the sense transistor, and the conductive junction is bonded to the silicon substrate in the tunneling region. A cell N + ion implantation is performed to form a cell, a tunneling oxide film is formed on the silicon substrate in the tunneling region, a pattern of the floating gate of the sense transistor and an interlayer insulating film are formed thereon, and the threshold voltage of the select transistor is In order to adjust, a second ion implantation is performed to increase the concentration of the silicon substrate in the region excluding the floating gate region.

Therefore, the present invention can suppress the generation of punchthrough of the select transistor without significantly increasing the threshold voltage of the sense transistor, thereby reducing the channel length of the select transistor and further reducing the size of the unit memory cell.

Description

Epirom Manufacturing Method             

1 is a cross-sectional view showing the structure of a general EEPROM.

2 is a graph showing a relationship between a sense line voltage and a bit line current in on-cell and off-cell of a general Y pyrom.

3 to 9 is a cross-sectional process diagram showing a method for producing ypyrom according to the present invention.

The present invention relates to an electrically erasable programmable ROM (EEPROM), and more particularly, it is possible to reduce the channel length of the select transistor by preventing punch through of the select transistor without significantly increasing the threshold voltage of the sense transistor. It relates to a method for preparing Y pyrom.

In general, ypyrom is a device having a form of memory capable of repeatedly recording and erasing data as an electrical signal instead of using ultraviolet rays. Ipyrom is a phenomenon in which electrons pass a thin insulator of several nm thickness by the turnneling effect, that is, Fowler-Nordheim turnneling. This device is also called a FLOTOX (floating gate tunnel oxide) device.

As shown in FIG. 1, a unit memory cell of a general Y pyrom is composed of two transistors, that is, a sense transistor (commonly referred to as a sense line) and a select transistor (commonly referred to as a word line). In the sense transistor, a turnneling oxide film 15 is formed on a part of the active region of the silicon substrate 10, and the floating gate 19 and the control gate 23 are interlayer insulating films 17 on the turnneling oxide film 15. It is made of a laminated structure through the. The select transistor has a structure in which a gate electrode 25 is formed on the gate oxide film 21. The N + diffusion regions of the source line 29 and the bit line 31 are each surrounded by an N− diffusion region of high breakdown voltage.

 In the case of the general YPIROM having such a structure, it is necessary to reduce the channel length of the select transistor in order to reduce the size of the unit memory cell. In this case, a high voltage is applied to the bit line 31 to punch through the select transistor. It is difficult to suppress the occurrence. This is because the P-type impurities are ion-implanted on the entire surface of the silicon substrate 10 before forming the floating gate 19 and the turnneling oxide film 15 of the memory cell, thereby controlling the threshold voltages of the sense transistor and the select transistor together. Because.

Recently, as a method for preventing the punch-through generation of the select transistor, a method of increasing the dose of impurities implanted into the entire surface of the silicon substrate before forming the floating gate and the tunneling oxide film in the memory cell has been used. come.

However, according to the conventional method, it is possible to prevent the punch-through generation of the select transistor, but the threshold voltage of the sense transistor also increases, so that the characteristics of the on-cell shown in FIG. At the lead time, there is a lack of margin that cannot accurately identify the on-cell. As a result, according to the conventional manufacturing method, it is difficult to reduce the channel length of the select transistor, and furthermore, it is difficult to reduce the unit memory cell size.

Accordingly, it is an object of the present invention to provide a method for manufacturing an pyrom, which can reduce the channel length of a select transistor by suppressing the punch-through generation of the select transistor without significantly increasing the threshold voltage of the sense transistor.

Method for producing yipirom according to the present invention for achieving the above object,
A first insulating film, which is a gate insulating film of a sense transistor, is stacked on an active region of the first conductive semiconductor substrate, and has the same conductivity type as that of an impurity doped in the semiconductor substrate to adjust a threshold voltage of the sense transistor. Implanting first conductivity type impurities into the entire surface of the semiconductor substrate;
Forming a high concentration of the second conductivity type cell diffusion region by ion implantation of a second conductivity type impurity having a conductivity opposite to that of the first conductivity type to form a conductive junction in a portion of the semiconductor substrate step;
Forming a tunneling oxide film on the cell diffusion region;
Forming a floating gate and an interlayer dielectric layer pattern on the tunneling oxide layer;
In order to increase the surface concentration of the semiconductor substrate, the first ion-type impurities having the same conductivity type as the impurities doped in the semiconductor substrate using the floating gate pattern as a mask layer are formed on the front surface of the semiconductor substrate. Injecting;
Forming a second insulating film on the semiconductor substrate outside the pattern of the floating gate, the second insulating film serving as a gate insulating film of the select transistor;
Forming a control gate pattern on the interlayer insulating film pattern and forming a gate electrode pattern of the select transistor on the second insulating film; And
By using the floating gate pattern and the gate electrode pattern as a mask layer, a third ion implanted impurity having a second conductivity type opposite to that of the first conductivity type is implanted into the diffusion region of a high breakdown voltage. And forming a step.
Preferably, the second ion implantation is performed at an energy of 30 to 100 KeV and a dose of 1.0e11 to 1.0e12. In addition, the first ion implantation is performed at an energy of 50 to 100 KeV and a dose of 1.0e11 to 1.0e12.

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Hereinafter, a method for preparing ypyrom according to the present invention will be described in detail with reference to the accompanying drawings.

3 to 9 is a cross-sectional process diagram showing a method for producing ypyrom according to the present invention. The same code | symbol is attached | subjected to the part same as a conventional part.

As shown in FIG. 3, first, an isolation layer (not shown) in the field region of the silicon substrate 10 is used to isolate the active regions of the first conductivity type, for example, P-type silicon substrate 10 using a conventional process. Not shown).

Subsequently, the first insulating film 11 is grown to a thickness of 200 to 500 mA as a gate oxide film of the sense transistor on the active region of the silicon substrate 10 and the front surface of the silicon substrate 10 is adjusted to control the threshold voltage of the memory transistor. The first ion implantation is performed on P-type impurities. Here, the first ion implantation is performed at an energy of 50 to 150 KeV and a dose of 1.0e11 to 1.0e12.

As shown in FIG. 4, the photoresist film 12 is then formed on the region where the turnneling oxide film is to be formed by using a photolithography process to form a conductive junction on the silicon substrate 10 under the future turnneling oxide film. The pattern of the photosensitive film 12 in which a window is located is formed on the first insulating film 11.

Subsequently, a high concentration of N-type impurities are implanted into a portion of the silicon substrate 10 for the cell N + region 13 of FIG. 6 to be formed in a subsequent process using the pattern of the photosensitive film 12 as a mask layer.

As shown in FIG. 5, the window of the photosensitive film 14 is then removed to define the turnneling area for removing the pattern of the photosensitive film 12 of FIG. A pattern of the photosensitive film 14 positioned on a portion of the 13 is formed on the first insulating film 11 and the exposed first insulating film 11 in the window is used as the mask layer to form the silicon substrate 10 below it. Etch until it is exposed.

As shown in FIG. 6, a thin turnneling oxide film having a thickness of 50 to 70 microseconds is formed on the silicon substrate 10 of the previously exposed turnneling region by removing the pattern of the photosensitive film 14 of FIG. 5 and using an oxidation process. 15).

At this time, the N-type impurity implanted with the ion is diffused while the tunneling oxide film 15 is formed, and the cell N + region 13 is formed below the tunneling oxide film 15.

As shown in FIG. 7, polysilicon for the pattern of the floating gate 19 is then laminated on the first insulating film 11 including the turnneling oxide film 15 to a thickness of, for example, 1500 kPa. An interlayer insulating film 17 having an oxide-nitride-oxide (ONO) structure is stacked thereon, for example, at a thickness of 200 mW.

Subsequently, a pattern of a photoresist film (not shown) is formed only in the floating gate region, and the interlayer insulating film and the polysilicon are sequentially etched using the pattern as a mask layer to thereby pattern and flow the pattern interlayer insulating film 17 of the floating gate 19. The pattern of the gate 19 is formed.

Subsequently, the first insulating film 11 outside the pattern of the floating gate 19 is wet etched until the silicon substrate 10 below is exposed, and then the pattern of the photoresist film is removed.

Subsequently, in order to control the threshold voltage of the select transistor, P-type impurities are formed on the silicon substrate 10 at low concentration by using the pattern of the interlayer insulating film 17 and the pattern of the floating gate 19 as mask layers. Inject. Here, it is preferable to perform the second ion implantation with an energy of 30 to 100 KeV and a dose of 1.0e11 to 1.0e12.

Accordingly, the present invention increases only the surface concentration of the silicon substrate 10 other than the floating gate region unlike the conventional art, and thus increases only the threshold voltage of the select transistor without increasing the threshold voltage of the sense transistor. This means that the characteristic curve of the on-cell shown in FIG. 3 is prevented from moving to the right (+) direction, thereby sufficiently securing a margin for accurately identifying the on-cell at a low Vcc lead.

As a result, the present invention can easily reduce the channel length of the select transistor by suppressing the punch-through generation of the select transistor without significantly increasing the threshold voltage of the sense transistor, and further, can easily reduce the unit memory cell size. .

As shown in FIG. 8, the first insulating film 11 is then etched using the control gate 19 and the interlayer insulating film 17 as a mask layer until the surface of the silicon substrate 10 is exposed. do.

Thereafter, the second insulating film, which is the gate oxide film 21 of the select transistor, is grown to a thickness of 250 상 에 on the exposed region of the silicon substrate 10.

On the resultant structure, polysilicon is formed to form a control gate of the sense transistor and a gate electrode of the select transistor. Subsequently, the polysilicon is selectively etched using a photolithography process to form the control gate 23 pattern on the pattern of the floating gate 19 of the sense transistor. The gate electrode 25 pattern is formed on the second insulating film 21 that is the gate oxide film 21 of the select transistor.

Subsequently, using the pattern of the control gate 23 and the pattern of the gate electrode 25 as a mask layer, N-type impurities are formed at low concentration in order to form the N-diffusion region of the high breakdown voltage shown in FIG. Inject.

As shown in FIG. 9, the third ion implanted impurities are diffused to surround the source line 29 and the bit line 31, and the cell N + diffusion region 13 and the high breakdown voltage N integrally connected thereto. -Form a diffusion area.

Thereafter, an insulating film, such as a high temperature oxide film, is stacked on the resultant structure and etched back to form spacers 27 on sidewalls of the floating gate 19 and the control gate 23, and the sidewalls of the gate electrode 25. The spacer 27 is also formed.

Then, a pattern of a photoresist film (not shown) is formed to continuously mask the spacer 27, the control gate 23, and the gate electrode 25, and using this as a mask layer, an N-type impurity to form an N + diffusion region. Ion implanted at high concentration and diffused. Thus, each N + diffusion region for the source line 29 and the bit line 31 is wrapped in the N-diffusion region of the high breakdown voltage.

 Subsequently, an interlayer insulating film for planarization is thickly stacked on the resultant structure, and a conventional metallization process is performed to complete an ipyrom cell.

As described above, according to the present invention, after forming the gate oxide film of the sense transistor in the active region of the silicon substrate 10, the first ion implantation for adjusting the threshold voltage of the sense transistor on the front of the active region Cell N + ion implantation for forming a conductive junction on the silicon substrate in the tunneling region, forming a tunneling oxide film on the silicon substrate in the tunneling region, and forming a pattern on the floating gate of the sense transistor A second ion implantation is performed to increase the concentration of the silicon substrate in the region other than the floating gate region in order to form an interlayer insulating film and to control the threshold voltage of the select transistor.

Accordingly, the present invention can suppress the occurrence of punchthrough of the select transistor without significantly increasing the threshold voltage of the sense transistor, thereby reducing the channel length of the select transistor and further reducing the size of the unit memory cell.

On the other hand, the present invention is described based on the preferred example shown in the drawings, but not limited to this and various modifications and improvements are possible by those skilled in the art to which the present invention belongs without departing from the spirit of the invention. Of course.

Claims (3)

(Correction) A first insulating film, which is a gate insulating film of a sense transistor, is laminated on an active region of a first conductivity type semiconductor substrate, and the same conductivity type as that of an impurity doped in the semiconductor substrate is used to control the threshold voltage of the sense transistor. A step of implanting a first ion into the front surface of the semiconductor substrate with an impurity of a first conductivity type; Forming a high concentration of the second conductivity type cell diffusion region by ion implantation of a second conductivity type impurity having a conductivity opposite to that of the first conductivity type to form a conductive junction in a portion of the semiconductor substrate step; Forming a tunneling oxide film on the cell diffusion region; Forming a floating gate and an interlayer dielectric layer pattern on the tunneling oxide layer; In order to increase the surface concentration of the semiconductor substrate, the first ion-type impurities having the same conductivity type as the impurities doped in the semiconductor substrate using the floating gate pattern as a mask layer are formed on the front surface of the semiconductor substrate. Injecting; Forming a second insulating film on the semiconductor substrate outside the pattern of the floating gate, the second insulating film serving as a gate insulating film of the select transistor; Forming a control gate pattern on the interlayer insulating film pattern and forming a gate electrode pattern of the select transistor on the second insulating film; And By using the floating gate pattern and the gate electrode pattern as a mask layer, a third ion implanted impurity having a second conductivity type opposite to that of the first conductivity type is implanted into the diffusion region of a high breakdown voltage. Method of producing a pyrom, characterized in that it comprises the step of forming. The method of claim 1, wherein the second ion implantation is performed at an energy of 30 to 100 KeV and a dose of 1.0e11 to 1.0e12. The method of claim 1, wherein the first ion implantation is performed at an energy of 50 to 100 KeV and a dose of 1.0e11 to 1.0e12.

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