JPH01257374A - Mos type nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To avoid the degradation of the breakdown voltage of the diffused layer of a memory transistor caused by the reduction of the depth of the diffused layer by a method wherein the channel direction dimension of the channel part is determined by the width of a trench only regardless to the depth of the diffused layer. CONSTITUTION:A trench 12 is formed in the channel part of a memory transistor 16 and the channel length is determined by the trench 12. Therefore, the channel direction dimension of the channel part of the memory transistor can be determined by the width of the trench only regardless to the depth of a diffused layer 3. In other words, when the size of the memory transistor is reduced, it is inevitable to reduce the depth of the diffused layer with the conventional constitution but it is not inevitable with this constitution. Therefore, the degradation of the breakdown voltage of the diffused layer accompanying the size reduction of the device can be avoided. Thus, the channel length can be reduced and a large integration scale can be achieved without degrading the breakdown voltage of the diffused layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type nonvolatile semiconductor memory device having a floating gate electrode.

[Conventional technology]

Conventionally, an MO3 type nonvolatile semiconductor memory device is shown in FIG.
), (b), a diffusion layer 3, a drain diffusion layer 3A, and a source diffusion layer 3B are formed on the surface of the semiconductor substrate 1, and the diffusion layer 3, the drain diffusion layer 3A, and the source diffusion layer 3B and the semiconductor A first insulating film 4 is deposited on the surface of the substrate 1. A first layer is selectively applied to a portion above the train diffusion layer 3A.
A second insulating film M5 thinner than the insulating film 4 is deposited. A floating gate electrode 6 covering the second insulation [5] and extending over the source diffusion layer 3B, and a selection gate electrode 8 spanning the diffusion layer 3 and the drain diffusion layer 3A are provided. It is covered with a third insulating film 7, and a control gate electrode 9 is provided on the third insulating film 7. In this way, a MOS type nonvolatile semiconductor memory device was manufactured.

[Problem to be solved by the invention]

In the conventional MO3 type nonvolatile semiconductor memory device described above, the channel length l of the storage transistor 16 is equal to the drain diffusion layer 3.
Since it is determined by the distance between A and the source diffusion layer 3B, in order to obtain the effective channel length, it is necessary to set ff = L + 2R as the channel length l, and 2R (of the depth R of the diffusion layer). (2 times), the size of the storage transistor becomes larger. Furthermore, in order to reduce the dimensions of the storage transistor 16, it is sufficient to reduce the depth R of the diffusion layer, but if R is reduced, the breakdown voltage of the diffusion layer decreases, and a certain value It is not possible to reduce R below. That is, if R is set below a certain value, the breakdown voltage will decrease, causing a problem that the storage transistor will no longer operate.

[Means to solve the problem]

The MO3 type nonvolatile semiconductor memory device of the present invention includes an element isolation insulating film provided on a -conductivity type semiconductor substrate and partitioning an element region, and a first insulating film of opposite conductivity type provided at a distance from each other in the element region. a third diffusion layer; a groove provided between the second diffusion layer and the third diffusion layer with side walls in contact with each other;
A first insulating film formed on the groove surface and the semiconductor substrate surface, and a part of the first insulating film on the second diffusion layer is removed and is thinner than the first insulating film. a second insulating film, covering the first insulating film in the trench, one of which extends over the first insulating film on the third diffusion layer, and the other includes the second insulating film; the first diffusion layer on the second diffusion layer.
a floating gate electrode formed extending over an insulating film; a third insulating film provided on the surface of the floating gate electrode; and a floating gate electrode provided facing the floating gate via the third insulating film. the first control gate electrode on the first insulating crotch;
and a selection gate electrode provided across the diffusion layer and the second diffusion layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention.

A diffusion layer 3 made of an impurity having a conductivity type opposite to that of the semiconductor substrate 1, a drain diffusion layer 3A, and a source diffusion layer 3B are provided on the surface of the semiconductor substrate 1. A layer 12 is provided between the source diffusion layer 3B and the train diffusion layer 3A so that their side walls are in contact with each other. A floating gate electrode 6 made of polycrystalline silicon is buried in the groove 12 via the first insulating film 4, and extends over both the source diffusion layer 3B and the drain diffusion layer 3A. 44 and a part of the first insulating film 4 are removed to form the second insulating film 5, which is thinner than the first insulating film 4. A third insulating film 7 is provided covering the floating gate electrode 6, and a control gate electrode 9 made of polycrystalline silicon is provided on the third insulating film 7, covering the floating gate electrode 6.

A selection gate 8 made of polycrystalline silicon is provided on the first insulating film 4, spanning the diffusion layer 3 and the drain diffusion layer 3A.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 2(a), a channel stopper 13, an element isolation insulating film 2, and an insulating film 14 are formed on a semiconductor substrate 1 by a conventional method, and then a diffusion layer 3 is selectively formed.

Next, as shown in FIG. 2(b), grooves 12 dividing the diffusion layer 3 are formed to form a train diffusion layer 3A and a source diffusion layer 3B.

Next, as shown in FIG. 2(c), after removing the insulating film 14, a first insulating film 4 having a thickness of about 50 nm is formed by thermal oxidation. After removing a portion of the first insulating film 4, thermal oxidation is performed again to form a second insulating film 5 with a thickness of about 10 nm. A floating gate electrode 6 made of polycrystalline silicon is formed.

Next, as shown in FIG. 2 ((1), the floating gate electrode 6
After forming a third insulating film 7 with a thickness of about 50 nm thereon, a selection gate electrode 8 and a control gate electrode are formed.

As described above, in the present invention, the groove 12 is formed in the channel portion of the storage transistor 16, and the channel length of the storage transistor is determined by this groove. For this reason, in the present invention,
The dimension of the channel portion of the storage transistor 16 in the channel direction can be determined only by the width of the groove, regardless of the depth of the diffusion layer, and the depth of the diffusion layer is made shallow in order to reduce the channel length of the conventional storage transistor. There is no problem that the breakdown voltage of the diffusion layer decreases because the depth of the diffusion layer is made shallow.

〔Effect of the invention〕

As explained above, in the present invention, a groove is formed in the channel portion of the storage transistor, and the channel length of the storage transistor is determined by the groove. It can be determined only by the width of the groove, regardless of the width. That is, conventionally,
Although it has been essential to reduce the depth of the diffusion layer when downsizing the memory transistor, it is not essential to reduce the depth of the diffusion layer in the present invention. Therefore, a decrease in the breakdown voltage of the diffusion layer, which has conventionally been a problem when downsizing the device, can be avoided. As described above, the present invention has the effect that the channel length can be shortened without lowering the breakdown voltage of the diffusion layer, and high-density integration is possible.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention, and FIGS. 2(a) to (d) illustrate a manufacturing method of an embodiment of the present invention. Cross-sectional views of a semiconductor chip shown in the order of steps for explanation, FIGS. 3(a) and 3(b) are conventional MO
A plan view of an example of a type 3 nonvolatile semiconductor memory device and B-B
' It is a line sectional view. 1... Semiconductor substrate, 2... Element isolation insulating film, 3...
- Diffusion layer, 3A... Drain diffusion layer, 3B... Source diffusion layer, 4... First insulating film, 5... Second insulating film, 6... Floating gate electrode, 7... ...Third insulating film,
8... Selection gate electrode, 9... Control gate electrode, 1
0... Interlayer insulating film, 11... Aluminum electrode, 1
2...Groove, 13...Channel stopper, 14...
- Insulating film, 15... selection transistor, 16... memory transistor.

Claims (1)

[Claims] an element isolation insulating film provided on a semiconductor substrate of one conductivity type and partitioning an element region; first to third diffusion layers of opposite conductivity types provided at intervals in the element region; a groove provided between the diffusion layer and the third diffusion layer with their sidewalls in contact; a first insulating film formed on the surface of the groove and the surface of the semiconductor substrate; a second insulating film that is provided by removing a part of the first insulating film and is thinner than the first insulating film; and a second insulating film that covers the first insulating film in the groove and one of which is on the third diffusion layer. a floating gate electrode formed to extend on the first insulating film on the second diffusion layer so as to extend on the first insulating film and the other to include the second insulating film; a third insulating film provided on the surface of the floating gate electrode; a control gate electrode provided facing the floating gate via the third insulating film; and a control gate electrode provided on the first insulating film. A MOS comprising a selection gate electrode provided straddling the diffusion layer and the second diffusion layer.
type nonvolatile semiconductor memory device.