JPH0795570B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a MOS non-volatile semiconductor memory device having a floating gate electrode.

[Conventional technology]

Conventionally, in a MOS type nonvolatile semiconductor memory device, as shown in FIGS. 3A and 3B, a diffusion layer 3, a drain diffusion layer 3A, and a source diffusion layer 3B are formed on the surface of a semiconductor substrate 1 and then diffused. Layer 3 and drain diffusion layer 3A and source diffusion layer 3B
A first insulating film 4 is deposited on the above and on the surface of the semiconductor substrate 1. A second insulating film 5 thinner than the first insulating film 4 is selectively deposited on a part of the drain diffusion layer 3A. The floating gate electrode 6 which covers the second insulating film 5 and extends on the source diffusion layer 3B, and the selection gate electrode 8 which extends over the diffusion layer 3 and the drain diffusion layer 3A are provided. The control gate electrode 9 is provided on the third insulating film 7 while being covered with the third insulating film 7. Thus, the MOS type nonvolatile semiconductor memory device was manufactured.

[Problems to be Solved by the Invention]

In the conventional MOS non-volatile semiconductor memory device described above, since the channel length 1 of the memory transistor 16 is determined by the distance between the drain diffusion layer 3A and the source diffusion layer 3B, it is necessary to obtain the effective channel length L. As channel length l, l = L +
2R must be set, and 2R (diffusion layer depth R 2
That is, the size of the memory transistor becomes larger. Further, in order to reduce the size of the memory transistor 16, it is sufficient to reduce the depth R of the diffusion layer.
If is smaller, the breakdown voltage (breakdown voltage) of the diffusion layer is lowered, and R cannot be made smaller than a certain value. That is, when R is set to a certain value or less, the breakdown voltage is lowered and the storage transistor does not operate.

[Means for Solving the Problems]

Therefore, in the present invention, one MOS type transistor and one
In a method for manufacturing a nonvolatile semiconductor memory device in which a memory cell is composed of a plurality of floating gate type transistors, a first conductivity type diffusion layer and a second conductivity type second diffusion layer are separated on a surface of a one conductivity type semiconductor substrate. Forming a groove by forming a groove by removing a predetermined region of the second diffusion layer, and separating the second diffusion layer into two regions by the groove, and dividing the second diffusion layer into two regions. Forming a gate electrode of the MOS transistor on the surface of the semiconductor substrate sandwiched between the diffusion layer in one region of the two diffusion layers and the first diffusion layer via a first insulating film; Forming a floating gate electrode of the floating gate type transistor by covering the first insulating film on the inner wall surface of the groove and the second insulating film on the diffusion layer in the one region, and on the floating gate electrode The floating gate type through a third insulating film And forming a control gate electrode of the transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A and 1B are a plan view and a sectional view taken along the line AA 'of a nonvolatile semiconductor memory device manufactured according to an embodiment of the present invention.

A diffusion layer 3, a drain diffusion layer 3A, and a source diffusion layer 3B made of impurities of the opposite conductivity type to the semiconductor substrate 1 are provided on the surface of the semiconductor substrate 1. A groove 12 is provided between the source diffusion layer 3B and the drain diffusion layer 3A so that its side wall is in contact. A floating gate electrode 6 made of polycrystalline silicon is buried in the groove 12 via a first insulating film 4 and extends over both the source diffusion layer 3B and the drain diffusion layer 3A. 4 and a part of the first insulating film 4 are removed to form a second insulating film 5 thinner than the first insulating film 4. A third insulating film 7 is provided to cover the floating gate electrode 6, and a control gate electrode 9 made of polycrystalline silicon is provided to cover the floating gate electrode 6 on the third insulating film 7. The first insulating film 4 straddles the diffusion layer 3 and the drain diffusion layer 3A.
A select gate 8 made of polycrystalline silicon is provided on the top.

2A to 2D are cross-sectional views of the semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 2A, a channel stopper 13, an element isolation insulating film 2 and an insulating film 14 are formed on a semiconductor substrate 1 by a usual method, and then a diffusion layer 3 is selectively formed.

Next, as shown in FIG. 2B, a groove 12 that divides the diffusion layer 3 is formed to form a drain diffusion layer 3A and a source diffusion layer 3B.

Next, as shown in FIG. 2C, after removing the insulating film 14, a first insulating film 4 having a thickness of about 50 nm is formed by a thermal oxidation method. After part of the first insulating film 4 is removed, it is thermally oxidized again to form a second insulating film 5 having a thickness of about 10 nm. A floating gate electrode 6 made of polycrystalline silicon is formed.

Next, as shown in FIG. 2D, after the third insulating film 7 having a thickness of about 50 nm is formed on the floating gate electrode 6, the selection gate electrode 8 and the control gate electrode 9 are formed.

According to the present invention, the groove 12 is formed in the channel portion of the memory transistor 16 as described above, and the channel length of the memory transistor is determined by this groove. Therefore, according to the present invention, the dimension of the channel portion of the memory transistor 16 in the channel direction can be determined only by the width of the groove irrespective of the depth of the diffusion layer. However, there is no problem that the breakdown voltage of the diffusion layer is lowered because the depth of the diffusion layer is made shallow and the depth of the diffusion layer is made shallow.

〔The invention's effect〕

As described above, according to the present invention, since the groove is formed in the channel portion of the memory transistor and the channel length of the memory transistor is determined by the groove, the dimension of the channel portion of the memory transistor in the channel direction is set to the depth of the diffusion layer. It has nothing to do with the width of the groove. That is, in the past,
Although it was essential to make the depth of the diffusion layer shallow when reducing the size of the memory transistor, it is not essential to make the depth of the diffusion layer shallow in the present invention. Therefore, it is possible to avoid the decrease in the breakdown voltage of the diffusion layer, which has been a problem when the device is downsized. As described above, the present invention has the effect that the channel length can be shortened and high-density integration can be achieved without lowering the breakdown voltage of the diffusion layer.

[Brief description of drawings]

1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of a nonvolatile semiconductor memory device manufactured according to an embodiment of the present invention, and FIGS. FIG. 3 is a cross-sectional view of a semiconductor chip, showing the order of steps for explaining an embodiment of the invention;
1A and 1B are a plan view and a cross-sectional view taken along line BB 'of an example of a conventional MOS non-volatile semiconductor memory device. 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Diffusion layer, 3A ... Drain diffusion layer, 3B ... Source diffusion layer, 4 ...
... first insulating film, 5 ... second insulating film, 6 ... floating gate electrode, 7 ... third insulating film, 8 ... selection gate electrode,
9 ... Control gate electrode, 10 ... Interlayer insulating film, 11 ... Aluminum electrode, 12 ... Groove, 13 ... Channel stopper,
14 ... Insulating film, 15 ... Select transistor, 16 ... Memory transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/788 29/792

Claims (1)

[Claims] 1. A method of manufacturing a non-volatile semiconductor memory device in which a memory cell is composed of one MOS type transistor and one floating gate type transistor, wherein a surface of one conductivity type semiconductor substrate is of opposite conductivity type. Forming the first diffusion layer and the second diffusion layer separately, and removing a predetermined region of the second diffusion layer to form a groove to form the second diffusion layer in two regions by the groove. And a step of separating the second diffusion layer into the two regions and a semiconductor substrate surface sandwiched by the diffusion layer in one region of the second diffusion layer and the first diffusion layer with the first insulating film interposed therebetween. Forming a gate electrode of a MOS transistor, and covering the first insulating film on the inner wall surface of the groove and the second insulating film on the diffusion layer in the one region to float the floating gate transistor. A step of forming a gate electrode,
A step of forming a control gate electrode of the floating gate type transistor on the floating gate electrode via a third insulating film, the method of manufacturing a semiconductor memory device.