JPS61187241A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61187241A JPS61187241A JP2677985A JP2677985A JPS61187241A JP S61187241 A JPS61187241 A JP S61187241A JP 2677985 A JP2677985 A JP 2677985A JP 2677985 A JP2677985 A JP 2677985A JP S61187241 A JPS61187241 A JP S61187241A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- heating
- brazing material
- semiconductor
- thermal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〈発明の分野〉
この発明は、混成集積回路に適用される半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device applied to a hybrid integrated circuit.
〈従来技術とその問題点〉
従来、この種の半導体装置として、たとえば第４図に示
すものが知られている。同図（Ａ）において、■は配！
Ｉ基板で、この配線基板ｌは電気絶縁基板２上に導電パ
ターン３を形成するとともに、この導電パターン３上に
半田などのろう付け材４が設定されている。<Prior art and its problems> Conventionally, as this type of semiconductor device, the one shown in FIG. 4, for example, is known. In the same figure (A), ■ is a placement!
This wiring board 1 is an I board, and a conductive pattern 3 is formed on an electrically insulating board 2, and a brazing material 4 such as solder is set on the conductive pattern 3.
５は半導体素子で、この半導体素子５は半導体基板６の
下面に電極７および５ｉ０２のような保護被膜８を有す
る。上記電極７は導電パターン３上のろう付け材４に対
向配設されて、配線基板１上に半導体素子５が載置され
る。この載置状態において、上記配線基板１の導電パタ
ーン３上に設定されたろうイ」け材４を加熱炉内で加熱
溶融させることにより、上記半導体素子５の電極７が同
図（Ｂ）に示すように電気的に接続固定される。5 is a semiconductor element, and this semiconductor element 5 has an electrode 7 and a protective film 8 such as 5i02 on the lower surface of a semiconductor substrate 6. The electrode 7 is arranged to face the brazing material 4 on the conductive pattern 3, and the semiconductor element 5 is placed on the wiring board 1. In this mounted state, the soldering material 4 set on the conductive pattern 3 of the wiring board 1 is heated and melted in a heating furnace, so that the electrodes 7 of the semiconductor element 5 are formed as shown in FIG. Electrically connected and fixed.
ところが、上記ろう付け材４の加熱溶融時に、半導体素
子５の自重によって、この半導体素子５の電８ｉ７がろ
う付け材４の内部に沈み込んで、半導体基板６の外周縁
部６ａがろう付け材４と接触して電気的に短絡される欠
点があった。However, when the brazing material 4 is heated and melted, the conductor 8i7 of the semiconductor element 5 sinks into the brazing material 4 due to the weight of the semiconductor element 5, and the outer peripheral edge 6a of the semiconductor substrate 6 is exposed to the brazing material. 4, which caused an electrical short circuit.
そこで、従来、第５図に示すように半導体素子５の電極
７に対向させて、ろう付け材４の内部に銅などの導電性
ボール９を埋設して半導体素子５の沈み込みを規制した
り、あるいは、第６図に示すように半導体基板６の外周
縁部６ａに対向させて、ろう付け材４の流動を規制する
ガラスペーストのどの流動規制層１０を配線基板ｌ上に
設定したものが知られている。Therefore, conventionally, as shown in FIG. 5, conductive balls 9 made of copper or the like are buried inside the brazing material 4 so as to face the electrodes 7 of the semiconductor element 5 to prevent the semiconductor element 5 from sinking. Alternatively, as shown in FIG. 6, a flow regulating layer 10 of glass paste for regulating the flow of the brazing material 4 is set on the wiring board l so as to face the outer peripheral edge 6a of the semiconductor substrate 6. Are known.
しかし、上記のようにろう付け材４の内部に導電性ボー
ル９を埋設したり、ろう付け材４の流動規制層１０を配
線基板１上に設定する作業がきわめて面倒である欠点が
あった。However, as described above, there is a drawback that the work of embedding the conductive balls 9 inside the brazing material 4 and setting the flow regulating layer 10 of the brazing material 4 on the wiring board 1 is extremely troublesome.
また、ろうイ」け材４の加熱溶融時における配線基板ｌ
と半導体素子５の有する熱分布や熱膨張係数の差によっ
て、半導体素子５が第５図の実線から仮想線で示すよう
に平面方向（矢印ａ方向）へ伸長する。その後、配線基
板ｌと半導体素子５の冷却にともなって、半導体素子５
が第５図の仮想線から実線で示す平面方向（矢印す方向
）へ収縮する過程において、ろう付け材４が固化したの
ち、その収縮が規制されるから、半導体素子５には熱歪
として残存し、半導体素子５の特性を悪化させる欠点が
あった。In addition, the wiring board l when the soldering material 4 is heated and melted.
Due to the difference in thermal distribution and thermal expansion coefficient of the semiconductor element 5, the semiconductor element 5 expands in the plane direction (direction of arrow a) as shown by the imaginary line from the solid line in FIG. Thereafter, as the wiring board l and the semiconductor element 5 are cooled, the semiconductor element 5
In the process of shrinking from the imaginary line in FIG. 5 to the plane direction shown by the solid line (in the direction of the arrow), the brazing material 4 solidifies and then its shrinkage is regulated, so that it remains in the semiconductor element 5 as thermal strain. However, there was a drawback that the characteristics of the semiconductor element 5 were deteriorated.
とくに、ろう付け材４はそれ自身の重力により垂れ下っ
て中央部が大径となり、その機械的強度が強いため、ろ
う付け材４が固化したのちに、半導体素子５が収縮しよ
うとするのを規制する強度が高く、半導体素子５に残存
する熱歪が大きいために、その熱歪によって半導体素子
５を破損させるおそれがあった。In particular, the brazing material 4 hangs down due to its own gravity and has a large diameter in the center, and its mechanical strength is strong, so it prevents the semiconductor element 5 from shrinking after the brazing material 4 has solidified. Since the regulating strength is high and the thermal strain remaining in the semiconductor element 5 is large, there is a risk that the semiconductor element 5 may be damaged due to the thermal strain.
〈発明の目的〉
この発明は上記従来の欠点を除去するためになされたも
ので、半導体素子の優れた特性を保持するとともに、製
造の容易な半導体装置を提供することを目的としている
。<Objective of the Invention> The present invention has been made to eliminate the above-mentioned conventional drawbacks, and aims to provide a semiconductor device that maintains the excellent characteristics of a semiconductor element and is easy to manufacture.
〈発明の構成と効果〉
この発明による半導体装置は、配線基板と半導体素子と
の間に加熱によって伸長する加熱伸長部材を介挿し、ろ
う付け材の加熱溶融時に上記加熱伸長部材を伸長させて
上記配線基板に半導体素子なろうイ」けしたことに特徴
を有する。<Structure and Effects of the Invention> A semiconductor device according to the present invention includes a heating elongating member that is expanded by heating inserted between a wiring board and a semiconductor element, and elongating the heating elongating member when heating and melting the brazing material. The feature is that the wiring board is designed to be a semiconductor element.
したがって、この発明によれば、ろう付け材の加熱溶融
時に上記加熱伸長部材を伸長させることにより、ろう付
け材が伸長するから、その機械的強度が低減される。そ
のため、ろう付け材が固化したのちにおける半導体素子
が収縮しようとするときの規制強度が低くなり、半導体
素子に残存する熱歪を上記伸長したろう付け材によって
吸収することができる。Therefore, according to the present invention, the brazing material is elongated by elongating the heating and elongating member when the brazing material is heated and melted, so that its mechanical strength is reduced. Therefore, the restraint strength when the semiconductor element tries to shrink after the brazing material has solidified is reduced, and the thermal strain remaining in the semiconductor element can be absorbed by the expanded brazing material.
また、ろう付け材が伸長して長寸となることによって、
半導体素子が平面方向へ伸長したとき、上記ろう付け材
を側方へ回動させようとする回動角度が小さくなり、そ
の小さくなった分だけ半導体素子５がろうイ」け材から
受ける反力が小さくなる。Also, as the brazing material expands and becomes longer,
When the semiconductor element expands in the plane direction, the rotation angle that attempts to rotate the brazing material laterally becomes smaller, and the reaction force that the semiconductor element 5 receives from the brazing material corresponds to the smaller rotation angle. becomes smaller.
したがって、半導体素子が熱歪によって特性の悪化や破
損を生じるおそれがない。Therefore, there is no risk of deterioration of characteristics or damage of the semiconductor element due to thermal strain.
さらに、加熱伸長部材は発泡性樹脂や、形状記憶合金を
配線基板と半導体素子との間に介挿するという簡単な構
成であるから、その製造が容易である。Furthermore, since the heat-stretching member has a simple structure in which foamable resin or shape memory alloy is inserted between the wiring board and the semiconductor element, it is easy to manufacture.
〈実施例の説明〉 以下、この発明の実施例を図面にしたがって説明する。<Explanation of Examples> Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明による半導体装置の一例を示す磨面図
である。図において、配線基板１と半導体素子５との間
には、加熱によって伸長する加熱伸長部材１１が介挿さ
れている。この加熱伸長部材１１は加熱によって発泡す
る発泡性樹脂や、電気絶縁性樹脂でコーティングされた
形状記憶合金から構成されている。なお、図中、第４図
と同一部分には同一・の符号を付してその詳しい説明を
省略する。FIG. 1 is a polished view showing an example of a semiconductor device according to the present invention. In the figure, a heating expansion member 11 that expands upon heating is inserted between a wiring board 1 and a semiconductor element 5. The heat-stretching member 11 is made of a foamable resin that foams when heated or a shape memory alloy coated with an electrically insulating resin. In addition, in the figure, the same parts as in FIG. 4 are given the same reference numerals, and detailed explanation thereof will be omitted.
上記配線基板１に半導体素子５を電気的に接続するには
、まず、第２図に示すように、配線基板ｌの−１−面と
半導体素子５の下面とに、１−記加熱伸長部材１１を接
着剤で仮り固定したのち、ろう付け材４を加熱炉内で加
熱溶融させると、」１記半導体素子５の電極７が第２図
に示すように上記ろう付け材４に電気的に接続される。In order to electrically connect the semiconductor element 5 to the wiring board 1, first, as shown in FIG. 11 is temporarily fixed with an adhesive, and then the brazing material 4 is heated and melted in a heating furnace. As a result, the electrode 7 of the semiconductor element 5 is electrically connected to the brazing material 4 as shown in FIG. Connected.
−１−記ろう付け材４の加熱溶融時における配線基板１
と半導体素子５の有する熱分布や熱膨張係数の差によっ
て、半導体素子５が第２図の実線から仮想線で示すよう
に平面方向（矢印ａ方向）へ伸長する。その後、配線基
板１と半導体素子５の冷却にともなって、半導体素子５
が第２図の仮想線から実線で示す平面方向（矢印す方向
）−収縮する過程において、ろう付け材４が固化したの
ち、その収縮が規制されようとする。-1- Wiring board 1 during heating and melting of brazing material 4
Due to the difference in thermal distribution and thermal expansion coefficient of the semiconductor element 5 and the semiconductor element 5, the semiconductor element 5 expands in the plane direction (direction of arrow a) as shown by the imaginary line from the solid line in FIG. Thereafter, as the wiring board 1 and the semiconductor element 5 are cooled down, the semiconductor element 5
In the process of shrinking from the imaginary line in FIG. 2 in the planar direction (direction indicated by the arrow) shown by the solid line, after the brazing material 4 solidifies, its shrinkage is regulated.
ところが、上記ろう付け材４の加熱溶融時に、加熱伸長
部材１１が発泡性樹脂の場合には発泡して、形状記憶合
金の場合にはその形状が原状に復帰して、第１図に示す
ように伸長する。このような加熱伸長部材１１の伸長に
よって、ろう付け材４が伸長され、上記ろう付け材４の
機械的強度が低減される。そのため、ろう付け材４が固
化したのちにおける半導体素子５の収縮を規制しようと
する規制強度が低くなり、半導体素子５に残存する熱歪
を上記伸長したろう付け材４によって吸収することがで
きる。However, when the brazing material 4 is heated and melted, if the heated elongated member 11 is made of a foamable resin, it will foam, and if it is made of a shape memory alloy, its shape will return to its original state, as shown in FIG. It extends to. The brazing material 4 is elongated by such elongation of the heating elongating member 11, and the mechanical strength of the brazing material 4 is reduced. Therefore, the strength of regulation that attempts to restrict shrinkage of the semiconductor element 5 after the brazing material 4 is solidified is reduced, and the thermal strain remaining in the semiconductor element 5 can be absorbed by the expanded brazing material 4.
また、ろう付け材４が伸長して長寸となることによって
、半導体素子５が平面方向へ長さｄだけ伸長したとき、
上記ろう付け材４を側方へ回動させようとする回動角度
θ１が、第３図に示すように、ろう付け材４が伸長しな
い場合の回動角度０２よりも小さくなり、その小さくな
った分だけ半導体素子５がろう付け材４から受ける反力
が小さくなる。Furthermore, when the semiconductor element 5 is extended by a length d in the plane direction due to the brazing material 4 elongating and becoming elongated,
As shown in FIG. 3, the rotation angle θ1 at which the brazing material 4 is to be rotated laterally becomes smaller than the rotation angle 02 when the brazing material 4 does not expand. Therefore, the reaction force that the semiconductor element 5 receives from the brazing material 4 becomes smaller.
したがって、半導体素子５が熱歪によって特性の悪化や
破損を生じるおそれがない。Therefore, there is no risk that the semiconductor element 5 will suffer from deterioration in characteristics or damage due to thermal strain.
さらに、加熱伸長部材１１は発泡性樹脂や形状記憶合金
を配線基板１と半導体素子５との間に介挿するという簡
単な構成であるから、その製造が容易である。Furthermore, since the heating elongation member 11 has a simple structure in which a foamable resin or a shape memory alloy is inserted between the wiring board 1 and the semiconductor element 5, it is easy to manufacture.
第１図はこの発明による半導体装置の一例を示す一部切
欠した正面図、第２図はこの発明による半導体装置の製
造工程を説明するための一部切欠した正面図、第３図は
この発明による半導体装置の作用説明図、第４図は従来
の半導体装置の一例を示し、（Ａ）は製造前の一部切欠
した正面図、（Ｂ）は製造後の一部切欠した正面図、第
５図および第６図は従来の半導体装置のそれぞれ異なる
他の例を示す一部切欠した正面図である。
■・・・配線基板、３・・・導電パターン、４・・・ろ
う付け材、５・・・半導体素子、７・・・電極、１１・
・・加熱伸長部材。
第１図
４：ろう付け材 １１：加熱伸長部材第３図FIG. 1 is a partially cutaway front view showing an example of a semiconductor device according to the present invention, FIG. 2 is a partially cutaway front view illustrating the manufacturing process of the semiconductor device according to the present invention, and FIG. 3 is a partially cutaway front view showing an example of the semiconductor device according to the present invention. FIG. 4 shows an example of a conventional semiconductor device, in which (A) is a partially cutaway front view before manufacturing, (B) is a partially cutaway front view after manufacturing, and FIG. 5 and 6 are partially cutaway front views showing other different examples of conventional semiconductor devices. ■... Wiring board, 3... Conductive pattern, 4... Brazing material, 5... Semiconductor element, 7... Electrode, 11...
・Heating expansion member. Figure 1 4: Brazing material 11: Heated expansion member Figure 3
Claims (3)
記配線基板の導電パターン上に設定されたろう付け材を
加熱溶融させて上記半導体素子の電極を電気的に接続固
定してなる半導体装置において、上記配線基板と半導体
素子との間に加熱によつて伸長する加熱伸長部材を介挿
し、上記ろう付け材の加熱溶融時に加熱伸長部材を伸長
させて上記配線基板に半導体素子をろう付けしたことを
特徴とする半導体装置。(1) In a semiconductor device in which a semiconductor element is placed on a wiring board, and the electrodes of the semiconductor element are electrically connected and fixed by heating and melting a brazing material set on the conductive pattern of the wiring board. , a heating extensible member that expands by heating is inserted between the wiring board and the semiconductor element, and the semiconductor element is brazed to the wiring board by expanding the heating extensible member when the brazing material is heated and melted. A semiconductor device characterized by:
からなる特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the heat-stretchable member is made of a foamable resin that foams when heated.
形状記憶合金からなる特許請求の範囲第１項記載の半導
体装置。(3) The semiconductor device according to claim 1, wherein the heating elongation member is made of a shape memory alloy coated with an electrically insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2677985A JPS61187241A (en) | 1985-02-14 | 1985-02-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2677985A JPS61187241A (en) | 1985-02-14 | 1985-02-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61187241A true JPS61187241A (en) | 1986-08-20 |
Family
ID=12202785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2677985A Pending JPS61187241A (en) | 1985-02-14 | 1985-02-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61187241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016077092A (en) * | 2014-10-07 | 2016-05-12 | 三菱電機株式会社 | Motor, air conditioner, and manufacturing method of motor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161853A (en) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | Semiconductor pellet mounted body and manufacture thereof |
-
1985
- 1985-02-14 JP JP2677985A patent/JPS61187241A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161853A (en) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | Semiconductor pellet mounted body and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016077092A (en) * | 2014-10-07 | 2016-05-12 | 三菱電機株式会社 | Motor, air conditioner, and manufacturing method of motor |
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