JPS61187195A - Memory refresh control system - Google Patents

Abstract

PURPOSE:To minimize the reduction in the processing capability of an information processor by detecting refresh enable and pre-refresh timing and using AND of both the detected outputs so as to execute the refresh cycle. CONSTITUTION:A refresh counter section 10 outputs a refresh trigger signal on a signal line 17 and outputs a pre-fresh timing signal onto a signal line 19 to input a preset signal on a signal line 18. Further, an AND gate 15 inputs the 1st and 2nd refresh enable signals on signal lines 6, 7 respectively to obtain AND and the result is outputted. Then the memory refresh cycle is obtained on the signal line 28 by the AND among the 1st refresh signal (signal line 6), the 2nd refresh enable signal (signal line 7) and the pre-refresh timing signal (signal line 19). Then the execution of the cycle using effectively the time not subject to memory access is attained by executing the refresh cycle to minimize the reduction in the processing capability of the information processing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory refresh control method for a memory that requires memo IJ refreshing in an information processing device, and particularly to a start timing control method for a memory refresh execution cycle.

(Prior Art) Conventionally, when memory refresh is controlled by a memory control unit in an information processing device equipped with a memory that requires memory refresh, a refresh cycle is detected and a memory refresh cycle is executed based on this detection signal. It was composed of

However, in the case of the conventional method, as shown in FIG. 4, if the central processing unit or DMA control unit is already executing a memory access cycle at the timing when the memory refresh cycle is to be started, the end of that cycle is not executed. Had to wait and perform a memory refresh cycle.

Furthermore, during the memory refresh cycle, of course,
Since the central processing unit and the DMA control unit cannot execute memory access cycles, the activation of the execution cycles has been delayed.

(Problems to be Solved by the Invention) As explained above, according to the prior art, there was a delay in the memory refresh cycle or execution cycle under the above operating conditions, so when the processing capacity of the information processing device decreased. There was a drawback.

An object of the present invention is to detect a cycle in which the central processing unit and the DMA control unit do not access the memory, detect a time shorter than the memory refresh cycle as the memory refresh timing, and use the AND of the rain detection signals to It is an object of the present invention to provide a memory refresh control method configured to eliminate the above-mentioned drawbacks by executing a refresh cycle, and to effectively utilize the time when memory is not accessed to enable execution in the memory refresh cycle.

(Means for solving the problem) The memory refresh control method according to the present invention includes a memory that requires dynamic refresh, a memory control section for controlling refresh, and a DMA control section for controlling direct memory access. The memory control section is comprised of refresh enable detection means, pre-refresh timing detection means, and refresh execution means.

The refresh enable detection means is for detecting a cycle in which the DMA control unit does not access the memory.

The pre-refresh timing detection means is for detecting a time period shorter than the memory refresh cycle required by the memory by the memory control unit as the memory refresh timing.

The refresh execution means is for executing a refresh cycle in the memory control section by a pre-refresh trigger signal obtained by ANDing the outputs of the refresh enable detection means and the output of the pre-refresh timing detection means.

(Embodiments) First, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the memory refresh control method according to the present invention. In FIG. 1, 1 is a central processing unit, 2 is a DMA control section, 3 is a memory control section, 4 is a memory, and 8 is a memory address bus. In FIG. 1, the memory control unit 3 receives a memory access trigger signal output from the DMA control unit 2 onto the signal line 5;
The first and second refresh enable signals output from the central processing unit 1 and the DMA control unit 2 onto the signal lines 6 and 7, respectively, and the address information on the memory address bus 8 are processed as input signals, and the signal lines A memory control signal is output to the memory IJ 4 via the memory IJ 9.

FIG. 2 is a block diagram showing details of the memory control section. In FIG. 2, the memory control section 3 includes a refresh address counter section 10 and a memory operation timing generation section 1.
1, a refresh address counter 12, first and second multiplexers 13 and 14, and AND gates 15 and 16. In FIG. 2, the refresh counter section 10 outputs a refresh trigger signal on a signal line 17, outputs a pre-refresh timing signal on a signal line 19, and inputs a preset signal on a signal line 18. The memory operation timing generation unit 11 inputs the refresh trigger signal on the signal line 17, the pre-refresh trigger signal on the signal line 28, and the memory access trigger signal on the signal line 5, and outputs the preset signal on the signal line 18. A refresh address update signal is output on the signal line 27, an address mode switching signal is output on the signal line 21, an address switching signal is output on the signal line 22, and a memory control signal is output on the signal line 23. outputs a write/read signal (W/I-1,)' on the signal line 24, outputs a row address selection signal (R, AS) on the signal line 24,
A column address selection signal (OAS) i is output on the signal line 25. The refresh address counter section 12 is connected to the signal line 2.
It inputs the refresh address update signal on signal line 7 and outputs the refresh address on signal line 20.

The first multiplexer 13 receives the address mode switching signal on the signal line 21, the refresh address signal on the signal line 20, and the address on the memory address bus 8, and inputs the address mode switching signal on the signal line 21, the refresh address signal on the signal line 20, and the address on the memory address bus 8. Output either. The output signals of the second multiplexer 14ij and il multiplexer 13 are inputted, and the memory address is divided into a row address and a column address and outputted onto the signal line 26 according to the address switching signal on the signal line 22.

The AND gate 15 inputs the first and second refresh enable signals on the signal lines 6 and 7, respectively, and outputs the logical product.

The AND gate 16 inputs the output of the AND gate 15 and the pre-refresh timing signal on the signal line 19, and outputs it onto the signal line 28 as a pre-refresh trigger signal.

FIG. 3 is a timing diagram illustrating the operation of the apparatus according to the invention shown in FIGS. 1 and 2.

The present invention will now be described in detail with reference to FIG.

As shown in Figure 3, the memory access cycles when memory refresh is not taken into consideration are CPU, DMA, and CP.
U, DMA, DMA, free.

The order is DMA, CPU, OjU, DMA, and CPU. In this case, the first refresh enable signal on signal line 6 is at a low level during the CPU cycle;
It is at a high level during cycle periods other than the PU cycle. Similarly, the second refresh enable signal on signal line 7 is at a low level during DMA cycles and is at a high level during cycles other than DMA cycles. Furthermore, since the pre-refresh timing signal on the signal line 19 is output only for a short time compared to the timing of the refresh trigger signal (on the signal line 17) according to the memory refresh cycle (see FIG. 2(C)), the timing shown in FIG. (a) +7) The phase is at a high level. If the pre-refresh timing signal is output onto the signal line 19 earlier than the refresh trigger signal on the signal line 17, that time has no particular meaning. However, the longer the period from FIG. 2(a) to FIG. 2(e), the more opportunities the functions of the present invention become effective.

As is clear from FIG. 2, the memory refresh cycle starts with the first refresh enable signal (signal line 6).
and a second refresh enable signal (signal line 7),
It is obtained on signal line 28 by ANDing with the pre-refresh timing signal (signal line 19). Activated by a pre-refresh trigger signal.

In FIG. 3, a pre-refresh trigger signal is output in phase S. In this embodiment, when the pre-refresh trigger M-15E on the signal line 28 is input to the memory operation timing generation unit 11, a preset signal is immediately output on the signal line 18 (see #3 (C)). ).

In response to this signal, the refresh counter unit 1° starts counting for refresh synchronization from the initial state.

Therefore, as shown in FIGS. 2(d) and 2(e), the pre-refresh timing signal on the signal line 19 becomes low level, and the refresh trigger signal on the signal line 17 is also no longer output. The count of the refresh counter section 10 progresses, and when the corresponding time arrives, the pre-refresh timing signal is again output on the signal I&19 and becomes high level, and the same control as above is repeated.

It is clear that when there is an empty memory access cycle as shown in FIG. 3, the memory refresh cycle can be performed without reducing processing performance by implementing the present invention.

On the other hand, if there is no free space in the memory access cycle, pre-refresh is sent on the signal line 28) IJ
No trigger signal is generated, and a refresh trigger signal on signal line 17 executes a memory refresh cycle similar to the prior art.

In FIG. 2, the block for outputting the memory control signal to the signal line 9 and its operation are not directly related to the present invention and are conventionally generally implemented, so their explanation will be omitted.

(Effects of the Invention) As described above, the present invention detects refresh enable and blur refresh timing, and performs a refresh cycle using a pre-refresh trigger signal obtained by logically multiplying rain detection outputs. This has the effect of making it possible to execute a memory refresh cycle by effectively using the time that is not being accessed, and minimizing the deterioration of the processing capacity of the information processing device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the memory refresh control method according to the present invention. FIG. 2 is an operation timing diagram when the pre-refresh trigger signal shown in FIG. 1 functions effectively. FIG. 3 is a block diagram showing details of the memory control section of FIG. 1. FIG. 4 is an operation timing diagram when the pre-refresh trigger signal does not function effectively according to the prior art. 1...Central processing unit 2...DMA control unit 3...
-Memory control unit 4...Memory lO...Refresh counter unit 11...Memory operation timing generation unit 12...Refresh address counter 13.14...Multiplexer 15-6...AND gates 5-9 , 17-28... Signal line agent Patent attorney Hisashi Inoro 23 Figure j Figure 4

Claims (1)

[Claims] Memory that requires dynamic refresh,
The memory control unit includes a memory control unit for controlling the refresh and a DMA control unit for controlling direct memory access, and the memory control unit detects that it is a cycle in which the DMA control unit does not access the memory. a pre-refresh timing detection means for detecting, as a memory refresh timing, a time shorter than the memory refresh period required by the memory by the memory control unit; an output of the refresh enable detection means; A refresh execution means for executing a refresh cycle in the memory control unit by a pre-refresh trigger signal obtained by ANDing the outputs of the pre-refresh timing detection means. Memory refresh control method.