JPH065066A - Memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device wherein data can be written irrespectively of the readout order in a FIFO manner or it can be read out irrespectively of the write order in a FIFO manner. CONSTITUTION:A memory device is provided with RAMs 12, 22 and control means 11, 21 which control the RAMs. The control means 11 has a built-in read address counter; in a write operation, it writes data to the RAM 12 according to a write address which is input from the outside; in a readout operation, it reads out data at the RAM 12 by incrementing the read address counter. The control means 21 has a built-in write address counter; in a write operation, it writes data to the RAM 22 by incrementing the write address counter; in a readout operation, it reads out data at the RAM 22 according to a read address which is input from the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, particularly RA.
First-in-first configured using M
The present invention relates to a memory device having an out (hereinafter referred to as FIFO) function.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a FIFO memory circuit disclosed in, for example, Japanese Patent Laid-Open No. 64-73592. In the figure, 31 is a control circuit, which has a write address counter and a read address counter built therein. 32 is a RAM and 33 is a gate circuit. FIG. 4 is a timing chart showing the operation of the FIFO memory circuit of FIG. 3, and FIG. 5 is an explanatory diagram thereof.

Next, the operation will be described. FIF of FIG.
When performing normal writing to the O memory circuit, the write signal (W) from the control circuit 31 becomes valid for the RAM 32 by setting the control signal (CONT) to "L", and writing can be performed in the A cycle. Becomes When re-reading is performed after all the written data is read in this state, the control signal is set to “H” to invalidate the write signal and activate the write request signal (/ WREQ). And write request. Then, in the B cycle, the read address counter built in the control circuit 31 is counted up. By this operation, the data can be reread by the number counted up from the first data.

For example, as shown in FIG. 5, three pieces of data are stored in the RAM 32 from the initial state of Step 1. In this case, the control signal is set to "L" as shown in FIG.
There are 3 A cycles that validate the write signal to RAM32.
The write address counter built in the control circuit 31 is cycled and becomes “3” at Step 4. next,
The three stored data are read in Steps 5 and 6. The read address counter counts up each time a read operation is performed, and if the count value of the write address counter matches, the control circuit 31 determines that the memory is empty. At this time, the data actually remains in the memory.

After that, the reread operation is started. First, in Step 8, the control circuit 31 is reset to the initial state. Next, the control signal is set to "H" to invalidate the write signal to the memory and activate the write request signal. In this case, write address in Step 9
The counter counts up, but no new data is written to the memory and the previous data value remains. Therefore, when re-reading the next data, Step
The data output at 10 is the data input at Step 2. In this way, by executing the B cycle and then reading the data, the previously stored data is sequentially output, so that re-reading is possible.

[0006]

In the conventional FIFO memory circuit, since the first input data is stored in order, and the reading is performed by the first-in first-out method in which the older data is prioritized, the FIFO memory circuit is preprocessed in the reading order. It is necessary to include a procedure of performing the above and writing in the FIFO memory circuit, and the work is troublesome.

The present invention has been made in order to solve the above problems, and writing can be performed in the FIFO memory circuit regardless of the reading order, or the writing can be performed regardless of the writing order. The purpose is to obtain a memory device that can be.

[0008]

A memory device according to one aspect of the present invention is a memory device having a RAM and a control means for controlling the RAM, wherein the control means has a built-in read address counter for writing. The data is written to the RAM according to the write address input from the outside, and when reading the data, the read address counter is incremented to read the data from the RAM. A memory device according to another aspect of the present invention is a memory device including a RAM and a control unit for controlling the RAM, wherein the control unit includes a write address counter and counts up the write address counter when writing. The data is written to the RAM by using the read data and the data is read from the RAM according to the read address input from the outside.

[0009]

According to one aspect of the present invention, when writing, data is written in the RAM in accordance with a write address input from the outside, and when reading, the read address counter counts up, and RA
The data of M is read. Therefore, the write address can be freely selected, and in the preprocessing stage, the preprocessed data can be sequentially written into the memory without paying attention to the order of reading from the memory. In another aspect of the present invention, the write address counter counts up to write the data to the RAM at the time of writing, and the data of the RAM is read at the time of reading according to the input read address. Therefore, the read address can be freely selected, and in the pre-processing stage, the data can be written in the memory in order from the data for which the pre-processing has been completed without paying attention to the order of reading from the memory.

[0010]

【Example】

Example 1. FIG. 1 is a block diagram showing the configuration of a memory device according to an embodiment of the present invention. In the figure, 11 is a control circuit, which has a built-in read address counter. Reference numeral 12 is a RAM, and 13 is a bit width conversion circuit.

Next, the operation will be described. When the write request signal WREQ is input to the control circuit 11, the control circuit 11 determines the state of the RAM 12 at that time and accepts the request. When the control circuit 11 accepts this write request, it writes the data to the RAM 12 according to the write address input from the outside. When a certain amount of data is written from the head address, the control circuit 11 monitors this and reads it. Start the cycle. The read address is designated by the read address counter, and the read address counter continuously counts up from the head address to the address where the data is written. When trying to access an unwritten address, the control circuit 11 suspends the read cycle.

The data at the address designated by the read address counter is sequentially read, and the read data is a bit control signal (bit-cont).
roll) determines the bit width of the data. For example, when 32 bit data is read, it is divided into 4 by the bit width conversion circuit 13 and is output for every 8 bit data. By dividing and outputting the data in this way, the data width is matched with the data width of the adjacent circuit interface (not shown).

Example 2. FIG. 2 is a block diagram showing the configuration of a memory device according to another embodiment of the present invention. Although the write address can be freely selected in the above embodiment, the read address can be freely selected in this embodiment. In the figure, 21 is a control circuit, which has a built-in write address counter. 22 is a RAM, and 23 is a bit width conversion circuit.

Next, the operation will be described. Control circuit 21
Causes the write address counter to count up, and the data is sequentially written to the RAM 22 at the addresses designated thereby. The control circuit 21 outputs the read request signal R
When REQ is input, the read address and the value of the write address counter are compared, and if the read address is smaller, the read cycle is executed. At that time, the data is read according to the read address input from the outside.

By the way, when writing the write data into the RAM 22, the bit width conversion circuit 23 appropriately converts the width of the input data and writes it. For example, 4 for 8 bit data
When the divided data is input, the size is converted to 32 bit data and written in the RAM 22. In this way, the write data is processed and fetched according to the data width output by the adjacent circuit (not shown).

[0016]

As described above, according to the present invention, since the write address or the read address can be freely selected, in the former case, the read operation is the same as that of the FIFO circuit, but the read operation is performed. You can write in any order. In the latter case, the writing operation is the same as that of the FIFO circuit, but the data can be read without being influenced by the writing order.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory device according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional FIFO memory circuit.

4 is a timing chart showing the operation of the FIFO memory circuit of FIG.

5 is an explanatory diagram of an operation of the FIFO memory circuit of FIG.

[Explanation of symbols]

 11 Control Circuit 12 RAM 13 Bit Width Conversion Circuit 21 Control Circuit 22 RAM 23 Bit Width Conversion Circuit

Claims (2)

[Claims] 1. A memory device comprising a RAM and a control means for controlling the RAM, wherein the control means has a built-in read address counter, and when writing, the R data is written in accordance with a write address inputted from the outside.
When writing to or reading from the AM, the RA is incremented by counting up the read address counter.
A memory device for reading M data. 2. A memory device comprising a RAM and a control means for controlling the RAM, wherein the control means has a built-in write address counter and counts up the write address counter input at the time of writing to write data. Is written in the RAM, and the RA is read according to a read address input from the outside when reading.
A memory device for reading M data.