JPS60252399A - Voice synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a speech synthesis device that can simultaneously output different speech messages to a plurality of speech synthesizers.

[Prior art]

Conventionally, audio data editing processing and audio data transfer processing are performed by one control circuit (for example, a microprocessor). In this case, speech output message specification information for multiple speech synthesizers (including specification information of the speech synthesizer to output, character string information to output, accent information, etc.) is input to the processor, and according to this information, registered words and arbitrary messages are input. Words are synthesized according to rules, speech data for each speech synthesizer is edited, and data is transferred from the speech memory to the speech synthesizer by program transfer or DMA transfer.

Furthermore, when a large number of speech synthesizers are connected, a plurality of control circuits are used. For example, if the number of speech synthesizers that can be processed by one control circuit is 32, when 128 speech synthesizers are used, four control circuits perform parallel processing.

As in the former case, when audio data editing processing and audio data transfer processing are performed by one processor, and the audio data transfer processing is program transfer, the audio data requested by multiple speech synthesizers can be transferred at high speed in real time. In order to output the output audio without interruption, the frame period (for example, IQm
s) It is necessary to preferentially transfer audio data from the synthesis memory to the synthesis synthesizer. For this reason, as the number of speech synthesizers that can be connected increases, the time required for audio data transfer processing, which requires real-time operation, increases, and this becomes a bottleneck, limiting the number of speech synthesizers that can be connected, that is, the number of lines. Furthermore, even when the audio data transfer process is performed by DMA transfer, the processor is in a halt state (stops operation) during the DMA transfer, so the audio data editing process is performed during the audio data transfer time within the frame cycle time. cannot be executed in parallel. Therefore, when synthesizing arbitrary single chains in a regular manner, there is not enough time allocated to processing that requires real-time processing in audio editing processing, that is, calculation of difference values of audio parameters, amplitudes, time lengths, etc., and interpolation processing. The number of connectable speech synthesizers is limited.

Furthermore, when performing parallel processing using one or more processors as in the latter case, it is necessary to provide an audio memory for each processor, which increases the amount of hardware.

Even if a single audio memory is shared by each processor, a priority control circuit or the like is required to access the shared audio memory, resulting in a complicated control circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a speech synthesis device that eliminates the above-mentioned drawbacks.

[Structure of the invention]

The device of the present invention includes an audio data editing unit that creates audio output instruction information based on input audio output message designation information and an audio memory management table, and stores audio output instruction information given from the audio data editing unit. and audio data transfer control means that asynchronously reads out the audio output instruction information from the storage unit and transfers audio data from the audio memory to the audio synthesizer based on the audio output instruction information.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a conventional speech synthesis device.

Referring to FIG. 1, the control circuit 102 responds to the audio output message designation information 101 input from the terminal 101, performs audio data editing processing for the designated audio synthesizer, and edits the audio data stored in the audio memory 103. The specified audio data is stored in the audio memory 103 by referring to the management table.
, and transfers it to the speech synthesizer 104 designated by program transfer or DMA transfer. The plurality of speech synthesizers 104 convert the speech data into speech waveforms and output them to each line 105.

FIG. 2 is a block diagram showing one embodiment of the present invention.

Audio data editing circuit 201 (details of operation are given in Japanese Unexamined Patent Application Publication No. 1983-
1.64400) responds to the audio output message designation information input from the terminal 101,
Referring to the audio memory management table 205, audio data editing processing is performed for each audio synthesizer, and audio output instruction information 202 as shown in FIG. 3 is output to the order memory 2031''.

At this time, the audio data editing circuit 201 can execute the next audio data editing process even during data transfer. FIG. 4 is a flowchart showing the processing contents of the audio data editing circuit 201. In the figure, step A is a process of receiving voice output message designation information, step B is a character string corresponding to the voice message to be output, included in the voice output message designation information, accent information for the voice message to be output, and voice synthesis to be output. In step C, the speech memory management table 205 is referred to for the corresponding speech synthesizer for each frame, and the speech parameter extraction and combination processing is performed based on the character string. Audio transmission instruction information 20 as shown
2, Step D is a process for transmitting voice transmission instruction information, and Step E is a process for detecting whether or not the voice message has been uttered (detected by counting the utterance time corresponding to the number of transferred bytes). If not, the next frame is processed in step C, and if the process is finished, the next step A is made to receive the next audio output message designation information.

The j order memory 203 is an F'IFO memory (First-In +
First-Out memory). The audio data transfer control circuit 204 reads the audio transmission instruction information 202 from the sequence memory 203, sets one audio memory address to the first counter in the circuit 204, sets the number of transfer bytes to the second counter in the circuit 204, and sets the number of bytes to be transferred to the second counter in the circuit 204. While incrementing the first counter by 1 until the second counter reaches 0, voice data is transferred at high speed from the address in the voice memory 103 specified by the first counter to the voice synthesizer 104 corresponding to the output line number. The speech synthesizer 104 converts the speech data into a speech waveform and outputs it to a designated line 105.

In this embodiment, the audio data editing process and the audio data transfer process are performed in separate circuits, so that the audio data editing circuit can edit the next audio data even during the data transfer time by simply setting the audio transmission instruction information in the order memory. Processing becomes executable. Furthermore, the order memory that connects the audio data chronology circuit and the audio data transfer control circuit can be configured with a simple circuit because seven times the number of output lines and a customer month that stores voice transmission instruction information are sufficient. It is possible to downsize the equipment.

〔Effect of the invention〕

As described above, the present invention has the advantage of being able to achieve faster processing and smaller size of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional speech synthesis device, FIG. 21 is a block diagram showing an embodiment of the present invention, FIG. The figure is a diagram showing a flowchart of processing contents of the i-voice data editing circuit. In the figure, 101...terminal, 102...control circuit, 103...audio memory, 104...
Speech synthesizer, 105... Output line, 201...
...Audio data editing circuit, 202...Audio transmission instruction information, 203...Sequence memory, 204
...Audio data transfer control circuit, 205...
...Voice memory management table. Hayabusa Iol Kaya 2nd 3rd Figure

Claims (1)

[Claims] In a speech synthesis device capable of simultaneously outputting different speech messages to a plurality of speech synthesizers, the speech data editing means creates speech output instruction information based on input speech output message specification information and a speech memory management table; a storage means for storing the audio transmission instruction information viewed from the audio data editing means; and a storage means for asynchronously reading out the audio transmission instruction information from the storage means and transmitting the audio data from the audio memory to the speech synthesizer based on the audio transmission instruction information. A speech synthesis device comprising: data transfer control means for transferring.