JPH0481196B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a speech synthesis device that can simultaneously output different speech messages to a plurality of speech synthesizers.

[Prior art]

Conventionally, audio data editing processing and audio data transfer processing are performed by one control circuit (for example, a microprocessor). In this case, speech output message specification information for multiple speech synthesizers (including specification information of the speech synthesizer to output, character string information to output, accent information, etc.) is input to the processor, and according to this information, registered words and Arbitrary words are synthesized according to rules, the speech data for each speech synthesizer is edited, and data is transferred from the speech memory to the speech synthesizer by program transfer or DMA transfer.

Furthermore, when a large number of speech synthesizers are connected, a plurality of control circuits are used. For example, 1
Assuming that the number of speech synthesizers that can be processed by one control circuit is 32, when using 128 speech synthesizers, the configuration is such that parallel processing is performed by four control circuits.

As in the former case, when audio data editing processing and audio data transfer processing are performed by one processor, and the audio data transfer processing is program transfer, the audio data required by multiple speech synthesizers can be transferred at high speed in real time. However, in order to output the output audio without interruption, it is necessary to preferentially transfer audio data from the speech synthesis memory to the speech synthesis device at every frame period (for example, 10 ms). Therefore, as the number of connected speech synthesizers increases, the time required for audio data transfer processing, which requires real-time operation, increases, and this becomes a network that limits the number of connectable speech synthesizers, that is, the number of lines. Similarly, when audio data transfer processing is performed using DMA transfer, the processor
During the transfer, it is in a halt (operation stopped) state, so the audio data editing process cannot be executed in parallel during the audio data transfer time within the frame cycle time. Therefore, when synthesizing arbitrary words according to rules, there is not enough time allocated to processing that requires real-time processing in audio editing processing, that is, calculation of difference values of audio parameters, amplitudes, time lengths, etc., and interpolation processing. The number of connectable speech synthesizers is limited.

Furthermore, when parallel processing is performed by a plurality of processors as in the latter case, it is necessary to provide an audio memory for each processor, which increases the amount of hardware. Even if a single audio memory is shared by each processor, a priority control circuit or the like is required to access the shared audio memory, resulting in a complicated control circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a speech synthesis device that eliminates the above-mentioned drawbacks.

[Structure of the invention]

The device of the present invention includes an audio data editing unit that creates audio output instruction information based on input audio output message designation information and an audio memory management table, and stores audio output instruction information given from the audio data editing unit. and audio data transfer control means that asynchronously reads out the audio output instruction information from the storage unit and transfers audio data from the audio memory to the audio synthesizer based on the audio output instruction information.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing a conventional speech synthesis device. Referring to FIG. 1, the control circuit 102 responds to the audio output message designation information 101 input from the terminal 101, performs audio data editing processing for the designated audio synthesizer, and edits the audio data stored in the audio memory 103. The designated audio data is read from the audio memory 103 with reference to the management table, and transferred to the designated audio synthesizer 104 by program transmission or DMA transmission. The plurality of speech synthesizers 104 convert the speech data into speech waveforms and output them to each line 105.

FIG. 2 is a block diagram showing one embodiment of the present invention. The audio data editing circuit 201 (for details of the operation, refer to Japanese Patent Laid-Open No. 164400/1983) responds to the audio output message designation information input from the terminal 101, and edits the audio memory management table 205.
, the audio data editing process for each audio synthesizer is performed, and audio output instruction information 202 as shown in FIG. 3 is output to the order memory 203. At this time, the audio data editing circuit 201 can execute the next audio data editing process even during data transfer. FIG. 4 is a flowchart showing the processing contents of the audio data editing circuit 201. In the figure, step A is a process of receiving audio output message designation information, and step B is character strings included in the audio output message designation information that correspond to audio parameters to be output, accent information for the audio message to be output, and speech synthesis to be output. In step C, the speech memory management table 205 is referred to for the corresponding speech synthesizer for each frame, and the speech parameter extraction and combination processing is performed based on the character string. Step D is a process for creating voice transmission instruction information 202 as shown in FIG. If the process is not completed, the next frame is processed, and if the process is completed, the next step A is used to receive the next audio output message designation information.

The order memory 203 is the audio data editing circuit 201
In order to enable the audio data transfer control circuit 204 to operate asynchronously, a FIFO memory (First-
In, First-Out memory). The audio data transfer control circuit 204 reads the audio transmission instruction information 202 from the sequence memory 203, sets the audio memory address in the first counter in the circuit 204, and
The number of transferred bytes is set in the second counter in the circuit 204, and while the first counter is incremented by 1 until the second counter becomes 0, the output line number is calculated from the address in the audio memory 103 specified by the first counter. The voice synthesizer 104 transfers voice data at high speed to the voice synthesizer 104 corresponding to the voice synthesizer 104. The voice synthesizer 104 converts the voice data into a voice waveform and outputs it to a designated line 105.

In this embodiment, the audio data editing process and the audio data transfer process are performed in separate circuits, so that the audio data editing circuit can edit the next audio data even during the data transfer time by simply setting the audio transmission instruction information in the order memory. Processing becomes executable. Furthermore, the sequential memory that connects the audio data editing circuit and the audio data transfer control circuit has sufficient capacity to store audio transmission instruction information for the number of output lines, and can be configured with a simple circuit, making it possible to downsize the device. It is.

〔Effect of the invention〕

As described above, the present invention has the effect of increasing the processing speed and reducing the size of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional speech synthesis device, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. The figure is a diagram showing a flowchart of processing contents of the audio data editing circuit. In the figure, 101... terminal, 102... control circuit, 103... voice memory, 104... voice synthesizer, 105... output line, 201... voice data editing circuit, 202... voice sending instruction information, 20
3...Order memory, 204...Audio data transfer control circuit, 205...Audio memory management table.

Claims (1)

[Claims] 1. A voice memory that stores voice parameters; a plurality of voice synthesizers that receive the voice parameters and synthesize voice; an voice memory management table that indicates the voice storage state of the voice memory; In response to the input audio output message designation information, refer to the audio memory management table and output the audio output line number and the audio memory address where the audio parameters of the audio to be output to the designated line are stored. an audio data editing section that outputs audio transmission instruction information composed of the number of audio parameters (number of bytes) of audio; a sequence memory that buffers the audio transmission instruction information output by the audio data editing section; means for reading the audio output instruction information and setting the audio memory address in a first counter; means for setting the audio parameter number in a second count; and a register for holding the audio output line number; Using the data output by the first counter as the address of the voice memory, one byte of voice parameters is read from the address of the voice memory indicated by the first counter and sent to the voice synthesizer of the voice output line number held in the register. means for transferring the audio parameters read from the audio memory; means for incrementing a first counter by 1 after completion of the transfer; means for decrementing a second counter by 1 after completion of the transfer; and means for transferring the audio parameters until the value of the second counter becomes 0. a voice data transfer section having means for reading voice parameters from the voice memory and transferring voice parameters to the voice synthesizer having the voice output line number held in the register; 2. The speech synthesis device according to claim 1, wherein the speech data editing section and the speech data transfer control section operate independently.