JPS61187067A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To shorten the access time by making it possible that a processor monopolizes shared resources when a multiprocessor system is degenerated to a single processor constitution. CONSTITUTION:If a processor 1 accesses a shared memory 4 when a processor 2 is not operated and only the processor 1 is operated, '1' is outputted from a signal line 1-9, and a bus use request is not outputted through a signal line 1-2; but if a signal line 8 is in the '0' state, a gate 1-10 is opened by gates 1-6 and 1-7, and an internal bus 1-4 and the shared bus 5 are connected, and the shared memory 4 is accessed unconditionally. When a device 3 accesses the shared memory 4, it issues the bus use request through a signal line 3-2. A bus control circuit 6 receives this signal and selects the device 3 by a competition circuit 6-1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiprocessor system, and particularly to a multiprocessor system that can be reduced to a single processor system.

[Background of the invention]

Conventional multiprocessor systems are based on the premise that multiple processors operate at the same time, and when a processor accesses a device and common memory that are shared among one processor, it is assumed that the number of processors, shared devices, and common memory are connected to a common memory. In order to obtain the right to use the bus, a use request was made to the bus management circuit, permission was obtained from the bus management circuit, and then such access was performed via the common bus. That is, the bus management circuit resolves conflicting requests for use of a common device and common memory by a plurality of processors, and controls any one processor to use the common bus at a time. However, when the number of processors degenerates to one, even though this processor can monopolize the shared device and common memory, it is necessary to obtain the right to use the common memory via the bus management circuit. Compared to a single-processor-only system, the device and common memory access time is longer and the performance is degraded. For example, the technique described in Japanese Patent Application Laid-Open No. 56-145067 can be mentioned.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor system that improves the performance of a single processor by eliminating the shortcomings in conventional multiprocessor systems in which performance decreases compared to a single processor dedicated system when the number of processors is reduced to one. It is in.

[Summary of the invention]

In the case of a multi-processor configuration in which a plurality of processors are operating, the present invention controls one processor and bus management means so that each processor obtains permission to use the bus via the bus management means, and a single processor in which only one processor is operating. When configured, when there is no bus use request from a device, the single processor unconditionally monopolizes the common bus without going through the bus management means, and when there is a bus use request from a device, the single processor's bus use request is suppressed. The multiprocessor system is characterized by a means for controlling the multiprocessor system.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing the structure of a multiprocessor system. 1 and 2 are processors, 1-1 and 2 respectively.
-1 local memory, each of which is used exclusively. A device 3 is shared by the processors 1 and 2, and a common memory 4 is also shared by the processors 1 and 2. 5 are processors 1 and 2. It is a common bus to which the device 6 and the common memory 4 are commonly connected, and 6 is a bus management circuit for controlling the use of the common bus 5. The bus management circuit includes processors 1 and 2. Signal IIJ1-2.2 from device 6
-2゜5-2, resolves conflicts regarding requests to use the common bus 5, selects one of the request sources, and sends a signal I! 1-3. 2-5. A permission signal is sent back via any one of 5-5.

The processor 1 or 2 that has obtained the permission signal in this way can access the device 3 or the common memory 4. 1-4
and 2-4 are processor buses connecting the processors 1, 2 and local memories 1-1, 2-1, respectively;
is a signal line to which 1 is sent when there is a bus use request from device 3 in a single processor system. This is a signal line that sends signal 1 from the processor in an 8-h single processor system to affirm permission for device 3 to use the bus.

FIG. 2 is a diagram showing the internal configuration of the processor 1 and the bus management circuit 6. The circuit configuration of processor 2 is also similar to that of processor 1.
It is similar to that of . Numeral 1-5 is a multi/single system selection signal source that outputs 11' when the processor is in a multiprocessor configuration, and outputs 0' when the processor is in a single processor configuration. 1-6 is a gate for exclusive use of the common bus 5 in a single processor configuration, and when the multi/single selection signal source 1-5 is 1', the output is ``0''; when it is ``0'', the output is 11; Also, when the signal IJ8 has an output, its output is 10. 1-7 is the logical sum of the output signal of the gate 1-6 and the permission signal obtained from the bus management circuit 6 via the signal R1-3. It is a gate to take.1-8 is
This is a gate for outputting a use request signal for the common bus 5 via the signal line 1-2 to the bus management circuit 6 in a multi-processor configuration, and for inhibiting output in a single-processor configuration. 1-9
is a signal source that issues a usage request for the common bus 5, and is relayed to the bus management circuit 6 by gates 1-8 in a multi-processor configuration, and output to the bus management circuit 6 by gates 1-8 in a single-processor configuration. Not done. 1-1
0 is a gate that controls whether or not to relay the internal buses 1-4 of the processor 1 to the common bus 5; when the output of the gates 1-7 is 1', the relay is relayed, and when the output of the gate 1-7 is 0', the relay is prohibited. .

Further, when the processor 1 receives a bus use prohibition signal from the bus management circuit 6 via the signal a7, it enters a wait state.
The use of internal bus 1-4 is stopped, the output of signal source 1-9 is set to 0', and 1 is output via signal line 8. The processing of the signal on the signal line 7 and the signal output on the signal line 8 are as follows:
DMA (direct) in a known single processor.

This process is similar to the process for bus requests to the processor during memory access. 6-1 is the signal line 1-2. 2
-2. 6-2 is a contention circuit that resolves contention between common bus usage requests sent via signal source 1-2.
This is a multi/single selection signal source similar to No. 5, and is set to 1' when a multiprocessor is used, and 0' when a single processor is used. 6-3 is an OR circuit, which is a gate that calculates the sum of the signal on signal line B and the output of signal source 6-2. 6-4
．． 6-5 and 6-6, the output of gate 6-3 is 11''
Only when the output of the competition circuit 6-1 is 1-5.2, respectively
-3 and 3-3, 6-7 is an OR gate that takes the sum of the use request signals on signal line 1-2, 2-2 or 3-2, and 6-8 is a signal When the output of source 6-2 is 1, output to signal @7 is prohibited and 1 signal source 6-
This is a gate that allows output to the signal line 7 when the output of the signal line 2 is 0'.

Next, we will explain the operation in a multiprocessor configuration. When using a multiprocessor, signal source 1-5 and signal source 6-2
The output of is set to 1'. In FIG. 2, when the processor 1 accesses the common memory 4, the 1g source 1-9 is set to 1'. This causes a common bus use request to be issued via gate 1-8 and signal line 1-2. Also, at this time, gate 1-6 is closed.

Upon receiving the use request signal from the signal line 1-2, the bus management circuit 6 resolves the conflict between the use requests via the signal lines 1-2.2-2.5-2, and adjusts the output of the signal source 6-2. is 1, so gates 6-3 and 6-4 . 6-5.6-6
via signal line 1-5.2-3. A permission signal is output through one of the terminals 5-6. Further, the use request signal is not sent to the signal line 7 by the gate 6-8. Processor 1 receives signal l
A permission signal is received via gate 151-3, gate 1-10 is opened by gate 1-7, and internal bus 1-4 is relayed to common bus 5 to access the common memory.

Next, the operation in a single processor configuration will be explained. At this time, in FIG. 1, it is assumed that processor 2 is not operating and only processor 1 is operating.

Also, the signal source 1-5 and signal source 6-2 in FIG.
is set to be output. When the processor 1 accesses the common memory 4, it outputs 1 from the signal source 1-9, but the gate 1-8 sends this bus use request to the signal line 1.
-2, and when the signal line 8 is in the 10 state, the gate 1-6 and gate 1-7
10 is opened and relays the internal buses 1-4 to the common bus 5, and the common memory 4 is accessed unconditionally. Also, device 3 is
When accessing the common memory 4, a bus use request is issued via the signal $5-2. The bus management circuit 6 receives this signal and selects the device 3 using the competition circuit 6-1.

At this time, the signal line 1-2 is always 0'', and the signal line 2-2 is always 0''.
2 is always 0 because processor 2 is not operating. On the other hand, gates 6-7 and 6-8 provide signal II.
7, the processor 1 is informed of the prohibition of bus use. Processor 1 puts itself into a wait state with this signal, and by setting signal source 1-9 to 01, gate 1-
After closing 102, send signal 12 to signal box 8. The bus management circuit 6 receives this signal, and the gate 6-3 and the gate 6-6
Signal II! A permission signal is sent to 5-3. In response to this, the device 3 accesses the common memory 4.

In this way, when a multiprocessor system is reduced to a single processor configuration with only one processor, the access time of the common memory and devices by the processor can be reduced by the processing time of the bus management circuit.

In the above embodiment, the local memories 1-1 and 2-1 and the processor buses 1-4 and 2-4 are not necessarily necessary, and a configuration may be adopted in which each processor accesses the common memory 4 only through the common bus 5.

〔Effect of the invention〕

According to the present invention, when a multiprocessor system is reduced to a single processor configuration with one processor, that processor exclusively uses shared devices and common memory, and a bus management circuit is used to access the devices and common memory of that processor. Since no processing is required, the access time of the processor is shortened and the performance of the processor is improved.

[Brief explanation of drawings]

Figure 1 shows the configuration a of a multiprocessor system. FIG. 2 is a circuit diagram showing the internal configuration of the processor and bus management circuit. 1...Processor 2...Processor 3...Device 4...Common memory 5...Common bus 6...Bus management circuit 1-2.2-2.3-2...Signal 11 (Common bus use request signal) 1-3.2-5.3-3...Signal line (use permission signal)
7...Signal line 8...Signal line 1-5.6-2...Signal source (multi/single system selection signal)

Claims (1)

[Claims] A plurality of processors, a shared device, and a common memory connected to a common bus, and a bus management means that resolves conflicts between bus usage requests from the processors and shared devices and grants usage permission to one usage request source. In the multiprocessor system having the above-mentioned processor and bus management means, when a multiprocessor configuration in which a plurality of processors are operating, each processor is controlled to obtain permission to use the bus via the bus management means as described above, and only one processor is allowed to use the bus. When a single processor is configured to operate, the single processor unconditionally monopolizes the common bus without going through the bus management means when there is no bus use request from the device, and the single processor monopolizes the common bus when there is a bus use request from the device. A multiprocessor system characterized by comprising means for controlling so that bus use requests are suppressed.