JPH0217820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiprocessor system, and particularly to a multiprocessor system capable of degenerating into a single processor system.

[Background of the invention]

Conventional multiprocessor systems are based on the assumption that multiple processors operate at the same time, and when processors access devices and common memory that are shared among processors, a common In order to obtain the right to use the bus, issue a usage request to the bus management circuit, obtain permission from the bus management circuit,
After that, such access was carried out via a common bus. That is, the bus management circuit resolves conflicting requests for use of a common device and common memory by a plurality of processors, and controls any one processor to use the common bus at a time.
However, if the number of processors degenerates to one,
Although this processor can monopolize shared devices and common memory, the right to use the common memory must be obtained via the bus management circuit, so the device and It has the disadvantage that it takes a long time to access the common memory and the performance is degraded when used. Incidentally, related technologies of this type include, for example, Japanese Patent Application Laid-open No. 1986-
The technique described in Japanese Patent No. 143067 is mentioned.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor system that improves the performance of a single processor system by eliminating the shortcomings in conventional multiprocessor systems where the performance deteriorates compared to a single processor dedicated system when the number of processors degenerates to one. It is in.

[Summary of the invention]

In the present invention, the processor and the bus management means are controlled so that in a multi-processor configuration in which a plurality of processors are operating, each processor obtains permission to use the bus via the bus management means, and a single processor in which only one processor is operating. When configured as a processor, the single processor unconditionally monopolizes the common bus without going through the bus management means when there is no bus use request from a device, and when there is a bus use request from a processor, the single processor's bus use request is suppressed. The multi-processor system is characterized by a multi-processor system including means for controlling the system.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing the structure of a multiprocessor system. Processors 1 and 2 have local memories 1-1 and 2-1, respectively, which are used exclusively. 3 is a device that is shared by processors 1 and 2, and 4 is a common memory that is also used by processors 1 and 2.
shared and used by 5 is a common bus to which the processors 1 and 2, devices 3, and common memory 4 are commonly connected; 6 is a bus management circuit for controlling use of the common bus 5; The bus management circuit resolves conflicts regarding requests to use the common bus 5 sent from processors 1 and 2 and devices 3 via signal lines 1-2, 2-2, and 3-2, and Select signal line 1-3,
A permission signal is sent back via either one of 2-3 and 3-3. The processor 1 or 2 that has obtained the permission signal in this way is the device 3 or the common memory 4.
can be accessed. 1-4 and 2-4 are processors 1 and 2 and local memories 1-1 and 2-, respectively.
1, and 7 is a signal line to which 1 is sent when there is a bus use request from device 3 in a single processor system. Reference numeral 8 denotes a signal line through which the processor sends a signal 1 affirming bus use permission for the device 3 in a single processor system.

FIG. 2 is a diagram showing the internal configuration of the processor 1 and the bus management circuit 6. The circuit configuration of processor 2 is also similar to that of processor 1. 1-5 is
This is a multi/single system selection signal source that outputs "1" when the processor is in a multiprocessor configuration, and outputs "0" when the processor is in the single processor configuration. 1-6 is a gate for exclusive use of the common bus 5 in a single processor configuration, and a multi/single selection signal source 1-5
When is "1", the output is "0", when it is "0", the output is "1", and when there is an output on the signal line 8, the output is "0". Reference numeral 1-7 is a gate for calculating the logical sum of the output signal of the gate 1-6 and the permission signal obtained from the bus management circuit 6 via the signal line 1-3. Reference numeral 1-8 denotes a gate for outputting a use request signal for the common bus 5 via the signal line 1-2 to the bus management circuit 6 in a multi-processor configuration, and for inhibiting output in a single-processor configuration.
Reference numeral 1-9 denotes a signal source that issues a use request for the common bus 5, which is relayed to the bus management circuit 6 by gates 1-8 in a multi-processor configuration, and relayed to the bus management circuit 6 by gates 1-8 in a single-processor configuration. is not output to. 1-10 is a gate that controls whether or not the internal bus 1-4 of the processor 1 is relayed to the common bus 5; when the output of the gate 1-7 is "1", it is relayed, and when it is "0", it is relayed. Relay is prohibited. Further, when the processor 1 receives a bus use prohibition signal from the bus management circuit 6 via the signal line 7, it enters a wait state, stops using the internal bus 1-4, and sets the output of the signal source 1-9 to "0". , further outputs 1 via the signal line 8. This signal line 7
The processing of the above signal and the signal output on the signal line 8 are similar to the processing for a bus request to a processor during DMA (direct memory access) in a known single processor. 6-1 is a conflict circuit that resolves conflicts between common bus usage requests sent via signal lines 1-2, 2-2, and 3-2, and 6-2 is a signal source similar to signal source 1-5. This is a multi/single selection signal source, and is set to "1" when using a multi-processor and "0" when using a single processor. 6-3 is an OR circuit, which is a gate that calculates the sum of the signal on the signal line 8 and the output of the signal source 6-2. 6-4, 6-5 and 6-6 are gate 6-
6-7 is a gate that outputs the output of the competition circuit 6-1 to 1-3, 2-3, and 3-3 only when the output of 3 is "1", and 6-7 is a gate that outputs the output of the competition circuit 6-1 to signal lines 1-2, 2-3, respectively.
6-8 is an OR gate that calculates the sum of the use request signals on signal source 6-2 or 3-2, and 6-8 prohibits output to signal line 7 when the output of signal source 6-2 is "1"; This is a gate that allows output to the signal line 7 when the output of -2 is "0".

Next, the operation in a multiprocessor configuration will be explained. In a multiprocessor configuration, the outputs of signal sources 1-5 and 6-2 are set to "1". In FIG. 2, when the processor 1 accesses the common memory 4, the signal source 1-9 is set to "1".
As a result, a common bus use request is issued via gate 1-8 and signal line 1-2. Also, at this time, gate 1-6 is closed. Signal line 1-2
In response to the use request signal from the bus management circuit 6,
Since the conflict between the usage requests via the signal lines 1-2, 2-2, and 3-2 is resolved, and the output of the signal source 6-2 is 1, the gates 6-3 and 6-4, 6-
Signal lines 1-3, 2-3, 3- via 5, 6-6
A permission signal is output through one of the three. Further, the use request signal is not sent to the signal line 7 by the gate 6-8. The processor 1 receives the permission signal via the signal line 1-3 and the gate 1-1 by the gate 1-7.
0 is opened and the internal buses 1-4 are relayed to the common bus 5 to access the common memory.

Next, the operation in a single processor configuration will be explained. At this time, in FIG. 1, it is assumed that processor 2 is not operating and only processor 1 is operating. Furthermore, the signal sources 1-5 and 6-2 in FIG. 2 are set to output "0". When processor 1 accesses common memory 4, signal source 1
-9 outputs 1, but when gate 1-8 does not output this bus use request via signal line 1-2 and signal line 8 is in the "0" state, gate 1-6
Gate 1-10 is opened by gate 1-7 to relay internal bus 1-4 to common bus 5, and access common memory 4 unconditionally. Also device 3
issues a bus use request via the signal line 3-2 when accessing the common memory 4. The bus management circuit 6 receives this signal and selects the device 3 using the competition circuit 6-1. At this time, the signal line 1-2 is always at "0", and the signal line 2-2 is always at "0" because the processor 2 is not operating.
On the other hand, gates 6-7 and 6-8 inform processor 1 via signal line 7 that bus use is prohibited. The processor 1 puts itself into a wait state by this signal, sets the signal source 1-9 to "0", closes the gate 1-10, and then sends 1 to the signal line 8. Upon receiving this signal, the bus management circuit 6 sends a permission signal to the signal line 3-3 through the gates 6-3 and 6-6. In response to this, the device 3 accesses the common memory 4.

In this way, when a multiprocessor system is reduced to a single processor configuration with only one processor, the access time of the common memory and devices by the processor can be reduced by the processing time of the bus management circuit.

Note that in the above embodiment, the local memory 1-
1 and 2-1 and processor bus 1-4 and 2-
4 is not necessarily necessary, and a configuration may be adopted in which each processor accesses the common memory 4 only through the common bus 5.

〔Effect of the invention〕

According to the present invention, when a multiprocessor system is reduced to a single processor configuration with one processor, that processor exclusively uses shared devices and common memory, and a bus management circuit is used to access the devices and common memory of that processor. Since no processing is required, the access time of the processor is shortened and the performance of the processor is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system, and FIG. 2 is a circuit diagram showing the internal structure of a processor and a bus management circuit. 1...Processor, 2...Processor, 3...Device, 4...Common memory, 5...Common bus, 6...
... Bus management circuit, 1-2, 2-2, 3-2 ... Signal line (common bus use request signal), 1-3, 2-3,
3-3... Signal line (use permission signal), 7... Signal line, 8... Signal line, 1-5, 6-2... Signal source (multi/single system selection signal).

Claims (1)

[Claims] 1. A plurality of processors, shared devices, and common memories connected to a common bus, and a bus management means that resolves conflicts between bus usage requests from the processors and shared devices and grants usage permission to one usage request source. In the multi-processor system having the above-mentioned processor and bus management means, when a multi-processor configuration in which a plurality of processors are operating, each processor is controlled to obtain permission to use the bus via the bus management means as described above, and only one processor is allowed to use the bus. In a single processor configuration in which the single processor operates, the single processor unconditionally monopolizes the common bus without going through the bus management means when there is no bus use request from the device, and when there is a bus use request from the device, the single processor A multiprocessor system characterized by comprising means for controlling bus usage requests of processors to be suppressed.