JPS6118046A - Microcomputer - Google Patents

Abstract

PURPOSE:To attain a microcomputer system with high reliability by using a detection circuit for discordance between an output latch and the terminal value and two microcomputers having the same program. CONSTITUTION:The output is inhibited to an output driver 13 by the signal value of a mode control signal line 15, and the signal impressed to a mode selection line is given to the line 15. Therefore the driver 13 becomes active in an execution mode of a microcomputer and then inactive in a fault detection mode. While a discordance detecting circuit 14 compares the bit values corresponding to an output latch 5 and an output terminal 8 with each other in a fault detection mode. If the discordance is detected, a fault detection signal is delivered to a malfunction detecting signal line via a discordance signal line 16. Thus it is possible to attain a microcomputer system of high reliability with two microcomputers having the same program.

Description

[Detailed description of the invention] Industrial applications The present invention is a 2-basis system for detecting failures caused by malfunctions or failures. It relates to a microcomputer that can be

Conventional configurations and their problems In recent years, microcomputers built on LSIs have come into widespread use as controllers for various devices. CPU and ROM are installed on the LSI.

A microcomputer that has both RAM and IO can significantly downsize the device, and its low cost makes it very useful.

On the other hand, from the viewpoint of high reliability of microcomputer-applied equipment, it is a major issue to detect malfunctions of microcomputers due to failures, disturbance noise, etc., and to prevent abnormal operations of the equipment.

The current situation is that conventional microcomputers do not have a failure testing function as LSIs.

The signal arrangement diagram of a typical microcomputer and its output circuit will be explained below.

Figure 1 shows the signal arrangement diagram of a conventional microcomputer, where 10o is the microcomputer, 1 is the reset signal line, 2a and 2b are the clock oscillation element lines, 3 is the input signal line, and 4 is the output signal line. be. A reset signal generated by an integrating circuit using C, R, etc. that generally detects the rise of the power supply is applied to the reset signal line 1.
The microcomputer 100 is brought into an initial state and starts execution. Generally, a crystal resonator or a ceramic oscillation element is connected to the clock oscillation element lines 2a and 2b to generate a reference clock for the microcomputer 1oO.

Looking at the operation of the microcomputer 100 from a macro perspective, it inputs data from the input signal line 3, executes arithmetic processing,
It can be said that the result is output to the output signal line 4.

FIG. 2 shows an output circuit of a conventional microcomputer, in which 6 is an output latch, 6 is an input signal line of the output latch, 7 is an output driver, and 8 is an output terminal. 6
The output latch input signal line is generally the internal data bus of the microcomputer. The data on the output launch input signal line 6 is latched to the output launch 6 by an output latch signal (not shown) generated when an output command is executed. The driver number 7 is a large-capacity L
Necessary to drive the SI external circuit.

As shown above, conventional microcomputers do not have any measures against failures or malfunctions in terms of hardware.
It is common for software to provide some measure of troubleshooting.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a microcomputer as a component of a highly reliable microcomputer system capable of detecting failures.

Structure of the Invention The present invention provides an output driver having an inactive state, a means for making the output driver inactive in an LSI operation mode, a mismatch detection circuit that compares data between an output latch and a terminal, and an LSI It is a microcomputer equipped with a means for outputting to the outside.
Two microcomputers with different operating modes constitute a highly reliable microcomputer/computer system.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a signal arrangement diagram of a microcomputer in an embodiment of the present invention. In FIG. 3, a reset signal line 1, clock oscillation element lines 2a and 2b,
The 0 input signal line and the 4 output signal line are the same as in the conventional example shown in FIG. 200 is a microcomputer, 9 is a mode selection line for specifying whether the operation mode of the microcomputer 200 is execution mode or fault inspection mode, 10 is a reset synchronization line, 11 is a clock synchronization line, 1
2 is a malfunction detection line.

The operation of the microcomputer 200 of the present invention configured as described above will be described below.

The microcomputer 200 operates differently depending on the state of the mode selection line 9. For example, when the mode selection line has a logic value of "1", the microcomputer 200 is in the execution mode, and when the mode selection line has a logic value of "0", it is in the failure detection mode.

Page 6 <Operation in execution mode> In execution mode, data on the input signal line 3 is input, arithmetic processing is performed, and the result is output to the output signal line 4, as in a conventional microcomputer. It differs from conventional microcomputers in this respect.

(,) The signal generated by the level of the reset signal line 1 is synchronized with the internal clock, and is output to the reset synchronization line 1o, and the signal on the reset synchronization line 10 is used as its own reset signal.

[Yes]) The clock generated by the oscillation element connected to the clock oscillation element lines 2a and 2b is outputted to the clock synchronization line 11, and the signal on the clock period line 11 is used as its own clock signal.

(C) The malfunction detection signal line 12 enters the input mode, and when the input signal becomes active, failure processing is executed by means of an interrupt or the like.

<Operation in fault detection mode> In fault detection mode, the data on input signal line 3
In this mode, the result of arithmetic processing is set in the output latch, but the drive to the terminal is not executed, and the output latch data of the device itself is compared with the terminal data to detect a failure. That is, (a) IJ upper set period line 10. The signals applied to the clock synchronization line 11 are respectively referred to as a reset signal and a clock signal.

(b) Prohibit output of the output latch data to the output signal line 4, compare the values of the output latch and the output signal line 4, and generate a mismatch detection signal. When a mismatch detection signal is generated, a fault signal is output to the malfunction detection line 12.

FIG. 4 shows high tf by the microcomputer of the present invention.
This is an example of the configuration of an ifW microcomputer system.

In FIG. 4, microcomputer 20OA is in execution mode, and microcomputer 200B is set in failure detection mode.

In other words, the key point of the present invention is to input the same input data to two microcomputers, to perform the same (7) arithmetic processing, to have only one microcomputer output the processing results, and to have the other microcomputer output the processing result. By comparing its own arithmetic processing results with the terminal data as the processing results of other microcomputers, it detects the occurrence of a failure, notifies the microcomputer in execution mode of the occurrence of a failure, and takes countermeasures against the failure. By doing so, the aim is to construct a highly reliable microcomputer system.

FIG. 6 is an example of an output circuit and a discrepancy detection circuit of a microcomputer according to the present invention.

In FIG. 5, the output driver 13 is prohibited from outputting according to the signal value of the mode control signal line 16. The mode control signal line 15 is supplied with the signal applied to the mode selection a9 in FIG. That is, when the microcomputer is in execution mode, the output driver is inactive, and in failure detection mode, it is inactive. The mismatch detection circuit 14 is
When in fault detection mode, output latch 6 and output terminal 8
Compare the corresponding bit values of , and if a mismatch is detected,
A failure detection signal is outputted to the malfunction detection signal line shown in FIG. 3 via the mismatch detection signal line 16.

9A=.

FIG. 6 shows a specific example of the configuration of the mismatch detection circuit. In the figure, 5a,! 5b, 5c and sa, sb.

8C are signal lines for corresponding bit values of the output latch 6 and the output terminal 8, respectively. Although the output of the mismatch detection circuit is not shown in the figure, it is usually gated with a specific clock of the microcomputer in consideration of the delay with respect to the output latch of the terminal data.

FIG. 7 is an example of a mismatch detection circuit having an output circuit and a mask function of a microcomputer according to the present invention.

The circuit shown in FIG. 7 differs from the circuit shown in FIG. 5 in that a mask register 17 is introduced and that the mismatch detection circuit 18 becomes slightly more complex. The mask register 17 is set by a microcomputer instruction, and the output latch 5 is set depending on the state of the mask register.
It is possible to set a field in which the value of the output terminal 8 and the value of the output terminal 8 are not compared.

FIG. 8 shows a specific example of the configuration of the mismatch detection circuit 18 shown in FIG. In the figure, 6a to 5c, 8a to 8C10 vanes and 17a to 17c are respectively output latch 5° output terminals 8. This is a signal line for the corresponding bit value of the mask register 17.

The reason for introducing the mask register 17 is to prohibit comparison when the values of the output latch and the output terminal are different in the microcomputer in the execution mode. For example, if the output signal line is directly connected to the transistor pace and driven, or in input mode when the output port is designed as an input/output port, it is necessary to inhibit comparison using a mask register.

Effects of the Invention The microcomputer of the present invention has high reliability by adding an output latch, a mismatch detection circuit with a terminal value, and a small amount of circuitry to eliminate it. It becomes possible to configure a microcomputer system. Moreover, the increase in hardware due to the present invention is small compared to the entire microcomputer, and of course, the increase in hardware for a single microcomputer is small.
11+,-.

However, it can be controlled in the same way as before, and its practical value is great.

[Brief explanation of the drawing]

Figure 1 is a signal arrangement diagram of a conventional microcomputer, Figure 2 is an output circuit diagram of a conventional microcomputer, and Figure 3 is a diagram of a conventional microcomputer's output circuit.
The figure is a signal arrangement diagram of a microcomputer according to an embodiment of the present invention, FIG. 4 is a configuration diagram of a highly reliable microcomputer system according to another embodiment of the present invention, and FIG. 5 is an output circuit and a discrepancy detection circuit according to the present invention. 6 is a circuit diagram showing a specific circuit of the mismatch detection circuit of FIG. 5, and FIG. 7 is another embodiment of the mismatch detection circuit having an output circuit and a mask function according to the present invention. FIG. 8 is a circuit diagram showing a specific circuit of the mismatch detection circuit of FIG. 6... Output launch, 8... Output terminal,
9...Mode selection line, 12...Malfunction detection line, 13...Output driver, 14...
... Mismatch detection circuit, 17 ... Mask register, 18 ... Mismatch detection circuit, 200.20O
A, 200B...Microcomputer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 83 Figure 4 2θθB Figure 5 Figure 6

Claims (2)

[Claims] (1) an output latch, a driver having an inactive state for driving the output latch data to an output terminal, LSI operation mode setting means, and means for making the driver inactive in one of the LSI operation modes; , comprising a circuit for comparing data at terminals corresponding to the output latch and detecting data mismatch, and means for outputting the mismatch detection circuit output to the outside of the LSI when the driver is in an inactive mode. microcomputer. (2) The mismatch detection circuit of the terminal corresponding to the output latch is
2. The microcomputer according to claim 1, having a masking function for specifying a portion on which comparison is not to be performed.