JPS61180353A - Data transfer control system - Google Patents

Abstract

PURPOSE:To reduce greatly the processing quantity needed for transfer of data and to improve the circuit throughput, by attaining the transfer of plural frames with just a single command through a circuit control channel of a controller. CONSTITUTION:When data equivalent to four frames of buffers (b), (c), (d) and (e) of a main memory 2 are transferred, a CPU 1 sets a single piece of control indication information to the buffer (a). Then the orders of transfer and the chain states of buffers are set to the chain areas of buffers (b-e). Then a circuit control channel 3 is started and reads and decodes the contents of the buffer (a). Then the channel 3 detects a transfer indication to read out the buffer (b) and knows the buffer (c) of the next transfer data from the chain information of the buffer (b) after the contents of the buffer (b) are transferred in the form of the 1st frame. Then the buffer (c) is read out and transferred as the 2nd frame. Hereafter buffers (d) and (e) are read out and transferred as the 3rd and 4th frames respectively.

Description

[Detailed description of the invention] 〔table of contents〕 The present invention will be explained in the following order.

[Industrial application field]

[Prior art] [Eight points to be solved by the invention] Means for solving problem C] (Figure 1) [Operation] [Example] Explanation of configuration (Figures 2 and 3) Description of transfer operation (Figures 4 and 5) [Effects of the invention] [Field of industrial application] The present invention relates to a data transfer control method for transferring data from a controller to a partner device such as a terminal via a line. In particular, the present invention relates to a data transfer control system in which a line control channel of a controller can transfer multiple frames of data in response to a command.

A line 6 connects the controller CT and the plurality of terminals 5a, 5b-.
A data transfer system as shown in FIG. 6(A), in which data is transferred by connecting the two, is widely used. For example, L A N
(Local Area Network) etc., data is transferred from the controller CT via the line 6 in accordance with requests from the terminals 5a and 5b, and the controller CT is also connected to a host computer (not shown), etc.
In some cases, data may be transferred to the line 6 by communicating with a host computer or the like.

The controller CT of such a data transfer system includes at least a main processor 1, its main memory 2, a line connection channel 3, and a common bus 4, and the line connection channel 3 connects the processor 30 and the common bus control unit. 3
1, a local memory 32, a line control section 33, and an internal bus 34. The line connection channel 3 has a processor 30, which independently reads transmission data from the main memory 2 via the common bus 4 from the common bus control unit 31, edits it frame by frame, and sends it to the line 6 from the line control unit 33. It is configured to transfer the data to terminals 5a to 5n configured with personal computers or the like. As shown in FIG. 7, one frame is composed of a terminal address A, transmission control information C, and transmission data SD, and has a maximum size of 1.5 Kbytes in a LAN.

[Conventional technology]

In order to transfer such l frames, the operation as shown in FIG. 8 has conventionally been performed within the controller CT.

(2) At the time of transfer, the main processor 1 prepares the control instruction information shown in FIG. 6(B) in the main memory 2 in the buffer a. Transmission data for l frames is prepared in advance in buffer b. The control instruction information for buffer a is shown in Figure 6 (B
), the data send command, the terminal address A to be transferred, the start address of the send data (in this example, the start address of buffer b), the send length, and the status (used when the transfer is completed as described later) The main processor 1 sets control instruction information other than the status of the buffer a via the common bus 4 when transferring the contents of the buffer a.

(2) Next, the main processor 1 interrupts the line control channel 3 via the common bus 4 and activates a command.

This command includes the start address of buffer a.

■ As a result, the line control channel 3 starts operating, and the processor 30 decodes this command via the common bus control unit 31 and internal bus 34, and the common bus control unit 3
DMA (Direct Access M
ode) mode, the contents of the buffer a of the main memory 2 are read out and transferred to the local memory 32 via the common bus control unit 31.
It is decoded after being stored in .

Processor 3 is ordered to send data by decoding the contents of buffer a, the transfer destination is terminal A, and the storage area (buffer b in this example) and length of the data to be sent can also be known from the start address and send length. Can be done.

■ Next, the processor 30 reads the contents of buffer b of the main memory 2 in the DMA mode via the common bus 4 for the transmission length from the start address given by the common bus control unit 31 (in this example, the start address of buffer b). The data is read out and stored in the local memory 32 via the common control unit 31.

(2) Furthermore, the processor 30 edits one frame and transmits one frame of data to the line 6 from the line control section 33, as shown in FIG.

(2) As a result, for example, the terminal 5a is designated, and (1) when the frame worth of transfer data is normally received, a response R1 is sent back. The response R1 is given to the processor 30 via the line 6, line control section 33, and internal bus 34, and normal reception is detected.

(2) Then, the processor 30 writes a normal end of data transfer to the status area of the buffer a of the memory 2 via the common bus 24 from the common bus control unit 31 in the DMA mode.

■Furthermore, the processor 30 notifies the main processor l of an interrupt via the common bus 4 from the common bus control unit 31, and
Completes frame transfer. Main processor 1 looks at the contents of the status area of buffer a in memory 2, and
Detects successful completion of data transfer.

In this way, in conventional data transfer control, one command (control instruction information) corresponds to the transfer of one frame.

[Problem that the invention seeks to solve]

Therefore, in the conventional method, interrupts from the main processor 1, command DMA read, data DMA read, status DMA write, and main processor l
The transfer of one frame is completed in the sequence of interrupting the DMA.
3 times main processor 1 and line control channel 3
This required a large amount of processing time.

On the other hand, in order to transfer a large amount of data such as an image, it is not enough to transfer it in one frame, but it is necessary to divide it into multiple frames and transfer it.

Therefore, in the conventional transfer control system, the number of frames is required to be multiplied by the amount of processing for one frame described above, and there is a problem that high-speed data transfer is not possible and the throughput of the line is limited.

On the other hand, a method can be considered in which the main processor 1 uses a command chain method to reduce the number of interrupts for each frame transfer for one command, one frame.
Since the number of ``processing'' is not reduced, the amount of processing cannot be reduced to that extent, and a similar problem occurs.

The present invention significantly reduces the amount of processing required for data transfer,
The purpose of this invention is to provide a data transfer control method that can improve line throughput.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

The present invention is based on removing the conventional restriction of transferring one frame for one command (control instruction information) and making it possible to transfer a plurality of frames with one command.

For example, to transfer 4 frames of buffers b, c, d, and e, one command is set in buffer a as before, but each buffer is Chain information cb, cc, cd, and ce indicating the chain status between buffers (between buffers) is added and stored.

Then, the aforementioned line control channel 3 reads the command in buffer a, decodes it, reads out the contents of buffer b, transfers one frame of data from the transmitted data, decodes the added chain information cb, and then transfers the command. Obtain the buffer C of the transmission data to be sent, read the contents of the high sofa C1
Transfer the data of the frame, and then do the same in the buffer d,
The frame is transferred within e.

[Effect]

In the present invention, after the main processor 1 sets a command to buffer a, the line control channel repeats reading and transferring to buffers c, d, and e one after another based on the chain information after reading and transferring buffer b, for example, 4 frames. It only takes 2 interrupts and 6 DMAs to transfer the amount. In the conventional example, it takes 8 interrupts and 12 DMAs to transfer 4 frames, and even with command chaining, it takes 2 interrupts and 12 DMAs.
Because the number of times is 12, the amount of processing can be significantly reduced, and the throughput of the line can be improved.

〔Example〕

FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a configuration diagram of a data buffer in FIG. 2.

In the figure, the same parts as those shown in Fig. 6 and Fig. 1 are indicated by the same symbols, and CFA is a chain area provided in each data buffer b, c, d, and e. , a chain designation flag CF indicating whether there is a chain with the next buffer, and the start address C of the next chain buffer.
A and the length L of the next buffer are stored, DA
is the transmission data area, and each data buffer bSc,
d and e to store transmission data SD to be transmitted in one frame. Therefore, buffers b, c, d, and e used as data buffer sofas are composed of a chain area CFA and a transmission data area DA, and the processor 30 of the line control channel 3 is composed of blocks b, c, d.

It has a function to separate the contents of the chain area CFA and analyze the chain information when e is read.

Next, the operation of the embodiment configuration shown in FIGS. 2 and 3 will be explained with reference to FIG. 4, a transfer operation explanatory diagram, and FIG. 5, a transfer sequence explanatory diagram. Here, data buffers b, c, dX
An example in which four frames of e are transferred will be explained.

(2) At the time of transfer, the main processor 1 prepares the control instruction information (command) shown in FIG. 6(B) in the main memory 2 in the buffer a. The control instruction information for buffer a is shown in Figure 6 (
B), the data send command, the terminal address to be transferred, the start address of the send data (in this example, the start address of buffer b), the send length (length of buffer b), and the status (transfer When the main processor 1 transfers the contents of the buffers b-e, the main processor 1 sends control instruction information other than status to the buffer a via the common bus 4.

Next, the main processor 1 sets chain information in each chain area CFA of the data buffer b z e prepared in advance via the common bus 4 . for example,
Chain specification flag CF for data buffers b, c, d
is "1" indicating that there is a chain, the chain specification flag CF of data buffer e is "0" indicating that there is no chain, and the next chain address CA of data buffers b, c, and d is the beginning of data buffers c, d, and e, respectively. To set the address to the next buffer length of data buffers b, c, ..d, write the length of data buffers c, d, .e, respectively.

In this way, data buffers bXc, d, and e have b
-e A chain configuration is made in the order of c→d→e.

(2) Next, the main processor 1 interrupts the line control channel 3 via the common bus 4 and activates a command.

This command includes the start address of buffer a.

■ As a result, the line control channel 3 starts operating, and the processor 30 decodes this command via the common bus control unit 31 and internal bus 34, and the common bus control unit 3
DMA (Direct Access M
ode) mode, the contents of the buffer a of the main memory 2 are read out and transferred to the local memory 32 via the common bus control unit 31.
It is decoded after being stored in .

Processor 3 is instructed to transmit data by decoding the contents of buffer a, and the transfer destination is terminal A, and the storage area and length of buffer b can also be known from the start address and transmission length.

■ Next, the processor 30 reads the contents of buffer b of the main memory 2 in DMA mode via the common path 4 for the transmission length from the start address given by the common bus control unit 31 (in this example, the start address of buffer b). The data is read out and stored in the local memory 32 via the common control unit 31.

■Furthermore, the processor 30, as shown in FIG.
Edit one frame from the transmission data of
1 frame of data is sent to line 6.

(2) As a result, when the terminal 5a is designated, for example, and successfully receives transfer data for one frame, it returns a response R1. The response R1 is given to the processor 30 via the line 6, line control section 33, and internal bus 34, and normal reception of frame 1 is detected.

■ Next, the processor 30 analyzes the contents of the chain area CFA of the buffer b of the local memory 32, checks whether there is a chain based on the chain designation flag CF, detects the presence of a chain, sets the next chain address CA as the first address, and sets the next chain address CA as the first address. Step with buffer length L as length■
Similarly, the contents of the buffer C of the main memory 2 are read out in the DMA mode and stored in the local memory 32.

■ Similar to step ■, the processor 3o edits one frame using the transmission data in the buffer C, and
3 transmits the second frame data to line 6.

(2) When the terminal 5a normally receives the signal in the same way as in step (2), the processor 30 detects this based on the response R2.

[Phase] Next, the processor 30 processes the chain area CF of the buffer C of the local memory 32 in the same way as Ste.
Analyze A, then set the chain address CA as the first address, set the next chain address CA as the length, and read out the contents of bar d in the main memory 2 in the DMA mode in the same manner as in steps ■ and ■. Store it in the local memory 32.

(2) Similar to steps (2) and (2), the processor 30 edits one frame using the transmission data in the buffer d, and transmits the third frame data to the line 6 from the line control unit 33.

@ When the terminal 5a receives the signal normally in the same way as in steps (2) and (2), the processor 30 detects this based on the response R3.

0 Similar to Step ■, [Phase], Proce Nosa 30 is
Chain area CF of buffer d in local memory 32
Analyze A, then read the contents of buffer e in main memory 2 in DMA mode using chain address CA as the first address and buffer length L as the length in the same manner as in steps ■, ■, [phase]. , and stored in the local memory 32.

(2) Similar to steps (2), (2), and (2), the processor 30 edits one frame using the transmission data in the buffer e, and transmits the fourth frame data to the line 6 from the line control unit 33.

[Phase] When the terminal 5a receives the signal normally in the same way as in steps ①, ①, and @, the processor 30 detects this based on the response R4.

[Phase] Similar to step ■, [phase], ■, processor 3
0 analyzes the chain area CFA of the buffer e in the local memory 32, and when detecting the absence of a chain, the processor 30 transfers data from the common bus control unit 31 to the status area of the buffer a in the memory 2 via the common bus 4. Write normal completion in DMA mode.

■Furthermore, the processor 30 notifies the main processor 1 of an interrupt via the common bus 4 from the common path control unit 31,
Transfer of 4 frames is completed.

The main processor l looks at the contents of the status area of the buffer a of the memory 2 and detects that the data transfer has been completed normally.

In this way, the buffers b, c, d of the main memory 2
, e, main processor l sets one piece of control instruction information in buffer a, and stores the transfer order and buffer connections ( chain condition),
If line control channel 3 is started, line control channel 3
reads the contents of buffer a of main memory 2, decodes it, detects a transfer instruction, reads buffer b of main memory 2, and transfers the contents of buffer b as the first frame.
The buffer for the next transfer data is known from the chain information of buffer b, and buffer C is read and transferred as the second frame. Thereafter, buffers d and e are similarly read and transferred as the third and fourth frames. The transfer completion is written to the status of the controller, the transfer operation is ended, and an interrupt is notified to the main processor.

This transmission data is obtained from an external storage device (not shown) provided in the controller CT or a host computer, and is stored in the main memory 2.

In the above-described embodiment, the transfer of four frames was explained as an example, but the transfer of a plurality of frames may be sufficient, and the structure of the chain information is not limited to the embodiment.

Although the present invention has been described above using one embodiment, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As described above, according to the present invention, the amount of processing required to transfer data for a plurality of frames can be significantly reduced, and the throughput of the line can therefore be significantly improved. In particular, a large amount of image information can be transferred at high speed over a LAN, and the waiting time on the receiving side is also significantly reduced.

Also, the configuration for this can be done by chaining the data,
It also has the advantageous practical effect of being able to realize functions easily and at low cost.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a configuration diagram of the data buffer configured in Fig. 2, and Fig. 4 is a transfer operation of the configuration in Fig. 2. FIG. 5 is an explanatory diagram of the transfer sequence of the configuration shown in FIG. 2, FIG. 6 is a diagram of the configuration of the data transfer system, FIG. 7 is a frame format diagram, and FIG. 8 is an explanatory diagram of conventional data transfer operation. It is. In the figure, CT--controller, l-main processor, 2-main memory, 3-line control channel, 5a, 5b one terminal, 6-line, a, b,, cXd, e-buffer, cb, ccX cd. , ce-chain information.

Claims (1)

[Scope of Claims] A main processor, a memory in which control instruction information and data to be transmitted are stored, and a memory activated by the main processor to read and decode the control instruction information in the memory and to transmit data to be transmitted in the memory. a line control channel for reading and transmitting transmission data to the line in frame units, and storing a plurality of pieces of transmission data corresponding to one frame with chain information added to the memory;
The line control channel reads the transmission data from the memory by decoding the control instruction information, transfers it to the line frame by frame, and then determines the next transmission from the memory based on the chain information added to the read transmission data. A data transfer control method characterized by reading data and transferring it to the line in units of frames.