JPS61177795A - Connection for multiterminal lead - Google Patents

Connection for multiterminal lead

Info

Publication number
JPS61177795A
JPS61177795A JP1907285A JP1907285A JPS61177795A JP S61177795 A JPS61177795 A JP S61177795A JP 1907285 A JP1907285 A JP 1907285A JP 1907285 A JP1907285 A JP 1907285A JP S61177795 A JPS61177795 A JP S61177795A
Authority
JP
Japan
Prior art keywords
terminal
lead
external
external lead
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1907285A
Other languages
Japanese (ja)
Inventor
鷲見 弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP1907285A priority Critical patent/JPS61177795A/en
Publication of JPS61177795A publication Critical patent/JPS61177795A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は薄膜KLママトリクスディスてレイパネルや液
晶マトリクス型ディスプレイバネμなどの製造に利用さ
れるもので、絶縁基板上に形成された多数の端子と、こ
の端子と対応する外部のフレキンプルリードの外部リー
ドとを電気的及び機従来の技術 薄膜ICLや液晶のマトリクス型ディスプレイパネルは
マ) IJクス型の多数の電極の外部取出し用端子をガ
ラス基板上に微小なピ・ソチで一連に形成し、この多数
の各端子に別のフレキシブルリードに形成した外部リー
ドを半田付けして電極の外部取出しを行うのが一般的で
ある。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used for manufacturing thin film KL matrix display panels, liquid crystal matrix display springs, etc. This terminal and the corresponding external lead of the external flexible pull lead are electrically and mechanically connected to the conventional thin film ICL and liquid crystal matrix display panels. It is common to form a series of small pins and sockets on the top of the electrode, and to each of these many terminals, external leads formed as separate flexible leads are soldered to take the electrodes out.

ここで薄膜KLママトリクスディスプレイパネルの構造
例を、第8図及び第9図を参照して説明する。尚、第8
図の左半分はX方向の断面図を示し、右半分はX方向と
直交するY方向の断面図を示す。図において、1は透明
なガラス基板、2はガラス基板1上に形成されたマトリ
クス型KL素子、8はガラス基板1上でKL素子2を気
密封止する逆皿状のカバーガラス、4はFiL素子2の
電極外部取出し用フレキシブルリードである。EL素子
2における5、5・・・・・・はガラス基板1上に工。
An example of the structure of a thin film KL matrix display panel will now be described with reference to FIGS. 8 and 9. Furthermore, the 8th
The left half of the figure shows a cross-sectional view in the X direction, and the right half shows a cross-sectional view in the Y direction orthogonal to the X direction. In the figure, 1 is a transparent glass substrate, 2 is a matrix type KL element formed on the glass substrate 1, 8 is an inverted dish-shaped cover glass that hermetically seals the KL element 2 on the glass substrate 1, and 4 is a FiL This is a flexible lead for taking out the electrode of element 2 to the outside. 5, 5, . . . in the EL element 2 are formed on the glass substrate 1.

T、Oを蒸着法等でX方向に所定ピ、ソチで多数のスト
ライプ状に形成した透明電極、6は透明電極5上を覆う
ytoi4の透明な第1絶縁層、7は第1の絶縁層6上
に形成したZnS:Mn等の発光層、8は発光層7上を
覆うY、01等の透明な第2絶縁層、9.9・・・・・
・は第2絶縁層8上に前記X方向と直交するY方向に所
定ピ、’IIチで多数のストライプ状に形成したAt蒸
着膜による背面電極である。
A transparent electrode formed of T and O in a large number of stripes at predetermined intervals in the X direction by vapor deposition or the like, 6 a transparent first insulating layer of ytoi 4 covering the transparent electrode 5, 7 a first insulating layer 6, a light emitting layer such as ZnS:Mn formed on the light emitting layer 7; 8, a transparent second insulating layer such as Y, 01, etc., covering the light emitting layer 7; 9.9...
* is a back electrode made of an At vapor-deposited film formed on the second insulating layer 8 in a large number of stripes at predetermined pitches in the Y direction perpendicular to the X direction.

KL素子2の各電極5・・・・・・、9・・・・・・は
ガラス基板1の周辺部まで延設されて、ガラス基板1の
周辺部に定ピ・ソチで形成した多数の端子10.10・
・・・・・に重畳されて接続される。端子10.10・
・・・・・はTi 、At、Niなどの金属の多層体で
ある。
Each of the electrodes 5, 9, . Terminal 10.10・
It is superimposed on and connected to .... Terminal 10.10・
. . . is a multilayer body of metals such as Ti, At, and Ni.

カバーガラス3は電4i!5・・・・・・、9・・・・
・・の端子近くを横切る位置に絶縁性接着剤11を介し
てガラス基板l上に固着され、このカバーガラス8とK
L素子2の間にシリコンオイル等の絶縁性保護流体12
が封入される(特公昭5’7−47559号公報)。フ
レキシブルリード4はポリイミド等の絶縁性のフレキシ
ブルなフィルム13に端子10゜10・・・・・・と同
一ピ、フチで多数の銅箔等よりなる外部リード14.1
4・・・・・・を被着形成したもので、外部リード14
.14・・・・・・の端部が対応する端子10.10・
・・・・・に半田15.15・・・・・・にて電気的及
び機械的に接続される。
Cover glass 3 is electric 4i! 5..., 9...
... is fixed on the glass substrate l via an insulating adhesive 11 at a position crossing near the terminals,
An insulating protective fluid 12 such as silicone oil is placed between the L elements 2.
is enclosed (Japanese Patent Publication No. 5'7-47559). The flexible lead 4 is an insulating flexible film 13 made of polyimide or the like, and the external lead 14.1 is made of a large number of copper foils etc. at the same pitch and edge as the terminal 10°10...
4... is formed by adhering to the external lead 14.
.. The end of 14... corresponds to the terminal 10.10.
. . . are electrically and mechanically connected by solder 15, 15 . . . .

フレキシブルリード4の外部リード14.14・・・・
・・と端子10.10・・・・・・の半田付けは、第1
0図及び第11図に示すように行われている。先ず第1
0図に示すように、ガラス基板1を安定した台16上に
載置する。一方フレキンブA/ IJ−ド4の各外部リ
ード14.14・・・・・・の端部上に予備半田15.
15・・・・・・を電気メ・フキ法等で付着しておいて
、このフレキシブルリード4を台16上のガラス基板1
上に位置合せして重ね、第11図に示すように各端子1
0.10・・・・・・上に対応する外部リード14.1
4・・・・・・を予備半田15.15・・・・・・を介
して重ねる。そしてフレキシブルリード4上に石英板1
7を載せて台16とでもってフレキシブルリード4をガ
ラス基板l上に抑圧(静圧)しておく。この状態で石英
板17の上方から赤外線ビーム18を石英板17を通過
させて照射しスキャンさせて、予備半田15.15・・
・・・・を順次に加熱し溶融させて、端子10.10・
・・・・・と外部リード14.14・・・・・・を半田
付けする(電子材料1975年2月P、125〜180
)。
External lead 14 of flexible lead 4.14...
...and terminal 10.10...... soldering is done in the first step.
This is done as shown in Figures 0 and 11. First of all
As shown in FIG. 0, the glass substrate 1 is placed on a stable stand 16. On the other hand, apply preliminary solder 15. on the ends of each external lead 14.
15 .
Align and overlap each terminal 1 as shown in Figure 11.
0.10...External lead 14.1 corresponding to above
4... are overlapped via preliminary solder 15.15...... And the quartz plate 1 is placed on the flexible lead 4.
7 is placed on it and the flexible lead 4 is pressed (static pressure) onto the glass substrate l using the stand 16. In this state, the infrared beam 18 is passed through the quartz plate 17 and scanned from above the quartz plate 17, and the preliminary solder 15.15...
. . . are sequentially heated and melted to form terminals 10.10.
...... and external leads 14.14...... (Electronic Materials February 1975 P, 125-180
).

ところで、上記赤外線加熱による半田付は方法は赤外線
ビーム18の熱エネルギーの内のガラス基板1から銅板
等の台16を伝って外部に逃げるロス分が多くて加熱効
率が悪いため、赤外線ビーム18のパワーを必要以上に
上げているが、そのためにフレキシブルリード4が過熱
により伸びて外部リード14が端子10から位置ずれを
起したり、端子10から外部リード14が浮き上って両
者間の半田付は性が悪くなることがあって、半田付けの
信頼性が悪く、製品の歩留りを悪くしていた。
By the way, in the method of soldering using infrared heating, a large amount of the thermal energy of the infrared beam 18 escapes from the glass substrate 1 to the outside through the base 16 such as a copper plate, resulting in poor heating efficiency. The power is increased more than necessary, but this may cause the flexible lead 4 to stretch due to overheating, causing the external lead 14 to become misaligned with the terminal 10, or the external lead 14 to lift up from the terminal 10, causing soldering between the two. However, the soldering reliability was poor and the product yield was poor.

また−組の端子10と外部リード14を接続する予備半
田15の量が少ないと上記理由による半田付は不良がよ
り発生し易いので、予備半田15の厚さdを大き目にす
る必要があった。しかし半田厚dが大きいと、端子10
と外部リード14を押圧して半田付けする際に、溶融半
田が槓に食み出して、隣接する端子−リード間の半田と
接触し、半田ブリッジによるショート不良が発生する危
険があって、尚更に歩留りを悪くしていた。
Furthermore, if the amount of the preliminary solder 15 used to connect the terminals 10 and the external leads 14 of the - group is small, defects are more likely to occur in soldering due to the above reasons, so it was necessary to increase the thickness d of the preliminary solder 15. . However, if the solder thickness d is large, the terminal 10
When pressing and soldering the external lead 14, there is a risk that the molten solder will protrude into the ram and come into contact with the solder between the adjacent terminal and lead, causing a short circuit failure due to a solder bridge. The yield was getting worse.

問題点を解決するための手段 本発明は絶縁基板上の端子とフレキシブルリードの外部
リードとの赤外線加熱による半田付けの際に、前記端子
と外部リードとを一部に対向しない部分を設けて重ね合
わせて、半田付けするようにしたことを特徴とする。
Means for Solving the Problems The present invention provides a method in which, when soldering a terminal on an insulating substrate and an external lead of a flexible lead using infrared heating, the terminal and the external lead are overlapped by providing a portion where they do not face each other. Additionally, it is characterized by being soldered.

作用 上記の手段によれば、予備半田を、赤外線ビームを照射
しスキャンさせ゛て溶融させたとき、端部及び/又は外
部リードの相手方と対向しない部分に余剰の半田が濡れ
て、従来のように隣接する端子及び/又は外部リードと
の間に食み出さないので、隣接する端子−外部リード間
の半田とブリ・フジしてショートを起こすことがない。
Effect: According to the above means, when the preliminary solder is irradiated with an infrared beam and scanned to melt it, the excess solder gets wet on the ends and/or the parts of the external leads that do not face the other party, and it is not possible to solve the problem as in the conventional method. Since the solder does not protrude between adjacent terminals and/or external leads, there is no chance of short circuits due to solder between adjacent terminals and external leads.

しかも、半田を厚くできるので、端子と外部リードとを
確実に半田付けできる。
Moreover, since the solder can be thickened, the terminals and external leads can be reliably soldered.

実施例 以下、この発明を薄膜KLパネルの端子とフレキシブル
リードの外部リードとの半田付けに実施する場合につい
て、図面を参照して説明する。
EXAMPLE Hereinafter, a case in which the present invention is applied to soldering between a terminal of a thin film KL panel and an external lead of a flexible lead will be described with reference to the drawings.

第1図ないし第3図は、第1の実施例の各段階の要部拡
大断面図を示し、第1図は半田付は前の分解断面図、第
2図は半田付は時の断面図、第3図は半田付は後の断面
図である。
Figures 1 to 3 show enlarged cross-sectional views of essential parts at each stage of the first embodiment. Figure 1 is an exploded cross-sectional view before soldering, and Figure 2 is a cross-sectional view after soldering. , FIG. 3 is a sectional view after soldering.

まず、台16上に、所定の幅の端子10を形成したガラ
ス基板lをatし、このガラス基&1の上に、前記端子
10と同一幅の外部リード14に予備半田15を形成し
たフレキシブルリード4を、その外部リード14が前記
端子10に対して所定寸法tだけずれるように位置決め
して重ね合わせ、フレキシブルリード4の上に石英板1
7を載置して加圧する。そして、石英板17の上から赤
外線ビーム18を照射しスキャンさせて、予備半田15
を溶融させる(第1図及び第2図)。すると、端子10
と外部リード14とが半田15を介して接続される。こ
のとき、余剰の半田15は、端子10と外部リード14
の互いに相手方と対向していない部分に濡れて、表面張
力で保持されて、隣接する端子io、io間に食み出す
ことがなく、ショートは生じない(第3図)。
First, a glass substrate l on which terminals 10 of a predetermined width are formed is placed on a stand 16, and on this glass substrate &1, flexible leads are formed on external leads 14 having the same width as the terminals 10 with preliminary solder 15 formed thereon. 4 are positioned so that their external leads 14 are shifted from the terminals 10 by a predetermined dimension t, and the quartz plates 1 are placed on top of the flexible leads 4.
7 is placed and pressurized. Then, the infrared beam 18 is irradiated and scanned from above the quartz plate 17, and the preliminary solder 15 is
(Figures 1 and 2). Then, terminal 10
and external leads 14 are connected via solder 15. At this time, the excess solder 15 is removed from the terminal 10 and the external lead 14.
The parts of the terminals that do not face each other get wet and are held by surface tension, so that they do not protrude between the adjacent terminals io and io, and no short circuit occurs (FIG. 3).

より具体的に説明すると、例えば端子10及び外部リー
ド140幅を0.4 rm、それぞれのピー’Iチを0
.8 tm、外部リード14に形成した予備半田15の
厚さを20〜40μ、端子10及び外部リード14のず
れ寸法tを0.1〜0.15箇に設定した場合、端子1
0及び外部リード14の本数160本中シ町−ト不良は
0ケ所であり、半田付は不良によるオープン不良もO木
であった。
To explain more specifically, for example, the width of the terminal 10 and the external lead 140 is 0.4 rm, and the pitch of each is 0.
.. 8 tm, the thickness of the preliminary solder 15 formed on the external lead 14 is set to 20 to 40 μm, and the deviation dimension t between the terminal 10 and the external lead 14 is set to 0.1 to 0.15 points, the terminal 1
Out of 160 leads and external leads 14, there were no defects at any point, and there were also no open defects due to soldering defects.

これに対して、端子10及び外部リード14のずれ寸法
tを0にした他は上記と同一条件にした場合、5〜10
ケ所のシシート不良が生じた。
On the other hand, when the same conditions as above are used except that the deviation dimension t of the terminal 10 and external lead 14 is set to 0, 5 to 10
Seat defects occurred in several places.

第4図は第2実施例の要部拡大平面図を示し、第5図は
第4図のB−B線に対応する断面図を示す。この実施例
は、端子10の幅よりも外部り−ド14の幅を小さくし
て、端子10の両側に外部°リード14と対向しない部
分を設けたものである。
FIG. 4 shows an enlarged plan view of the main part of the second embodiment, and FIG. 5 shows a sectional view corresponding to the line B--B in FIG. 4. In this embodiment, the width of the outer lead 14 is made smaller than the width of the terminal 10, and portions not facing the outer lead 14 are provided on both sides of the terminal 10.

又、この変形例として、端子lO及び外部リード14の
一端を揃えて、端子10の片側のみに外部リード14と
対向しない部分を設けてもよい。
Further, as a modification of this example, the terminal 10 and one end of the external lead 14 may be aligned, and a portion not facing the external lead 14 may be provided only on one side of the terminal 10.

r’jl、 6図は第3実施例の要部拡大平面図を示し
、第7図は第6図のC−C線に対応する断面図を示す。
r'jl, FIG. 6 shows an enlarged plan view of the main part of the third embodiment, and FIG. 7 shows a sectional view corresponding to the line CC in FIG. 6.

この実施例は、外部リード14を端子lOと同一幅で、
かつ端子lOに対して所定角度だけ傾斜するように形成
して、端子10及び外部リード140両方に、相手方と
対向しない部分を、各2箇所ずつ設けたものである。
In this embodiment, the external lead 14 has the same width as the terminal lO,
The terminal 10 and the external lead 140 are both formed to be inclined at a predetermined angle with respect to the terminal 10, and have two portions each that do not face the other party.

発明の効果 本発明によれば、端子と外部リードとを、一部に対向し
ない部分を設けて重ね合わせて、半田付けするようにし
たから、予備半田を厚くしても、余剰の半田が端子及び
/又は外部リードの相手方と対向しない部分に濡れて保
持され、端子間に食み出さないので、端子と外部リード
とを確実に半田付けでき、しかも隣接する端子間でシ言
−トが発生しない、信頼性の高い半田付けができる。
Effects of the Invention According to the present invention, since the terminal and the external lead are overlapped and soldered with some portions not facing each other, even if the preliminary solder is thick, the excess solder will not be absorbed by the terminal. And/or it is wetted and held in the part of the external lead that does not face the other party, and does not protrude between the terminals, so the terminal and external lead can be reliably soldered, and furthermore, a sheet occurs between adjacent terminals. Highly reliable soldering is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図はこの発明を薄膜ELパネルの端子
とフレキンプルリードの外部リードとの半田付けに実施
する場合の、第1実施例の各段階の要部拡大断面図で、
第1図は半田付は前の分解断面図、第2図は半田付は時
の断面図、第3図は半田付は後の断面図である。 第4図はこの発明の第2実施例について説明するための
要部拡大平面図で、第5図は第4図のB−B線に対応す
る断面図である。 第6図はこの発明の第8実施例について説明するための
要部拡大平面図で、第7図は第6図のC−C線に対応す
る断面図である。 第8図は端子にフレキシブルリードを接続した薄膜KL
パネルの断面図で、左半分はX方向の断面を示し、右半
分はX方向に直交するY方向の断面を示し、第9図は第
8図のA−A線に沿う要部拡大断面図である。 第1O図は従来方法による半田付は前の要部拡大分解断
面図で、第11図は半田付は時の要部拡大断面図である
。 1・・・・・・・・・・・・・・・絶縁基板(ガラス基
板)、4・・・・・・・・・・・・・・・フレキンプル
リード、5・・・・・・・・・・・・・・・透明電極、
9・・・・・・・・・・・・・・・背面電極、10・・
・・・・・・・・・・端子、 14・・・・・・・・・外部リード、 15・・・・・・・・・(予備)半田、16・・・・・
・・・・台、 17・・・・・・・・・石英板、 18・・・・・・・・・赤外線ビーム。 半田付(1←電卸≠スそ過9鋤I![lG第1図 第2図 )←− c!14−I
1 to 3 are enlarged sectional views of essential parts at each stage of the first embodiment when the present invention is applied to soldering between the terminal of a thin film EL panel and the external lead of a flexible lead.
FIG. 1 is an exploded sectional view before soldering, FIG. 2 is a sectional view before soldering, and FIG. 3 is a sectional view after soldering. FIG. 4 is an enlarged plan view of essential parts for explaining a second embodiment of the present invention, and FIG. 5 is a sectional view taken along line B--B in FIG. 4. FIG. 6 is an enlarged plan view of essential parts for explaining an eighth embodiment of the present invention, and FIG. 7 is a sectional view taken along line CC in FIG. 6. Figure 8 shows a thin film KL with flexible leads connected to the terminals.
In the cross-sectional view of the panel, the left half shows a cross-section in the X direction, the right half shows a cross-section in the Y direction orthogonal to the X direction, and FIG. 9 is an enlarged cross-sectional view of the main part along line A-A in FIG. 8. It is. FIG. 1O is an enlarged exploded sectional view of the main part before soldering by the conventional method, and FIG. 11 is an enlarged sectional view of the main part after soldering. 1...Insulating substrate (glass substrate), 4...Flexible pull lead, 5...・・・・・・・・・Transparent electrode,
9...... Back electrode, 10...
・・・・・・・・・Terminal, 14・・・・・・External lead, 15・・・・・・(Spare) solder, 16・・・・・・
...stand, 17...quartz plate, 18...infrared beam. Soldering (1←Electronic Wholesale≠Short 9 Plow I! [IG Figure 1 Figure 2) ←- c! 14-I

Claims (1)

【特許請求の範囲】  絶縁基板上の周辺部に沿って形成された多数の端子と
、絶縁性フィルムの周辺部に沿って上記端子と同一ピッ
チで多数の外部リードを形成したフレキシブルリードの
前記外部リードとを予備半田を介し重ね合わせて外部よ
りの赤外線加熱にて半田付けするものにおいて、 前記端子と外部リードとを一部に対向しない部分を設け
て重ね合わせて、半田付けするようにしたことを特徴と
する多端子リードの接続方法。
[Claims] The external part of the flexible lead includes a large number of terminals formed along the periphery of an insulating substrate and a large number of external leads formed at the same pitch as the terminals along the periphery of the insulating film. In a device in which the terminal and the external lead are overlapped via preliminary solder and soldered using external infrared heating, the terminal and the external lead are overlapped with a part that does not face each other and soldered. A method for connecting multi-terminal leads featuring:
JP1907285A 1985-02-01 1985-02-01 Connection for multiterminal lead Pending JPS61177795A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1907285A JPS61177795A (en) 1985-02-01 1985-02-01 Connection for multiterminal lead

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1907285A JPS61177795A (en) 1985-02-01 1985-02-01 Connection for multiterminal lead

Publications (1)

Publication Number Publication Date
JPS61177795A true JPS61177795A (en) 1986-08-09

Family

ID=11989226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1907285A Pending JPS61177795A (en) 1985-02-01 1985-02-01 Connection for multiterminal lead

Country Status (1)

Country Link
JP (1) JPS61177795A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823147A (en) * 1994-07-07 1996-01-23 Nippondenso Co Ltd Connecting structure for circuit board
JP2010103138A (en) * 2008-10-21 2010-05-06 Panasonic Corp Connection structure and connection method for electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823147A (en) * 1994-07-07 1996-01-23 Nippondenso Co Ltd Connecting structure for circuit board
JP2010103138A (en) * 2008-10-21 2010-05-06 Panasonic Corp Connection structure and connection method for electronic component

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