JPH0228546Y2 - - Google Patents
Info
- Publication number
- JPH0228546Y2 JPH0228546Y2 JP1984099324U JP9932484U JPH0228546Y2 JP H0228546 Y2 JPH0228546 Y2 JP H0228546Y2 JP 1984099324 U JP1984099324 U JP 1984099324U JP 9932484 U JP9932484 U JP 9932484U JP H0228546 Y2 JPH0228546 Y2 JP H0228546Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- substrate
- terminal
- electrode layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 13
- 229910000679 solder Inorganic materials 0.000 description 15
- 238000005476 soldering Methods 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 239000006059 cover glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229920002545 silicone oil Polymers 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Description
【考案の詳細な説明】
産業上の利用分野
本考案は薄膜ELパネルに関し、詳しくはマト
リクス状に配置された電極層を有し、平面薄型デ
イスプレイ・デバイスとして使用される薄膜EL
パネルの電極端子部の構造に関するものである。[Detailed description of the invention] Industrial application field The present invention relates to a thin film EL panel, and more specifically, a thin film EL panel that has electrode layers arranged in a matrix and is used as a flat thin display device.
This relates to the structure of the electrode terminal portion of the panel.
従来の技術
この薄膜ELパネルの具体例を第５図から説明
すると、同図に示すようにガラス板等の透光性の
基板１上に、In、Sn等の酸化物等からなる透明
電極、すなわち第１の電極層２、Y2O3等からな
る第１の誘電体層３、Mn等をドープしたZnS等
よりなる発光層４、前記第１の誘電体層３と同様
の材質よりなる第２の誘電体層５、Al等からな
る背面電極、すなわち第２の電極層６を順次積層
し、薄膜EL素子７を形成する。更にこの薄膜EL
素子７を覆うように凹板状のカバーガラス８を、
光硬化性樹脂材等の接着剤９を介して基板１上に
固着させることにより基板１及びカバーガラス８
からなる外囲器１０を形成し、薄膜ELパネル素
子７の耐湿性を向上させるため上記外囲器１０内
にシリコンオイル等の絶縁性保護流体１１を封入
する（特公昭57−47559号公報）。ここで上記第１
及び第２の電極層２，６…は、第６図に示すよう
に発光層４を第１及び第２の誘電体層（図示せ
ず）を介して挾み込むことにより相互に直交する
ように夫々複数本平行配置されてマトリクス状に
形成される。各第１及び第２の電極層２，６…の
一端は基板１の周辺部に延設され、各辺部にて第
１及び第２の電極層２，６…の端子部２′，６′…
を形成する。この端子部２′，６′…を介して上記
第１及び第２の電極層２，６…とフレキシブルリ
ード１２，１２…とを電気的に接続する。第１及
び第２の電極層２，６…の交差点に挾まれた発光
層４の各部分はELセルを形成し、薄膜EL素子駆
動用の交流電源（図示せず）からフレキシブルリ
ード１２，１２…を介して第１及び第２の電極層
２，６…に選択的に電圧を印加することにより、
各ELセルを発光させて文字や図形等の所望の画
像を表示させている。Prior Art A specific example of this thin film EL panel will be explained from FIG. 5. As shown in the figure, a transparent electrode made of an oxide such as In or Sn is placed on a transparent substrate 1 such as a glass plate. That is, a first electrode layer 2, a first dielectric layer 3 made of Y 2 O 3 etc., a light emitting layer 4 made of ZnS doped with Mn etc., and made of the same material as the first dielectric layer 3. A second dielectric layer 5 and a back electrode made of Al or the like, that is, a second electrode layer 6 are sequentially laminated to form a thin film EL element 7. Furthermore, this thin film EL
A concave plate-shaped cover glass 8 is placed so as to cover the element 7.
The substrate 1 and the cover glass 8 are fixed on the substrate 1 via an adhesive 9 such as a photocurable resin material.
In order to improve the moisture resistance of the thin film EL panel element 7, an insulating protective fluid 11 such as silicone oil is sealed in the envelope 10 (Japanese Patent Publication No. 57-47559). . Here, the first
and the second electrode layers 2, 6... are arranged so that they are orthogonal to each other by sandwiching the light emitting layer 4 through the first and second dielectric layers (not shown), as shown in FIG. A plurality of these are arranged in parallel to form a matrix. One end of each of the first and second electrode layers 2, 6... extends to the periphery of the substrate 1, and terminal portions 2', 6 of the first and second electrode layers 2, 6... '...
form. The first and second electrode layers 2, 6, . . . and the flexible leads 12, 12, . . . are electrically connected through the terminal portions 2', 6', . Each part of the light emitting layer 4 sandwiched at the intersection of the first and second electrode layers 2, 6... forms an EL cell, and flexible leads 12, 12 are connected to an AC power source (not shown) for driving the thin film EL element. By selectively applying voltage to the first and second electrode layers 2, 6... via...
Each EL cell is made to emit light to display desired images such as characters and figures.
上記第１及び第２の電極層２，６…の端子部
２′，６′…は、第７図Ａ，Ｂ及び第８図に示すよ
うに基板１の周辺部に沿つて第１及び第２の電極
層２，６…と同一ピツチ間隔で電極パツド１３，
１３…を電子ビーム蒸着等により形成する。即
ち、上記第１の電極層２の一部に重畳して電極パ
ツド１３…を形成し、第２の電極層２，６…は、
電極パツド１３，１３…の一部に重畳して形成す
る。上記電極パツド１３，１３…は、例えばTi
等の基板１となじみのよい金属からなる最下層１
３ａと、Al等よりなる中間層１３ｂと、Ni等の
半田となじみのよい金属からなる最上層１３ｃと
を順次積層してなる３層構造のものである。また
一方、前記フレキシブルリード１２は絶縁性のプ
ラスチツクフイルム１２ａに、第１及び第２の電
極層２，６…の端子部２′，６′…と同一ピツチ間
隔で、胴等よりなる複数本のリードパターン１２
ｂ，１２ｂ…を平行に被着形成したもので、第１
及び第２の電極層２，６…の端子部２′，６′とフ
レキシブルリード１２，１２…との接続は、電極
パツド１３，１３…とリードパターン１２ｂ，１
２ｂ…の端部とを位置合わせし、電極パツド１
３，１３…の最上層１３ｃ，１３ｃ…にリードパ
ターン１２ｂ，１２ｂ…を半田付けしている。
尚、第１及び第２の電極層２，６…の端子部２′，
６′…は、上記電極パツド１３，１３…とリード
パターン１２ｂ，１２ｂ…との半田付けを容易且
つ確実にするため幅広に設定されている。 The terminal portions 2', 6'... of the first and second electrode layers 2, 6... are arranged along the periphery of the substrate 1 as shown in FIGS. Electrode pads 13, at the same pitch spacing as the electrode layers 2, 6...
13... are formed by electron beam evaporation or the like. That is, the electrode pads 13 are formed by partially overlapping the first electrode layer 2, and the second electrode layers 2, 6...
The electrode pads 13, 13, . . . are formed so as to partially overlap with each other. The electrode pads 13, 13... are made of Ti, for example.
The bottom layer 1 is made of a metal that is compatible with the substrate 1 such as
3a, an intermediate layer 13b made of Al or the like, and an uppermost layer 13c made of a metal compatible with solder such as Ni, which are successively laminated to have a three-layer structure. On the other hand, the flexible lead 12 has a plurality of wires made of a body etc. attached to the insulating plastic film 12a at the same pitch spacing as the terminal portions 2', 6'... of the first and second electrode layers 2, 6... Lead pattern 12
b, 12b... are formed in parallel, and the first
The terminal portions 2', 6' of the second electrode layers 2, 6... and the flexible leads 12, 12... are connected to the electrode pads 13, 13... and the lead patterns 12b, 1.
Align the ends of electrode pads 1 and 2b...
Lead patterns 12b, 12b, . . . are soldered to the top layers 13c, 13c, .
Note that the terminal portions 2' of the first and second electrode layers 2, 6...
6'... are set wide in order to facilitate and ensure soldering between the electrode pads 13, 13... and the lead patterns 12b, 12b....
考案が解決しようとする問題点
ところで上述したように第１及び第２の電極層
２，６…の端子部２′，６′…にフレキシブルリー
ド１２，１２…を接続するに際しては、通常フレ
キシブルリード１２，１２…に半田膜を形成した
状態で該フレキシブルリード１２，１２…を電極
パツド１３，１３…に圧着させて赤外線ビームを
スキヤンさせること等により半田付けしている
が、フレキシブルリード１２，１２…に形成され
た半田膜の膜厚にバラツキが存在すると共に、接
続時での加熱及び加圧を均一に保持することに困
難性を伴う。その結果、フレキシブルリード１
２，１２…の接続強度が不足したり、延いては接
触不良が生じたりする場合があつた。また近年、
薄膜ELパネルにおける画像表示に高解像度が要
求されており、この場合第１及び第２の電極層
２，６…のピツチ間隔が小さくなるため端子部
２′，６′…が非常に近接し、半田付けの信頼性を
向上するために多目の半田を用いた場合、接続時
に余分な半田の流れ出しによつて隣接する端子部
２′，６′…間の短絡が発生する場合もあり、信頼
性が大幅に低下するという問題点があつた。Problems to be solved by the invention By the way, as mentioned above, when connecting the flexible leads 12, 12... to the terminal parts 2', 6'... of the first and second electrode layers 2, 6..., the flexible leads are usually used. The flexible leads 12, 12... are soldered by pressing the electrode pads 13, 13... with a solder film formed on them and scanning the infrared beam, but the flexible leads 12, 12... There are variations in the thickness of the solder film formed on... and it is difficult to maintain uniform heating and pressure during connection. As a result, flexible lead 1
There have been cases where the connection strength of 2, 12, etc. is insufficient, and even poor contact occurs. Also, in recent years,
High resolution is required for image display on thin-film EL panels, and in this case, the pitch distance between the first and second electrode layers 2, 6... becomes small, so the terminal portions 2', 6'... are very close together. If a large amount of solder is used to improve the reliability of soldering, the excess solder may flow out during connection, causing a short circuit between adjacent terminals 2', 6', etc. There was a problem in that the performance was significantly reduced.
問題を解決するための手段
本考案は上記問題点に鑑み提案されたもので、
第１及び第２の電極層の端子部とフレキシブルリ
ードとの接続を信頼性の高いものにするものであ
り、その技術的手段は基板上に第１の電極層、第
１の誘電体層、発光層、第２の誘電体層、第２の
電極層を順次積層し、第１及び第２の電極層を基
板の周辺部に沿つて配設された電極パツドに接続
して端子部を形成したものに於いて、上記端子部
間の基板上に絶縁層を形成すると共に該絶縁層と
端子部との間に隙間を設けかつ端子部に少なくと
も絶縁層側に開口する溝部を設けたことを特徴と
する。Means for solving the problem This invention was proposed in view of the above problems.
The purpose is to make the connection between the terminal parts of the first and second electrode layers and the flexible leads highly reliable, and the technical means thereof is to provide a first electrode layer, a first dielectric layer, a first dielectric layer, A terminal portion is formed by sequentially laminating a light emitting layer, a second dielectric layer, and a second electrode layer, and connecting the first and second electrode layers to electrode pads disposed along the periphery of the substrate. In this, an insulating layer is formed on the substrate between the terminal parts, a gap is provided between the insulating layer and the terminal part, and a groove part opening at least toward the insulating layer side is provided in the terminal part. Features.
実施例
以下に本考案に係る薄膜ELパネルの一実施例
を第１図乃至第４図から説明する。図において、
第５図乃至第８図と同一符号は同一物を示しその
説明は省略する。本考案の特徴は第１及び第２の
電極層２，６…の端子部２″，６″…にある。第１
図は第１及び第２の電極層２，６…の端子部２″，
６″…とフレキシブルリード１２，１２…との接
続状態を示し、第２図は上記第１及び第２の電極
層２，６…の端子部２″，６″…、即ち電極パツド
１３′，１３′…を示す。この電極パツド１３′，
１３′…は、第３図に示すようにメタルマスクを
利用した真空蒸着法等により基板１の周辺部に沿
つて第１及び第２の電極層２，６…と同一ピツチ
間隔で形成され、従来と同様にTi等からなる最
下層１３a′、Al等からなる中間層１３b′、Ni等
からなる最上層１３c′を順次積層してなる３層構
造を有する。また第２図にも示すように上記電極
パツド１３′，１３′…の最上層１３c′，１３c′…
の上面には、半田との接着強度を大きくするた
め、四方に開口する溝部１４，１４…が予め形成
される。更に第４図に示すように真空蒸着法等に
より電極パツド１３′，１３′…間の基板１上に絶
縁層１５，１５…を被着形成する。この絶縁層１
５，１５…の厚みは電極パツド１３′，１３′…の
厚みよりも若干厚肉に設定され、且つ絶縁層１
５，１５…の幅は電極パツド１３′，１３′…間の
間隔よりも狭く設定されて絶縁層１５，１５…と
電極パツド１３′，１３′…との間に例えば数百μ
ｍ程度の隙間１６，１６が設けられている。Embodiment An embodiment of the thin film EL panel according to the present invention will be described below with reference to FIGS. 1 to 4. In the figure,
The same reference numerals as in FIGS. 5 to 8 indicate the same components, and the explanation thereof will be omitted. The feature of the present invention lies in the terminal portions 2'', 6''... of the first and second electrode layers 2, 6.... 1st
The figure shows terminal portions 2'' of the first and second electrode layers 2, 6...
6''... and the flexible leads 12, 12..., and FIG. 13'... is shown.These electrode pads 13',
13' are formed along the periphery of the substrate 1 at the same pitch interval as the first and second electrode layers 2, 6, etc. by a vacuum evaporation method using a metal mask, as shown in FIG. As in the conventional case, it has a three-layer structure in which a bottom layer 13a' made of Ti or the like, an intermediate layer 13b' made of Al or the like, and an uppermost layer 13c' made of Ni or the like are laminated in this order. Further, as shown in FIG. 2, the uppermost layers 13c', 13c'... of the electrode pads 13', 13'...
In order to increase the adhesive strength with solder, grooves 14, 14, . Furthermore, as shown in FIG. 4, insulating layers 15, 15, . . . are deposited on the substrate 1 between the electrode pads 13', 13', . . . by vacuum evaporation or the like. This insulating layer 1
The thickness of the electrode pads 13', 13'... is set to be slightly thicker than that of the insulating layer 1.
The widths of the electrode pads 13', 13'... are set narrower than the spacing between the electrode pads 13', 13'..., so that there is, for example, several hundred microns between the insulating layers 15, 15... and the electrode pads 13', 13'...
A gap 16, 16 of about m is provided.
上記第１及び第２の電極層２，６…の端子部
２″，６″…とフレキシブルリード１２，１２…と
を接続するに際しては、従来と同様の要領にてフ
レキシブルリード１２，１２…に半田膜を形成し
た状態で、電極パツド１３′，１３′…とリードパ
ターン１２ｂ，１２ｂ…の端部とを位置合わせ
し、フレキシブルリード１２，１２…を第１及び
第２の電極層２，６…の電極パツド１３′，１
３′…に赤外線ビームをスキヤンすること等によ
り半田付けする。この時、上記電極パツド１３′，
１３′…上に溝部１４，１４…を設けているため、
接着表面積が大きく、且つ、複雑になることで、
フレキシブルリード１２，１２…の接着強度が大
きくなる。又、余分な半田は電極パツド１３′，
１３′…と絶縁層１５，１５…との隙間１６，１
６…に容易に流れ出ると共に、絶縁層１５，１５
…に阻止されて、隣接する電極パツド１３，１３
同士が半田により短絡することがない。 When connecting the terminal portions 2'', 6''... of the first and second electrode layers 2, 6... and the flexible leads 12, 12..., the flexible leads 12, 12... are connected in the same manner as in the conventional method. With the solder film formed, the electrode pads 13', 13'... and the ends of the lead patterns 12b, 12b... are aligned, and the flexible leads 12, 12... are connected to the first and second electrode layers 2, 6. ...electrode pads 13', 1
Soldering is carried out by scanning an infrared beam on 3'.... At this time, the electrode pads 13',
Since grooves 14, 14... are provided on 13',
Due to the large and complex adhesive surface area,
The adhesive strength of the flexible leads 12, 12... increases. Also, excess solder is removed from the electrode pads 13',
13'... and the gaps 16, 1 between the insulating layers 15, 15...
6... and the insulating layers 15, 15.
..., the adjacent electrode pads 13, 13
There will be no short circuit between them due to soldering.
考案の効果
本考案によれば、第１及び第２の電極層の端子
部間の基板上に絶縁層を形成すると共に該絶縁層
と端子部との間に隙間を設けたことにより、上記
第１及び第２の電極層の端子部にフレキシブルリ
ードを半田付け接続するに際して、フレキシブル
リードの半田膜の膜厚及び、加圧条件が不均一で
あること等から溶融した余分な半田が流れ出して
も、端子部と絶縁層との間の隙間に貯められ、ま
た薄膜ELパネルの高解像度化に伴い、隣接する
端子部が近接する場合でも絶縁層が隔壁となつて
余分な半田の流れ出しによる隣接する端子部間の
短絡を未然に防止することが可能となる。更に上
述したように余分な半田を端子部と絶縁層との間
に隙間に貯めることができるので、従来よりも半
田量を多くしても問題はなく、多量の半田を使用
することができることによつて半田付け不良が発
生することもなく、信頼性も大幅に向上する。Effects of the invention According to the invention, an insulating layer is formed on the substrate between the terminal parts of the first and second electrode layers, and a gap is provided between the insulating layer and the terminal part. When connecting the flexible leads to the terminals of the first and second electrode layers by soldering, excess melted solder may flow out due to uneven thickness of the solder film of the flexible leads and uneven pressure conditions. , is accumulated in the gap between the terminal part and the insulating layer, and as the resolution of thin-film EL panels increases, even when adjacent terminal parts are close to each other, the insulating layer acts as a partition wall and excess solder flows out. It becomes possible to prevent short circuits between terminal parts. Furthermore, as mentioned above, excess solder can be stored in the gap between the terminal part and the insulating layer, so there is no problem even if the amount of solder is increased compared to conventional methods, and a large amount of solder can be used. Therefore, soldering defects do not occur, and reliability is greatly improved.
さらに端子部に溝部を形成したので半田付の強
度が増し、余分な半田は絶縁層と端子部との間の
隙間に流れ出て、半田付けの信頼性が向上する。 Furthermore, since the groove portion is formed in the terminal portion, the strength of soldering is increased, and excess solder flows out into the gap between the insulating layer and the terminal portion, improving the reliability of soldering.
第１図乃至第４図は本考案に係る薄膜ELパネ
ルの一実施例を説明するためのもので、第１図は
第１及び第２の電極層の端子部とフレキシブルリ
ードとの接続状態を示す部分平面図、第２図は第
１及び第２の電極層の端子部並びに絶縁層を示す
要部拡大斜視図、第３図及び第４図は端子部及び
絶縁層の形成を説明するための要部拡大断面図で
ある。第５図は薄膜ELパネルの具体例を示す断
面図、第６図は従来における第１及び第２の電極
層とフレキシブルリードとの接続状態を示す要部
平面図、第７図Ａ，Ｂは第５図の要部拡大断面
図、第８図は第１及び第２の電極層の端子部を示
す部分斜視図である。
１……基板、２……第１の電極層、２′，２″…
…第１の電極層の端子部、３……第１の誘電体
層、４……発光層、５……第２の誘電体層、６…
…第２の電極層、６′，６″……第２の電極層の端
子部、１２……フレキシブルリード、１３，１
３′……電極パツド、１４……溝部、１５……絶
縁層、１６……隙間。
Figures 1 to 4 are for explaining one embodiment of the thin film EL panel according to the present invention, and Figure 1 shows the connection state between the terminal portions of the first and second electrode layers and the flexible leads. FIG. 2 is an enlarged perspective view of main parts showing the terminal portions and insulating layers of the first and second electrode layers, and FIGS. 3 and 4 are for explaining the formation of the terminal portions and the insulating layers. FIG. Fig. 5 is a cross-sectional view showing a specific example of a thin film EL panel, Fig. 6 is a plan view of main parts showing the connection state between the first and second electrode layers and flexible leads in the conventional art, and Fig. 7 A and B are FIG. 5 is an enlarged sectional view of the main part, and FIG. 8 is a partial perspective view showing the terminal portions of the first and second electrode layers. 1... Substrate, 2... First electrode layer, 2', 2''...
...Terminal portion of first electrode layer, 3...First dielectric layer, 4...Light emitting layer, 5...Second dielectric layer, 6...
...Second electrode layer, 6', 6''...Terminal part of second electrode layer, 12...Flexible lead, 13,1
3'... Electrode pad, 14... Groove, 15... Insulating layer, 16... Gap.
Claims (1)
層、第２の誘電体層、第２の電極層を順次積層
し、第１及び第２の電極層を基板の周辺部に沿つ
て配設された電極パツドに接続して端子部を形成
し、端子部にフレキシブルリードを半田付けした
ものに於て、上記端子部間の基板上に絶縁層を形
成すると共に該絶縁層と端子部との間に隙間を設
けかつ端子部に少なくとも絶縁層側に開口する溝
部を設けたことを特徴とする薄膜ELパネル。 A first electrode layer, a first dielectric layer, a light emitting layer, a second dielectric layer, and a second electrode layer are sequentially laminated on the substrate, and the first and second electrode layers are placed on the periphery of the substrate. In the case where a terminal part is formed by connecting to the electrode pads arranged along the line, and a flexible lead is soldered to the terminal part, an insulating layer is formed on the substrate between the terminal parts, and the insulating layer and the flexible lead are soldered to the terminal part. A thin film EL panel characterized in that a gap is provided between the terminal part and a groove part that opens at least toward an insulating layer side in the terminal part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984099324U JPS6113891U (en) | 1984-06-29 | 1984-06-29 | Thin film EL panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984099324U JPS6113891U (en) | 1984-06-29 | 1984-06-29 | Thin film EL panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6113891U JPS6113891U (en) | 1986-01-27 |
| JPH0228546Y2 true JPH0228546Y2 (en) | 1990-07-31 |
Family
ID=30658831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984099324U Granted JPS6113891U (en) | 1984-06-29 | 1984-06-29 | Thin film EL panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6113891U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001222021A (en) * | 2000-02-09 | 2001-08-17 | Seiko Epson Corp | Liquid crystal device and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559491A (en) * | 1978-10-27 | 1980-05-02 | Citizen Watch Co Ltd | Liquid crystal display cell |
| JPS5593294A (en) * | 1979-01-05 | 1980-07-15 | Matsushita Electric Ind Co Ltd | Reflow soldering method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035981Y2 (en) * | 1980-03-31 | 1985-10-25 | シャープ株式会社 | connector |
| JPS57191070U (en) * | 1981-05-29 | 1982-12-03 |
-
1984
- 1984-06-29 JP JP1984099324U patent/JPS6113891U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559491A (en) * | 1978-10-27 | 1980-05-02 | Citizen Watch Co Ltd | Liquid crystal display cell |
| JPS5593294A (en) * | 1979-01-05 | 1980-07-15 | Matsushita Electric Ind Co Ltd | Reflow soldering method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6113891U (en) | 1986-01-27 |
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