JPS61176155A - Manufacture of active matrix substrate - Google Patents
Manufacture of active matrix substrateInfo
- Publication number
- JPS61176155A JPS61176155A JP60016745A JP1674585A JPS61176155A JP S61176155 A JPS61176155 A JP S61176155A JP 60016745 A JP60016745 A JP 60016745A JP 1674585 A JP1674585 A JP 1674585A JP S61176155 A JPS61176155 A JP S61176155A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- silicon thin
- active matrix
- film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 36
- 239000011159 matrix material Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010409 thin film Substances 0.000 claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 239000012535 impurity Substances 0.000 abstract description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 18
- 239000010703 silicon Substances 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 12
- 150000002500 ions Chemical class 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
- 238000002513 implantation Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁基板上に形成された薄膜トランジスタ（以
後ＴＦτと略す）の製造方法忙関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a thin film transistor (hereinafter abbreviated as TFτ) formed on an insulating substrate.
善に液晶表示装置等忙用いられる絶縁基板上ＫＴＦＴア
レイを形成したアクティブマトリクス基板の製造方法忙
関する。The present invention relates to a method of manufacturing an active matrix substrate on which a KTFT array is formed on an insulating substrate, which is often used in liquid crystal display devices and the like.
従来のアクティブマトリクス基板の製造方法について、
ポリシリコンＴＰＴを使って説明する。Regarding the conventional method of manufacturing active matrix substrates,
This will be explained using polysilicon TPT.
ポリシリコン７１ＦＴは、第２図忙示すように絶縁基板
１１上にポリシリコン薄膜１２を５００Ａ〜５０００Ａ
の膜厚でＣＶＤ法（気相成長法）吟忙より形成し、所定
の形状に選択的虻エツチングする。As shown in FIG.
The film is formed using the CVD method (vapor phase growth method) to a film thickness of 100 mL, and selectively etched into a predetermined shape.
このポリシリコン薄１１２を熱酸化して、ゲート酸化＃
１３を形成し、さらにゲート電極１４を形成する几め忙
高融点金属薄膜やポリシリコン薄膜を２０００ Ａ〜１
００ＧＯＡの膜厚で形成し熱拡散忙よる不純物拡散後、
所定の形状となす。ゲート電極１４をマスクとしてイオ
ン注入により不純物をポリシリコン１２中に注入してソ
ース１５及びドレイン１６を形成する。モノチャネルＴ
ＰＴ基板の場合。This polysilicon thin film 112 is thermally oxidized to form a gate oxide #
13, and a high melting point metal thin film or polysilicon thin film to form the gate electrode 14 at 2000 A~1.
After forming a film with a thickness of 00 GOA and diffusing impurities by thermal diffusion,
Make it into a predetermined shape. A source 15 and a drain 16 are formed by implanting impurities into the polysilicon 12 by ion implantation using the gate electrode 14 as a mask. Mono channel T
In case of PT board.
け、Ｎ形あるーはＰ形のどちらか一方の不純物を注入す
ればよ−が、０ＭＯ８の場合などけ、例えばＰ形の不純
物を全面に注入し友後フォトレジスト等によりヤスクを
形成して選択的ＫＮ形不純物の注入する。Ｎ形、Ｐ形の
不純物注入の順番でもよいし、Ｐ形Ｎ形双方とも選択的
に注入してもよい。Either one of the impurities, N-type or P-type, should be implanted, but in the case of 0MO8, for example, P-type impurities are implanted over the entire surface and a mask is formed using photoresist or the like. Selective KN type impurity implantation. The N-type and P-type impurities may be implanted in this order, or both P and N-type impurities may be implanted selectively.
不純物層を形成し友後、絶縁層を形成して層間絶縁１１
ｉ１１７とし熱処理し几あと、フォトエツチング法によ
りコンタクトホールを開口して後、透明導電膜により配
線１８及び画素駆動電極１９を形成する。以上忙よりア
クティブマトリクス基板が形成される。After forming an impurity layer and forming an insulating layer, interlayer insulation 11
After heat treatment as i117, contact holes are opened by photoetching, and then wiring 18 and pixel drive electrodes 19 are formed using a transparent conductive film. Through the above steps, an active matrix substrate is formed.
しかし、前述の従来技術では、絶縁基板上にイオン注入
を行う食め、絶縁基板上に多量の電荷が蓄積されること
になり、基板内で放電が発生して膜破壊が頻発に発生し
て、アクティブマトリクス基板の製造を困難にするとい
う問題点を有する。However, in the above-mentioned conventional technology, since ions are implanted onto the insulating substrate, a large amount of charge is accumulated on the insulating substrate, and discharge occurs within the substrate, resulting in frequent film breakdown. However, this method has the problem of making it difficult to manufacture an active matrix substrate.
そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、アクティブマトリクス基板の歩
留りを向上し、安定製造を可能にする製造方法を提供す
るところにある。The present invention is intended to solve these problems, and its purpose is to provide a manufacturing method that improves the yield of active matrix substrates and enables stable manufacturing.
本発明のアクティブマトリクス基板の製造方法は、ゲー
ト電極を形成した後、シリコン薄膜を基板全面に形成し
、イオン注入を行つ友のち忙シリコン薄膜を酸化するこ
とを特徴とする。The method for manufacturing an active matrix substrate of the present invention is characterized in that after forming a gate electrode, a silicon thin film is formed on the entire surface of the substrate, and after ion implantation is performed, the silicon thin film is oxidized.
本発明の上記の製造方法によれば、導電性を有するシリ
コン薄膜をイオン注入する基板上に形成してイオン注入
を行なうととにより、基ｆ！！面を一定電位に保つこと
ができ、イオン注入中に発生する放電を防ぐことができ
る。さらに基板上に形成され几シリコン薄膜をイオン注
入後に酸化することにより良質な層間絶縁膜となすこと
がモきる。According to the above-described manufacturing method of the present invention, a conductive silicon thin film is formed on a substrate into which ions are to be implanted, and ions are implanted. ! The surface can be kept at a constant potential, and discharge that occurs during ion implantation can be prevented. Furthermore, by oxidizing the silicon thin film formed on the substrate after ion implantation, it is possible to form a high-quality interlayer insulating film.
第１図及び第３図は１本発明の実施例Ｋかけるアクティ
ブマトリクス基板の製造方法を示す断面図である。1 and 3 are cross-sectional views showing a method of manufacturing an active matrix substrate according to Example K of the present invention.
絶縁基板１上にシリコン薄膜２をａＶＤ（化学気相成長
）法により５００°に〜３０００ Ａの厚さで形成し、
フォトエツチングにより所定の形状にす、る。A silicon thin film 2 is formed on an insulating substrate 1 by aVD (chemical vapor deposition) method at an angle of 500° to a thickness of ~3000 A,
A predetermined shape is formed by photo-etching.
エツチングはＣＦ４あるいはＯＦ、と０．ガスの混合ガ
ス忙よりプラズマエツチングする。Etching is CF4 or OF, and 0. Plasma etching is performed using a mixture of gases.
次に熱酸化により５００Ａ〜２０００ Ａのシリコン酸
化膜を形成しゲート酸化膜３となし、さらにシリコン薄
膜をＯＶＤ法により２０００λ〜１００００裏の膜厚で
形成し熱拡散による不純物拡散しｔあとフォトエツチン
グによりゲート電極５及び配線を形成する。上記薄膜パ
ターン形成した基板上にシリコン薄膜６を１００λ〜１
ｏｏｏＸの厚さでＯＶＤ法（常圧ＯＶＤ法、減圧ＯＶＤ
法、プラズｖＯＶＤ法等）Ｋより形成した後、Ｐ形不純
物としてＩＩＢ＋をビーム電流５００μＡ、注入量ｌＸ
１０”ｃｌＬ４の条件で不純物の注入を行い、さら忙フ
ォトレジストによりイオン注入マスクを形成してＮ形不
純物としてｓＩＮ をビーム電流８００μＡ、注入量
Ｓ Ｘ １０”ニー２の条件で不純物の注入を行なう。Next, a silicon oxide film of 500A to 2000A is formed by thermal oxidation to form the gate oxide film 3, and a silicon thin film is further formed with a thickness of 2000A to 10000A by the OVD method, impurities are diffused by thermal diffusion, and then photoetched. The gate electrode 5 and wiring are formed by the following steps. A silicon thin film 6 with a thickness of 100λ to 1
OVD method (normal pressure OVD method, reduced pressure OVD method) with a thickness of oooX
method, plasma VOVD method, etc.), then IIB+ as a P-type impurity was implanted at a beam current of 500 μA and an implantation amount lX.
Impurity implantation is performed under the conditions of 10"clL4, and an ion implantation mask is formed using a photoresist, and impurity implantation is performed with sIN as an N-type impurity at a beam current of 800 μA and an implantation amount S x 10" knee 2. .
このときのイオンの加速電圧は、各薄膜層の膜厚と不純
物に対するスト９ピングパワーを考慮して決める。イオ
ン注入後、水蒸気雰囲気内で８００℃〜１０００℃の温
度でシリコン薄膜６を熱鹸化して完全にシリコン酸化膜
７にする。さらｋこのシリコン酸化膜７の上ＫＯＶＤ法
によりシリコン酸化膜８を形成しシリコン酸化膜７及び
８０合計の厚さが５０００ Ａ以上になるようｋする。The ion acceleration voltage at this time is determined in consideration of the thickness of each thin film layer and the striking power for impurities. After ion implantation, the silicon thin film 6 is thermally saponified at a temperature of 800° C. to 1000° C. in a steam atmosphere to completely convert it into a silicon oxide film 7. Furthermore, a silicon oxide film 8 is formed on this silicon oxide film 7 by the KOVD method so that the total thickness of the silicon oxide films 7 and 80 becomes 5000 Å or more.
この後は従来と同様にして熱処理して眉間絶縁膜となる
シリコン酸化膜７及び８にコンタクトホールを開口して
透明導電膜による配線９及び画素駆動電極１０を形成し
て、０Ｍ０Ｅ＋ドライバーを内蔵した液晶表示パネル用
の’ｒＦ？アクティブマトリクス基板を形成し斥。After this, contact holes were opened in silicon oxide films 7 and 8, which will become the glabellar insulating film, by heat treatment in the same manner as before, and wiring 9 and pixel drive electrodes 10 made of transparent conductive films were formed, and a 0M0E+ driver was built in. 'rF? for liquid crystal display panels? Form an active matrix substrate.
さらに上記アクティブマトリクス基板上ＫＤＯ力９ト膜
としてシリコン酸化膜をスパッタ蒸着し端子部を金属配
線して、通常行なわれる手順に従りて液晶パネルとした
。Furthermore, a silicon oxide film was sputter-deposited as a KDO film on the active matrix substrate, and the terminal portions were wired with metal, thereby forming a liquid crystal panel according to the usual procedure.
〔実施例２〕
ゲート電極まで実施例１と同様忙して絶縁基板上に薄膜
パターン形成し几のち、リンをドービンで形成した。リ
ンのドーピングけＳｉ薄膜形成後熱拡散でも同じである
。この基篇を実施例１と同様にして不純物のイオン注入
した後、ドライ酸素雰囲気中で１０００℃〜１１５０℃
の温度負性でＳｉ薄膜を熱酸化して、完全にシリコン酸
化膜となす。以下実施例１と同様にしてアクティブマト
リクス基板となし、さら忙液晶表示パネルとなし友。[Example 2] As in Example 1, a thin film pattern was formed on an insulating substrate up to the gate electrode, and then phosphorus was formed using dobin. The same is true for phosphorus doping and thermal diffusion after forming a Si thin film. After implanting impurity ions into this basic structure in the same manner as in Example 1, it was heated to 1000°C to 1150°C in a dry oxygen atmosphere.
The Si thin film is thermally oxidized at a negative temperature of , to completely form a silicon oxide film. Thereafter, an active matrix substrate was fabricated in the same manner as in Example 1, and a liquid crystal display panel was fabricated.
以上述べ几ように本発明によれば、導電性を有するシリ
コン薄膜で基板表面を覆っ几状態でイオン注入ができる
ことから、イオン注入忙よる基板表面内での放電を完全
忙防ぐことができるようになり、しかも放電を完全に防
ぐことができ次ことからビーム電流を大巾に増すことが
できるよう忙なりイオン注入の処理能力ｆ）Ｌ大巾忙（
約１０倍）改善された。さら忙まｔ、基板表面を覆った
シリコン薄膜を熱酸化で絶縁化ができしかも絶縁性の良
好で緻密な膜であることから眉間絶縁膜の噂質がよくな
り、歩留り信頼′性ｂｚ向上する。As described above, according to the present invention, ion implantation can be performed in a stable state by covering the substrate surface with a conductive silicon thin film, making it possible to completely prevent discharge within the substrate surface due to ion implantation. Moreover, discharge can be completely prevented, and the beam current can be greatly increased due to the processing capacity of ion implantation.
(approximately 10 times) improved. In addition, the thin silicon film covering the substrate surface can be insulated by thermal oxidation, and since it is a dense film with good insulating properties, the quality of the glabellar insulating film is improved and the yield reliability is improved. .
第１図は本発明によるアクティブマトリクス基板の製造
方法を示す主ｌ！断面図である。
第２図は従来、のアクティブマトリクス基板の主要断面
図である。
第３図は本発明によるアクティブマトリクス基板の主要
断面図である。
１．１１・・・・・・絶縁基板
２．６．１２ ・・・・・・ポリシリコン薄膜３．１３
・・・・・・ゲート絶縁膜
５．１４・・・・・・ゲート電極
７・・・・・・シリコン酸化膜
１０．１９・・・・・・画素駆動電極
以 上
出麗人 株式会社 諏訪精工會FIG. 1 shows a method for manufacturing an active matrix substrate according to the present invention. FIG. FIG. 2 is a main cross-sectional view of a conventional active matrix substrate. FIG. 3 is a main cross-sectional view of an active matrix substrate according to the present invention. 1.11...Insulating substrate 2.6.12...Polysilicon thin film 3.13
......Gate insulating film 5.14...Gate electrode 7...Silicon oxide film 10.19...Pixel drive electrode or higher Suwa Seiko Co., Ltd. meeting
Claims (1)
成したアクティブマトリクス基板において、ゲート電極
を形成後にＳｉ薄膜を形成する工程と、前記Ｓｉ薄膜上
からイオン注入を行う工程と、イオン注入後に前記Ｓｉ
薄膜を酸化する工程とを含むことを特徴とするアクティ
ブマトリクス基板の製造方法。In an active matrix substrate in which a MOS type thin film transistor array is formed on an insulating substrate, there are a step of forming a Si thin film after forming a gate electrode, a step of performing ion implantation from above the Si thin film, and a step of performing ion implantation on the Si thin film after ion implantation.
1. A method of manufacturing an active matrix substrate, comprising the step of oxidizing a thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60016745A JPS61176155A (en) | 1985-01-31 | 1985-01-31 | Manufacture of active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60016745A JPS61176155A (en) | 1985-01-31 | 1985-01-31 | Manufacture of active matrix substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61176155A true JPS61176155A (en) | 1986-08-07 |
Family
ID=11924803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60016745A Pending JPS61176155A (en) | 1985-01-31 | 1985-01-31 | Manufacture of active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61176155A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63305872A (en) * | 1987-06-08 | 1988-12-13 | Sanyo Scott Kk | Virucidal sheet |
-
1985
- 1985-01-31 JP JP60016745A patent/JPS61176155A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63305872A (en) * | 1987-06-08 | 1988-12-13 | Sanyo Scott Kk | Virucidal sheet |
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