JPS6117298A - Test method of large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To shorten a testing time of a large-scale integrated circuit and to reduce a test cost by testing simultaneously an ROM and RAM. CONSTITUTION:An integrated circuit is set to an test mode by a ROM/RAM test mode specifying means 16. An ROM address specifying means 12 specifies an address by one step from zero address and transfers ROM data to an RAM through a data bus. As soon as the overall bit writing to the RAM is terminated, an RAM address specifying means 14 starts again at zero address to read data. The ROM address specifying means 12 re-starts at the moment all the RAM data is completely outputted, begins the specifying the address next to that at the stopping. Said procedure is repeated until all data in the ROM is transferred to the RAM. Thus testing of the ROM and RAM can be executed simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention eliminates the drawbacks of conventional testing methods for large-scale integrated circuits that include ROM and RAM in one chip semiconductor substrate, and efficiently performs device tests. It concerns testing methods.

Conventional configurations and their problems In recent years, large-scale integrated circuits have become multi-functional and complex, incorporating digital-to-analog converters, CPUs, timer circuits, liquid crystal and fluorescent display tube drive circuits into one chip. It has become. One-chip microcomputers and the like are equipped with large-capacity ROMs and RAMs in addition to the above-mentioned circuits, and in particular, efforts are being made to increase the capacity of RAMs.

A conventional method of testing to confirm bit loss in ROM and RAM provided in one chip will be described below.

FIG. 1 is an example of a block diagram of a conventional ROM bit loss confirmation test means. 1 is ROM, 2 is ROM a)
It is a means for specifying a response, and consists of a counter circuit, a latch, etc. 3 is a peripheral terminal, and 4 is a test signal generating means.

The operation of the ROM bit loss confirmation test method performed by the conventional ROM test means configured as described above will be described below.

First, the test means 4 sets the integrated circuit to the ROM-1 test mode. At this time, the ROM address designating means 2 is in a mode that starts from designating address 0 and sequentially designates addresses one by one, and designates the ROM address from address 0 to the final address. The ROM data at the specified address is output to the peripheral terminal 3, and the L
A bit drop test is performed by an SI tester.

FIG. 2 is an example of a block diagram of a RAM bit loss confirmation test means. 6 is a RAM, 6 is a test means, 7 is a peripheral terminal, 8 is a data write signal path to the RAM, and 9 is a RAM data read signal path.

The operation of the RAM bit loss confirmation test method performed by the conventional RAM test means configured as described above will be described below.

First, the test means 6 sets the RAM test mode. At this time, the data write signal to the RAM,
The data read signal can be generated arbitrarily.

Further, RAM address designation can also be set arbitrarily from the peripheral terminal 7. The address data and write data of the RAM are transferred from the peripheral terminal 7 to the RAM, respectively, and the entire area data is written to the specified address by the write signal on the path 8. After writing is completed, the read signal on path 9 transfers the RAM data to peripheral terminal 7 and outputs it to RAM.
A bit loss confirmation test for M is performed using an LSI tester.

However, if ROM and RAM are on the same chip,
In addition, since the data bus for data transfer is often shared, the test method described above
Each of the M tests must be performed independently. R.O.
The problem arises that the larger the capacity of M and the RAM, the longer the test time.

Purpose of the Invention The present invention is intended to solve the above-mentioned conventional problems.
It is an object of the present invention to efficiently test a large-scale integrated circuit including an OM and a RAM in one chip, and to shorten test time.

DESCRIPTION OF THE INVENTION The present invention is a method for testing an integrated circuit that includes a ROM test means and a RAM test means, and allows two memory tests to be performed simultaneously, thereby reducing the test time.

DESCRIPTION OF THE EMBODIMENT FIG. 3 shows a block diagram of a ROM and RAM simultaneous test means in an embodiment of the present invention.

3. 11 is ROM, 12 iROM7 address designation means, 13 is RAM 114 is RAM address designation means, 15 is ROM address designation prohibition means, 16 is RO
M, RAM test mode designation means, 17 peripheral terminals, 1
8 is a RAM write signal line, and 19 is a RAM read signal line.

The ROM of this embodiment is configured as described above.

The operation of the RAM simultaneous test method will be explained below based on the block diagram of FIG.

First, the integrated circuit is set to a test mode by the ROM/RAM test mode specifying means 16.

ROM addressing circuit 12 is at address 0! The RAM address designating means 14 operates in synchronization with the 010M data output, which performs addressing in 71 steps and transfers the ROM data to the RAM via the data bus, and at the same time the signal a
18 RAM write signals are generated, and ROM data is sequentially written from address 0 of the RAM. When the ROM data is written to the final address of RAM, the ROM
ROM address specification is temporarily prohibited by the address specification prohibition means 16. The ROM addressing means 12 stops while maintaining the previous state and is in a waiting state until all the RAM data is output.The RAM addressing means 14 starts reading the data at the same time as all bits have been written to the RAM. Therefore, it starts again from address 0. At the same time as all RAM data is finished outputting, it starts from address 0.
The OM address specifying means 12 starts specifying from the next address when restarting or stopping, and performs the above operations in the ROM.
4Q, ROM, and RAM can be tested at the same time by repeating the test until all data is transferred to RAM.

Effects of the Invention According to the present invention, testing time for large-scale integrated circuits can be shortened and test costs can be reduced by testing ROM and RAM at the same time, and this effect becomes greater as the RAM capacity increases. 5. An excellent method for testing large-scale integrated circuits can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional ROM test means, FIG. 2 is a block diagram of a conventional RAM test means, and FIG. 3 is a block diagram of a ROM and RAM simultaneous test means according to an embodiment of the present invention. 11...ROM, 12...ROM address designation means, 13...RAM, 14...
...RAM address 5 specifying means, 16...
・ROM address specification prohibition means, 16...RO
M/RAM test mode specifying means, 17... peripheral terminal, 18... RAM write signal, 1e.
...RAM read signal. Name of agent: Patent attorney Toshio Nakao and 1 other person31
Figure I @ 2 Figure

Claims (1)

[Claims] A large-scale integrated circuit with read-only memory (ROM) and random access memory (RAM) on a single chip semiconductor substrate includes a test circuit that can read ROM data and RAM data, and write data to RAM at will. . A method for testing a large-scale integrated circuit, characterized in that a bit loss test of the ROM data and RAM data is performed simultaneously.