JPH02143984A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten test time and to improve productivity by performing a test on every selecting word line. CONSTITUTION:A test mode is executed on every unit of selective word line. In other words, all the data are written on a memory cell 3 on the selective word line 1 so as to become the same data, and the data in each memory cell 3 on the selective word line 1 appears on each bit line 2. The data on each bit line 2 is set at an 'H' level or an 'L' level by respective sense amplifier. In a normal mode, one of bit lines is selected, and no data on another bit lines is tested. In the test mode, the data on all the bit lines 2 are effectively used. In such a way, the test time can remarkably be shortened by employing a system to perform the test simultaneously at every unit of selective word line.

Description

[Detailed Description of the Invention] Field of Application in UM Industry] This invention relates to a semiconductor memory device, and particularly to a test circuit thereof.

[Conventional Technique fr] FIG. 3 is a block diagram of a data output system of a conventional "l!: conductor device.

In the figure, (1) is a word line, (2) is a bit line, (
3) is a memory cell selected by a word line (1) and a bit line (2), (4) is a memory cell block constituted by a plurality of word lines and bit lines, (5) is an output control circuit, and (6) is a memory cell block selected by a word line (1) and a bit line (2). ) is the I10 line that connects the selected memory cell (3) and the output control circuit (5), (7) is the test mode control signal that sets the output control circuit (5) to normal mode or test mode, ( 8) is the output signal of the output control circuit.

Next, the operation will be explained using a dynamic semiconductor memory device as an example.

In order to test whether information is stored and read normally, there are two test methods: normal mode and test mode.

In normal mode, to read written information, use word i! (1) and the bit line (2), the data of the selected memory cell (3) is transferred to the I10 line (6) for each memory cell block (4).
) are respectively input to the output control circuit (5). At this time, since the output control circuit (5) is set to normal mode, only the signal of the selected block is output as the output signal.

In the test mode, data is manually input from each memory cell block (4) to the output control circuit (5) as in the normal mode, but the test mode control signal (
7), the output control circuit (5) performs data processing in the test mode.

Data processing in test mode is output control circuit (5)
This is a process of combining the data of each block (4) input into one block so that they can be tested simultaneously.

For example, if all the data in each block (4) is H', then H
If all the impedances are L', then L' is used, and if some are H' and some are L', then the old gh impedance is used.

Therefore, the output is an output signal that can check all data in each memory cell block (4).

[Problem to be solved by the invention] Since the conventional test mode is configured as described above, all outputs of the preamplifier are tested at the same time, so as the memory capacity increases, the test time decreases. This has the problem that the effect of shortening the length is weakened.

The present invention was made to solve the above-mentioned problems, and aims to shorten test time by performing test mode on a selected word line basis.

[Means and effects for solving the problem] The semiconductor memory device according to the present invention uses a method of simultaneously testing selected word lines, instead of the conventional method of simultaneously testing the outputs of preamplifiers, thereby greatly reducing the test time. can be shortened to

[Embodiment] An embodiment of the present invention will now be described with reference to the drawings. 1st
In the figure, (1) is a word line, (2) is a bit line, (
3) is a memory cell selected by a word line (1) and a bit line (2); (4) is a memory cell block constituted by a plurality of word lines (1) and bit lines (2);
(5) is an output control circuit; (6) is an I10 line that connects the selected memory cell (3) and the output control circuit (5);
7) is a test mode control signal that sets the output control circuit (5) to normal mode or test mode, (8) is the output signal of the output control circuit (5), (9) is an unselected bit line, (10) is a test circuit that processes data at the selected word line level.

When the normal mode is selected, the output control circuit (5) outputs only the data of the selected memory cell of the selected block (4) as an output signal, as in the conventional case. When test mode is selected, the preamplifier output of each block (4) is disabled.
A test circuit (1) that processes data in units of word lines (1)
The output data processed in step 0) is integrated and processed by the output control circuit (5), and the result is used as an output signal.

FIG. 2 is a circuit diagram of one embodiment of the test circuit (10). The test mode operation of the present invention will be explained with reference to the drawings.

The same data is written to all memory cells on the selected word line. When this word line is selected, the data of each memory cell on the selected word line is placed on each bit line -L. Data on each bit line is set to H' or L' level by each sense amplifier.

In the normal mode, one of the bit lines is selected and the data on the other bit lines are not tested. In the test mode of the present invention, data on all bit lines are effectively used by the configuration shown in the figure.

In the figure, if H' is stored in all BiL (Bito to Bitn), all paired Bits become "L" level due to the operation of the sense amplifier. Therefore, when Tr, , Tr2 are turned ON in the test mode, node 3 becomes "L level", node 1 becomes "L level", node 2 becomes "H'", and the output of the test circuit (10) is node 1 and node 1. It becomes the L level of NOR of 2. On the contrary, all B it (B ito ~
Even when δ is written into L' into B i tr+), node 3 becomes "L level," node node becomes "H level," node 2 becomes "L level," and the output becomes "L level."

In this way, when all the memory cells (3) can normally store data, the output of the test circuit (10) becomes "L". If there is a defective memory cell (3), both node 1 and node 2 will be at the "L" level, and the "H" level will be obtained as an output. In addition, if there is a defect in the sense amplifier, especially if the sense amplifier is always at L level (this refers to the case where both Bit and Bit are at L level,
), note 3 becomes H level, so note 1. Both nodes 2 become "L level", and a defect can be detected.

[Effects of the Invention] As described above, according to the present invention, since it is possible to test each selected word line, the test time can be shortened and productivity can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data output system of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the test circuit of FIG. 1, and FIG. 3 is a conventional semiconductor memory device. FIG. 2 is a block diagram of a data output system of FIG. In the figure, (1) is a word line, (2) is a bit line, (3) is a memory cell, (4) is a memory cell block, (5) is an output control circuit, (6) is an I10 line, (7) is a test mode control signal, (8) is an output signal of the output control circuit, (9) is an unselected bit line, and (10) is a test circuit. In addition, the same symbols in the figures indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 ΩTE~7 ] - Figure 3 Procedural amendment (voluntary) 1. Indication of the case Patent Application No. 1983-296518 2. Name of the invention Semiconductor storage device Representative of the person making the amendment Moriya Shiki 4, Agent 5, Detailed explanation of the invention column 6 of the specification subject to amendment, Contents of the amendment (1) "Output control circuit (5)" in the third line of page 2 of the specification Correct the statement to read "output control circuit (5)."that's all

Claims (1)

[Claims] A semiconductor memory device comprising a memory cell array consisting of a plurality of word lines, bit lines, and groups of memory cells located at the intersections of these, and comprising means for testing the storage capacity of the memory cells in units of selected word lines. .