JPH02107981A - Semiconductor integrated circuit incorporated in memory - Google Patents

Abstract

PURPOSE:To reduce the number of signal observation terminals by enabling the discrete control of multiplexer circuits in regard to an address signal, a data input signal, a write enable signal and a block select signal. CONSTITUTION:A latch circuit 19 is provided with an input terminal 20, an output terminal 21 and a clock terminal 22. Select control signals of an address signal, a data-in signal, a write enable signal and a block select signal are supplied from the circuit 19, and the input terminal 20 of the circuit 19 is connected commonly with an address signal terminal 10 of a test. Accordingly, a terminal for the test being necessary for the selection control of multiplexer circuits 8 is secured by the clock terminal 22 alone. According to this constitution, an address signal observation terminal and a data-in signal observation terminal can be dispensed with.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testability design method for semiconductor integrated circuits.

[Conventional technology]

8 and 9 are 1o circuit diagrams of a semiconductor integrated circuit equipped with a conventional multiplexer-type memory test auxiliary circuit. FIG. 8 shows the normal operation mode, and FIG. 9 shows the memory test mode. It shows.

In the figure, 111 is a memory circuit, 12) is an address signal terminal, 131 is a data-in signal terminal, 41 is a write enable signal terminal, 161 is a block select signal terminal, (
61 is a data out signal terminal, (?lL) and (7b
) tfi logic circuit, (8) is a multiplexer circuit, (9
1 is the control terminal of the multiplexer circuit, +101 is the test address signal terminal, aυ is the test data-in signal terminal, 0 is the test write enable signal terminal, (ll
is the test block select signal terminal, a4 is the address signal observation terminal, a (to) is the data in signal observation terminal, trowel is the write enable signal w4 observation terminal, 1η is the block select signal observation terminal, US is the data out signal observation terminal It is.

8 and 9 only show the interconnection between the memory circuit Il+, the logic circuit (7a) rib), and the multiplexer circuit (8), and the +a buried circuit (?a) (Wb)
Dark connections etc. are omitted.

Next, the operation will be explained.

When the multiplexer circuit (8) is switched to the logic circuit ('Ia) side using the control a terminal (9) as shown in Figure 8, the logic circuit (?lL) and the memory circuit...the dark signal is connected and the circuit is activated as a semiconductor integrated circuit. The desired normal operation can be performed.

Conversely, the control terminal (9) connects the multiplexer circuit (8) to the test terminal +101, υ, (1
(If you switch to llga, you can apply any test signal to the memory circuit from these test terminals. If you also use the data out signal observation terminal Q81 in this state, all of the memory circuits... Since the signals can be observed or controlled from the outside, the memory circuit il+ can be tested in the same way as a single memory integrated circuit.

As a semiconductor integrated circuit, in addition to testing the memory circuit, the logic circuit r7a) (Wb) must also be tested.10 When testing the logic circuit (?a), the output signal to the memory circuit il+ It is essential to observe Therefore, as shown in FIGS. 8 and 9, it is necessary to provide an address signal observation terminal Q4, a data-in signal observation terminal QIA, a write enable signal observation terminal ae, and a block select signal observation terminal θη.

[Problem to be solved by the invention]

Conventional memory test auxiliary circuits are configured as described above, and require a large number of address signal observation terminals and data-in signal observation terminals (for example, in a 256-word x 8-tlit memory circuit, 8 of each: 16 in total). However, there was a problem in that the package cost of the semiconductor integrated circuit increased, making it impossible to obtain a cheap semiconductor integrated circuit.

〔the purpose〕

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit with a built-in memory in which the number of address signal observation terminals and data-in signal observation terminals can be reduced.

[Means to solve the problem]

The semiconductor integrated circuit with a built-in memory of the present invention is configured so that the control of the multiplexer circuit can be performed independently with respect to all address signals, data input signals, write enable signals, and pro rack select signals.

[Effect]

In the semiconductor integrated circuit with a built-in memory of the present invention, by independently switching the control signals of the multiplexer circuits, the address signal input to the memory circuit can be indirectly transmitted to the data out terminal of the memory circuit. It also becomes possible to transmit the data-in signal input to the memory circuit to the data-out terminal of the memory circuit by a write operation.

As a result, the address signal and data-in signal output from the logic circuit can be observed via the data act signal observation terminal, so the address signal observation terminal and data-in signal observation terminal can be deleted.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

1 to 6 are circuit diagrams of semiconductor integrated circuits according to the present invention, and each is the same circuit.

However, the selection state of the multiplexer circuit (8) is different in each figure. Figure 1 is during normal operation, Figure 8 is during memory test, Figure 3 is when observing address signal, and Figure 4 is when observing write enable signal. , FIG. 6 shows the selection state when observing the block select signal, and FIG. 6 shows the selection state when observing the data-in signal.

In the figure, (9a), (9b), r9(ri) and (9d) are an address signal selection control terminal, a data-in signal selection control terminal, a write enable signal selection control terminal, and a block select signal selection control terminal. Other symbols are the same as those in the prior art.

Next, the operation will be explained.

FIG. 1 corresponds to the conventional FIG. 8, and since all the multiplexer circuits (8) of t'' select the logic circuit (?a) side, normal operation as a semiconductor device can be performed.

Figure 8 corresponds to the conventional Figure 9, and all the multiplexer circuits (8) select the test terminals (101 to 01 side), so all input signals of the memory circuit Il+ can be controlled externally. If the data out signal observation terminal 01 is used in this state, all signals of the memory circuit +11 can be observed or controlled from the outside, so the memo circuit 41rJK can be treated as a single memory integrated circuit. A similar test can be performed.

Figure 8 shows the logic circuit r? It shows the selected state of the multiplexer circuit (8) when observing the address signal from a). As shown in the figure, a write enable signal and a block select signal are applied from the test terminal Tl2101 to set the memory circuit (1) in a read state. Further, the multiplexer circuit (8) is controlled so that the address signal is applied to the memory circuit il+ from the logic circuit (?a) side.

At this time, the memory circuit 111K has previously written data such that the address signal is transmitted to the data out signal terminal (6), such as 0.1 at address 0, 2 at Fi1%2 address, etc. There is a need. If these conditions are met, the address signal is transmitted to the data act signal terminal 1B), and observation via the data out signal observation terminal 011 becomes possible. Note that at this time, since a write operation to the memory circuit is not performed, either side of the multiplexer circuit +81tlj connected to the data-in signal terminal 131 may be selected.

FIG. 4 shows the selected state of the multiplexer circuit (8) when all write enable signals from the logic circuit (?a) are observed. As shown in the figure, the write enable signal is applied from the logic circuit (7a) side, and the block select signal is applied from the test terminal 0. At this time, the block select signal is set to an unselected state so that writing is not performed in the memory circuit (1). this is! I
/c3 As mentioned in the explanation of the figure, the memory circuit... has an address signal that is transmitted to the data out signal terminal (61) such as θ address 0.1 address 1.2 address 2, etc. This is to prevent the data from being destroyed since it has been written in advance.

Note that either side of the multiplexer circuit (8) connected to the address signal and the data-in signal may be selected. The write enable signal is observed through the write enable signal observation terminal all.

FIG. 5 shows the selection state of the multiplexer circuit (8) when observing the block select signal t from the logic circuit (7a). As shown in the figure, the block select signal is applied from the logic circuit (?a) side and the write enable signal is applied from the test terminal. At this time, the write enable signal is set to a read state so that writing to the memory circuit 111 is not performed. Again, either side of the memory circuit multiplexer circuit (8) may be selected. Block select signal observation is performed via block select signal observation terminal Gη.

FIG. 6 shows the selection pattern m of the multiplexer circuit (8) when observing the data-in signal from the logic circuit r7a). Data in signal as shown in the figure? logic circuit r7
From the a) side, connect the address signal, write enable signal, and block select signal to the test terminal t101 rJ
' Add from 40m.

The data-in signal from the logic circuit (?a) is sent to the memory circuit i.
Write to a specific address (for example, address 0) of l+.

Observation is performed via the data-out signal observation terminal aIl'ft by reading from the data-out signal terminal (6). Therefore, since the data at the specific address used at this time is destroyed, it is necessary to write the original data (for example, 0) to the specific address (for example, address 0) of the fan after observing the data-in signal.

As described above, as shown in FIGS. 1 to 6, it is necessary that the multiplexer circuits (8) for address signals, data input signals, write enable signals, and block select signals can be controlled independently. That is, the address signal selection control terminal (9a) and the data-in signal selection terminal (9t+
), Light Ine FIG. 7 shows another implementation of this invention F14Jt
- The book shown is a circuit diagram of a semiconductor integrated circuit in which a latch circuit WlrQlt is provided in order to reduce the number of selection control terminals of the multiplexer circuit (8). The output terminal - is the clock terminal of the latch circuit (1ll). The selection control signals of the address signal, data-in signal, write enable signal, and block select signal are output terminal 3I of the latch circuit a-.
Since the input terminals of the latch circuits W and 4 are commonly connected to the test address signal terminal 1101, the only test terminal required is the clock terminal -. It's over.

Therefore, the number of test terminals can be reduced.

A more inexpensive semiconductor integrated circuit can be obtained.

〔Effect of the invention〕

According to the present invention, since the control signals of the multiplexer paths are switched independently, the number of address signal observation terminals and data-in signal observation terminals can be reduced. A semiconductor integrated circuit can be obtained.

[Brief explanation of drawings]

1 to 6 are [01 circuit diagrams] of a semiconductor integrated circuit showing one embodiment of the present invention, in which FIG. 1 is during normal operation, FIG. 8 is during a mesori circuit test, and FIG. 8 is an address signal , at the time of observation, FIG. 4 shows the time when the write enable signal is observed, FIG. 6 shows the time when the block select signal is observed, and FIG. 6 shows the time when the data-in signal is observed. FIG. 7 is a circuit diagram of a semiconductor integrated circuit showing another embodiment of the present invention, FIG. 8 is a circuit diagram of a conventional semiconductor integrated circuit (during normal operation), and FIG. 9 is a test time of the memory circuit shown in FIG. FIG. In the figure, ... is a memory circuit, 12) is an address signal terminal, (
3I is a data in signal terminal, (41 is a write enable signal terminal, +511'i block select signal terminal, 1
61ti data out signal terminals, (7a) and (7b
) is a logic circuit, (8) is a multiplexer circuit, +91F
i multiplexer circuit control terminal, r9a) is address signal selection control terminal, (9b) is data in signal selection control terminal, (9c) is write enable signal selection control terminal, (9d) is block select signal selection control terminal, 1101 is the test address signal terminal, Uυ is the test data-in signal terminal, uflJ is the test write enable signal terminal, O'4 is the test block select signal terminal, 04 is the address signal observation terminal, %1151 is the data-in signal observation terminal. terminal, a4 is write enable signal observation terminal, aη is block select signal observation terminal, Ol
is the data out signal observation terminal, U- is the latch circuit, - is the input terminal of the latch circuit, @D is the output terminal of the latch circuit,
- is the clock terminal of the latch circuit. In Figure 1, the same symbols indicate the same or equivalent parts.

Claims (1)

[Claims] The address signal, data input signal, write enable signal, and block include means for switching the address signal, data input signal, write enable signal, and block select signal of the built-in memory with an external test signal. A semiconductor integrated circuit with a built-in memory, characterized in that means for switching select signals can be independently controlled.