JPS61171312U - - Google Patents
Info
- Publication number
- JPS61171312U JPS61171312U JP5400685U JP5400685U JPS61171312U JP S61171312 U JPS61171312 U JP S61171312U JP 5400685 U JP5400685 U JP 5400685U JP 5400685 U JP5400685 U JP 5400685U JP S61171312 U JPS61171312 U JP S61171312U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power amplification
- amplification circuit
- pass filter
- driven
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案を説明する回路ブロツク図、
第２図は実施例を示す回路図、第３図イは第１お
よび第２電力増幅回路の周波数特性図、第３図ロ
は負荷端子における周波数特性図、第４図は従来
例を説明するマルチアンプシステムのブロツク図
、である。
１１……電１電力増幅回路、１２……第２電力
増幅回路、１３……低域フイルタ回路、１４……
高域フイルタ回路、１５……位相反転回路。
Figure 1 is a circuit block diagram explaining this idea.
Fig. 2 is a circuit diagram showing an embodiment, Fig. 3 A is a frequency characteristic diagram of the first and second power amplifier circuits, Fig. 3 B is a frequency characteristic diagram at the load terminal, and Fig. 4 explains a conventional example. 1 is a block diagram of a multi-amplifier system. 11... Electric power amplifier circuit 1, 12... Second power amplifier circuit, 13... Low-pass filter circuit, 14...
High-pass filter circuit, 15...phase inversion circuit.
Claims (1)
高域フイルタ回路を介した第２電力増幅回路とを
互に逆相で駆動し、前記第１電力増幅回路の出力
端子と前記第２電力増幅回路の出力端子間に負荷
を接続するようにしたことを特徴とする電力増幅
器。 A first power amplification circuit via a low-pass filter circuit and a second power amplification circuit via a high-pass filter circuit are driven in opposite phases to each other, and the output terminal of the first power amplification circuit and the second power amplification circuit are driven in opposite phases. A power amplifier characterized in that a load is connected between the output terminals of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5400685U JPS61171312U (en) | 1985-04-10 | 1985-04-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5400685U JPS61171312U (en) | 1985-04-10 | 1985-04-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61171312U true JPS61171312U (en) | 1986-10-24 |
Family
ID=30575384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5400685U Pending JPS61171312U (en) | 1985-04-10 | 1985-04-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61171312U (en) |
-
1985
- 1985-04-10 JP JP5400685U patent/JPS61171312U/ja active Pending