JPS6183317U - - Google Patents

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Publication number
JPS6183317U
JPS6183317U JP16813484U JP16813484U JPS6183317U JP S6183317 U JPS6183317 U JP S6183317U JP 16813484 U JP16813484 U JP 16813484U JP 16813484 U JP16813484 U JP 16813484U JP S6183317 U JPS6183317 U JP S6183317U
Authority
JP
Japan
Prior art keywords
power amplifier
output terminal
positive
negative
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16813484U
Other languages
Japanese (ja)
Other versions
JPH0418247Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16813484U priority Critical patent/JPH0418247Y2/ja
Publication of JPS6183317U publication Critical patent/JPS6183317U/ja
Application granted granted Critical
Publication of JPH0418247Y2 publication Critical patent/JPH0418247Y2/ja
Expired legal-status Critical Current

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  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の増幅装置の構成を示す図、第
2図および第3図は従来の増幅装置の構成を示す
図である。 1は電力増幅器、2aは電圧増幅部、2bは電
力増幅部、3は正側の出力端子、4は負側の出力
端子、5は帰還回路、6は電源トランス、7は整
流回路、8,9は第1、第2の平滑コンデンサ、
10は電源トランスの中間端子、11は第1、第
2の平滑コンデンサの接続点、12は直流電源回
路、13,14は電源供給端子、15は負荷、1
6は増幅器、17は位相反転回路、18,19は
第1、第2の帰還ループの配線部、20,21は
第1、第2の導線である。
FIG. 1 is a diagram showing the configuration of an amplifying device according to the present invention, and FIGS. 2 and 3 are diagrams showing the configuration of a conventional amplifying device. 1 is a power amplifier, 2a is a voltage amplification section, 2b is a power amplification section, 3 is a positive output terminal, 4 is a negative output terminal, 5 is a feedback circuit, 6 is a power transformer, 7 is a rectifier circuit, 8, 9 are first and second smoothing capacitors;
10 is an intermediate terminal of a power transformer, 11 is a connection point between the first and second smoothing capacitors, 12 is a DC power supply circuit, 13 and 14 are power supply terminals, 15 is a load, 1
6 is an amplifier, 17 is a phase inversion circuit, 18 and 19 are wiring sections for the first and second feedback loops, and 20 and 21 are first and second conductive wires.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧増幅部2a、電力増幅部2bおよび当該電
力増幅部2bの出力を正側の出力端子3から取り
出すようにするとともに、帰還回路5を介して上
記電圧増幅部2aの入力側へ負帰還ループを形成
した電力増幅器1と、電源トランス6、整流回路
7および当該整流回路7に接続された正側、負側
の第1、第2の平滑コンデンサ8,9とからなる
直流電源回路12とを具備し、当該直流電源回路
12の第1、第2の平滑コンデンサ8,9の正極
端子8a、負極端子9bを上記電力増幅器1の電
源供給端子13,14にそれぞれ接続し、上記第
1、第2の平滑コンデンサ8,9の接続点11を
上記電力増幅器1の負側の出力端子4に接続する
とともに、正側、負側の出力端子3,4に負荷1
5を接続するようにした増幅装置であつて、上記
電力増幅器1の負側の出力端子4または第1、第
2の平滑コンデンサ8,9の接続点11に生じる
寄生信号成分を上記電力増幅器1の電圧増幅部2
a、電力増幅部2bを経て正側の出力端子3に利
得「1」で正帰還する第2の帰還ループを形成し
た増幅装置において、上記電力増幅器1の正側の
出力端子3、負側の出力端子4または上記第1、
第2の平滑コンデンサ8,9の接続点11に第1
、第2の導線20,21をそれぞれ接続し、当該
第1、第2の導線20,21をより合わせて上記
第1の帰還ループ、第2の帰還ループの配線部1
8,19としたことを特徴とする増幅装置。
The voltage amplification section 2a, the power amplification section 2b, and the outputs of the power amplification section 2b are taken out from the positive output terminal 3, and a negative feedback loop is connected to the input side of the voltage amplification section 2a via the feedback circuit 5. The DC power supply circuit 12 includes the power amplifier 1 and a power transformer 6, a rectifier circuit 7, and first and second smoothing capacitors 8, 9 on the positive side and negative side connected to the rectifier circuit 7. Then, the positive terminals 8a and negative terminals 9b of the first and second smoothing capacitors 8 and 9 of the DC power supply circuit 12 are connected to the power supply terminals 13 and 14 of the power amplifier 1, respectively, and the first and second The connection point 11 of the smoothing capacitors 8 and 9 is connected to the negative output terminal 4 of the power amplifier 1, and the load 1 is connected to the positive and negative output terminals 3 and 4.
5 is connected to the power amplifier 1, and the parasitic signal component generated at the negative side output terminal 4 of the power amplifier 1 or the connection point 11 of the first and second smoothing capacitors 8 and 9 is connected to the power amplifier 1. voltage amplification section 2
a. In an amplifier device forming a second feedback loop that provides positive feedback with a gain of "1" to the positive output terminal 3 via the power amplifier 2b, the positive output terminal 3 of the power amplifier 1 and the negative output terminal 3 of the power amplifier 1 are connected. Output terminal 4 or the first
At the connection point 11 of the second smoothing capacitors 8 and 9, the first
, the second conductive wires 20 and 21 are connected, respectively, and the first and second conductive wires 20 and 21 are twisted together to form the wiring section 1 of the first feedback loop and the second feedback loop.
8.19.
JP16813484U 1984-11-06 1984-11-06 Expired JPH0418247Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16813484U JPH0418247Y2 (en) 1984-11-06 1984-11-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16813484U JPH0418247Y2 (en) 1984-11-06 1984-11-06

Publications (2)

Publication Number Publication Date
JPS6183317U true JPS6183317U (en) 1986-06-02
JPH0418247Y2 JPH0418247Y2 (en) 1992-04-23

Family

ID=30725914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16813484U Expired JPH0418247Y2 (en) 1984-11-06 1984-11-06

Country Status (1)

Country Link
JP (1) JPH0418247Y2 (en)

Also Published As

Publication number Publication date
JPH0418247Y2 (en) 1992-04-23

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