JPS61146099U - - Google Patents
Info
- Publication number
- JPS61146099U JPS61146099U JP2951485U JP2951485U JPS61146099U JP S61146099 U JPS61146099 U JP S61146099U JP 2951485 U JP2951485 U JP 2951485U JP 2951485 U JP2951485 U JP 2951485U JP S61146099 U JPS61146099 U JP S61146099U
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- lch
- connect
- parallel connection
- rch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は従来のマトリクス回路によつて構成さ
れるサラウンドシステム、第２図は本考案の一実
施例によつて構成されるサラウンドシステム、第
３図は第２図の回路８の具体的実施例を示す図、
第４図は第２図及び第３図における、Ｌｃｈ，Ｒ
ｃｈの周波数特性を示す図である。
６……フロント用Ｒｃｈスピーカ、７……フロ
ント用Ｌｃｈスピーカ、８……周波数特性を有す
る回路、Ｌ……インダクタンス。
FIG. 1 shows a surround system constructed by a conventional matrix circuit, FIG. 2 shows a surround system constructed by an embodiment of the present invention, and FIG. 3 shows a specific implementation of the circuit 8 in FIG. Diagram showing an example,
Figure 4 shows Lch, R in Figures 2 and 3.
FIG. 3 is a diagram showing frequency characteristics of channels. 6... Front Rch speaker, 7... Front Lch speaker, 8... Circuit having frequency characteristics, L... Inductance.
Claims (1)
に、それぞれＬｃｈ及びＲｃｈスピーカの＋端子
（または−端子）を接続し、−端子（または＋端
子）を共通接続して、インダクタンスと抵抗との
並列接続回路を介してアンプのスピーカ出力端子
の一端子に接続したことを特徴とするマトリクス
回路。 (2) 前記並列接続回路は、その定数を可変でき
るようにした実用新案登録請求の範囲第１項記載
のマトリクス回路。[Claims for Utility Model Registration] (1) Connect the + terminals (or - terminals) of the Lch and Rch speakers to the Lch and Rch speaker output terminals of the amplifier, respectively, and connect the - terminals (or + terminals) in common. , a matrix circuit characterized in that it is connected to one terminal of a speaker output terminal of an amplifier via a parallel connection circuit of an inductance and a resistor. (2) The matrix circuit according to claim 1, wherein the parallel connection circuit has a variable constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2951485U JPS61146099U (en) | 1985-03-01 | 1985-03-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2951485U JPS61146099U (en) | 1985-03-01 | 1985-03-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61146099U true JPS61146099U (en) | 1986-09-09 |
Family
ID=30528392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2951485U Pending JPS61146099U (en) | 1985-03-01 | 1985-03-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61146099U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4839002A (en) * | 1971-09-20 | 1973-06-08 | ||
| JPS4914103A (en) * | 1972-05-16 | 1974-02-07 |
-
1985
- 1985-03-01 JP JP2951485U patent/JPS61146099U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4839002A (en) * | 1971-09-20 | 1973-06-08 | ||
| JPS4914103A (en) * | 1972-05-16 | 1974-02-07 |