JPS61170143A - Device for coding and decoding - Google Patents

Abstract

PURPOSE:To decrease the entire code length while keeping the correction capability by regarding a check part of an original code as a part of information to form a overlapped code and applying addition of modulo to the code. CONSTITUTION:The information inputted from an information input terminal 4 is coded by a Cr coder 6 at each K-bit and converted into an n-bit code word. The operation above is repeated by N times, a UR coder 7 generates a check symbol of (N-k) on a GF(2<n-k>) from a check part of the code word Co while regarding it as K symbol information to form an N-symbol code word, an adder A1 applies addition of modulo 2, and each symbol of the check part of the code word Co and the code UR is subject to addition of modulo 2 corresponding to a bit. Then a synthesized code word Cz is obtained. An internal recovery check vector is formed by an information part of the reception vector and addition of modulo 2 is applied to the check part of the reception vector. When an error is within the correction capability range of the code UR, it is corrected entirely and the code word UR transmitted from the transmission side is recovered by a UR recovery device 10. In applying reception vector modulo 2 addition to the code word UR decoded correctly by a UR decoder 11, a received word of the code word Co is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction code encoding and decoding device.

[Conventional technology]

Conventional code for this kind of equipment? The codeword format used was shown in Figure 811. In the figure, 1 is an information symbol part, 2 is a check symbol part, and 3 is a code Cr.
The encoding direction is shown.

As shown in the figure, the error V added on the information transmission path is corrected by the code Cr on the decoding side of the transmitted Ig code. In other words, the code Cr is divided into an information symbol part 1 and a check symbol part 2 along the encoding direction B, and is inspected, and only if there is an error is corrected before decoding. .

[Problem that the invention seeks to solve]

Since the conventional encoding and decoding apparatuses were configured as described above, there was a problem in that the redundant portion was large for a given correction ability, resulting in a decrease in reliability.

This invention was made in order to solve all of these six problems, and when decoding, redundant check symbols with respect to correction ability are regarded as part of the information in the full convolution code, and the information symbols and check symbols are completely integrated. 2, encode it into a superimposed code, add it to the code word 6 of the original code Cr, and generate a part of the check symbol from the transmission vector? It is an object of the present invention to provide an encoding and decoding device that cancels the code length and shortens the entire code length while maintaining full correction capability.

[Means for solving problems]

The encoding and decoding device according to the present invention has an n-symbol C
R encoders iN are superimposed, and the check symbols are encoded as information symbols of the full superimposed code Ua, and the original code word CO is added with the addition of puja? This eliminates the need to transmit part of the check vector of the source code.

[Effect]

In this invention, since the information vector of the superposition code and the check vector of the original Cr code are completely the same, the result of adding puja is always all zeros, and that much information can be omitted from the transmission vector. Therefore, the overall code length can be reduced without reducing the performance.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First of all, FIG. 1 shows a control circuit of an embodiment of this invention? The block connection diagram shown in FIG. 2 is a hardware configuration diagram of the encoding device of the present invention; FIG. 8 is a model diagram for explaining the encoding process of the present invention.

Next, in Figures #IJ1 and 2, 4 is an information input terminal, 5 is an information output terminal, 6 is an information Cr encoder, 7 is a UR encoder, 8 is a sent word memo + 7-19 is a received word memory, 1
0 is a UR regenerator, 11 is a UR decoder, 12 is a Cr decoder, A is a puja adder, A2 is a communication device, 16
1 is a noise, A5 is an encoding device, Ba is a decoding device, 14 is an address/data/control signal bus, and 15 is a control circuit. Further, in FIG. 3, 16 is a check symbol part of the superimposed code UR, and 17 is the Cr code word □ omitted from the transmission vector and the information part of the superimposed code.

In FIG. 1, information input from the information input terminal 4 is encoded bit by bit by a Cr encoder 6 and converted into an n-bit code word. When this operation is repeated N times, a code word e of N×n symbols as shown in FIG. 8(b) is generated. Next, encoding 2 of the superimposed code Ua is performed, and the OR encoder 7 generates all the check symbols of the symbol in N- on GF(2), considering it as all the symbol information from the polarization part of the code word 6, and generates the N symbol A name with a code word of gold. The more N X (
n −'k ) Obtain the thinnest rectangular arrangement.

Next, an adder shown in FIG. 1A performs the addition, and the check part of the code word Co and each symbol of the code U'a are added in correspondence with bits. □ Then, the composite code word C2 shown in FIG. 8 (dl) is obtained. This process will be explained in more detail below.

That is, on the transmitting side, a 1dcr encoder 7 generates a Co code word,
Letting the vector expression kCr(il in the first row), the equation (1) is obtained.

Crfil = (Kil, Qil)
-(1) All symbol information of superposition code UR in row il 1≦
When i≦K, it is expressed by equation (2).

Qi = C(il l1
(2) Also, when K+1≦i≦N, equation (3) is obtained.

Qi = V(il, drumming (3)
) However, V(il[is the check vector calculated by the encoding algorithm of the code UR. The vector representation of the first row of the composite code word C2 is assumed to be ξ1.

When 1≦i≦/:i = (Kkl, 0)...
・・・・・・(4) K+1≦i≦N timekeeper = (engineering (il, cttl + V(il)
...... (5) In equation (4) above, the zero vector does not need to be sent as information, so the transmission vector C
(If l≦i≦C(il=(尤(i))...
・・・・・・・・・ (6) When K+1≦i≦N, C(il=(尤(il), C(il+V(il)
・・・・・・・・・ (Becomes power.

In this way, the information part 17 of the Cr codeword and superimposed code obtained by omitting the first row vector Ci k from the transmission vector of dl is obtained in FIG. 8 (understand that the rectangular symbol part becomes an all-zero vector). can.

It is also understandable that this part does not always need to be sent.

Next, FIG. 4 is a block diagram showing the decoding side hardware, and FIG. 5 is a model diagram explaining the entire decoding process. Fourth
In the figure, 9 is a receiver 4i word memory, a 10UUR regenerator,
11i-jlJR decoder, 12ba Cr decoder, and 19 a control circuit.

Further, the reception vector is arranged as shown in FIG. 5 (at).The reception vector is expressed by equation (8).

Cz-(FL,, bird,...,RN,)...
......(8) For each element Ri, Ri = (r' (11, 0) R' - (ri (21, (1) RK - (rt (1<:l, 01RK+I
−(ri (K+l) p re (
tg+1))RN=(rL(Nl, rcf
Nl') That is, it is assumed that there is a zero vector in the upper right part of Fig. 5 (at).

Here, is the error vector added on the transmission path? (9)
Expressed by the formula Ei = (et, ec) -----
------- (9).

However, when ■≦i≦, e. -O″′C exists.

Next, from the information part of the received vector, the internal reproduction check vector C
Make a tray (Figure 5 (b)).

C(1=C4jl+5(jl...
...... (1'2 Here, 5fjl is an additional error caused by an error in the information section, which is called a correction syndrome here.The internal reproduction vector created in this way is received. Add the puja to the check part of the vector.

The received vector UR of the code UR is reproduced (Fig. 5(d)
)).

UR(jl-C(jl+ 5(jl+eo(jl
−・・・・・・030≦j≦ then e(B(jl=f) ・・・・・・
...(1Φ. Code UR(jl error 5(jl
-1-e. If tjl is within the correction capability range of the code UR, the code word UR that is completely corrected and sent from the transmitting side is regenerated by the UR regenerator 10 (FIG. 5(e)).

When the code word URf reception vector correctly decoded by the UR decoder 11 is added, the reception word co of the code word Co is obtained (FIG. 5(f)).

When 1≦j<lg, the j-th element is Cr(jl−(1(jl+et(jl, C(
jl) -・-When L15j>K, correct it with a normal strike force.

Since the information part of the superimposed code (K 1)・(n−k) symbols.

FIG. 6 is a diagram completely explaining the difference in reliability between information portions A and B of the present invention. That is, if we pay attention to the difference between information parts A and B in Figure 6, we can see that the information department public figures used to correct t errors using an n-bit code word, but with this method, the information in the inspection part can be corrected. is not sent, so the error rate is lowered by the vector of the test portion.

In other words, since there is no error in the communication path in the inspection unit, the superimposed code L
After correcting the error Sik in la, the error in the symbol part may be corrected in the Cr code word.

Now, if the code Cr has t-fold error correction capability, the probability of correction failure in the original Cr code word is expressed as Pf Ua.

However, the correction failure probability puucAF! of the code of the present invention! j
becomes.

Next, the hardware for actually adding the superimposed codes and extracting the original information on the decoding side will be explained below.

Now, code cr 'i (control circuit 15, UR decoder 11
, R8 (Reed-
8olomon) Sign is fully returned. Generator polynomial of code cr'
k G (Xl-1+X+.

FIG. 7 is an explanatory diagram of superimposing the check symbol 914 of the code UR on the check part of one code word Cr(jl) of the code Cr.

In the figure, 20 indicates the check part of Cr (jl code candy, 21 indicates the check symbol Qj of the UR code word, and 22 indicates the vector v+, +++c (the part of jl) in which both are superimposed. When Qj is the check vector of the Cr code word, This process can be omitted since it becomes an O vector and does not need to be transmitted.

Is Figure 8 the process of Figure 7? In the configuration diagram of the hardware to be executed, 26 is an information input terminal, 24 is an information output terminal, and A
, i puja adder, Dsu G[Xl= 1+x+x'
Division circuit by, S, , S2 is a switch, Exl
.

EX2 is an exclusive OR gate, F, , F2. F3
．． F, is a shift register with l-bit flip-flops. Initially switch S is closed, switch S2
is open, information Ki) is input from the information input terminal 26, and division is executed in the division circuit 1)s. Then, the information of K=11 pits is input and the division result of n-k=4 pits is sent to the flip-flops F,, F2. F8. Stored in F4. Next, the switch S1 is opened and the switch S2 is closed, and puja addition is performed using the input information and the puja adder A1. At this time, the check vector V(jl of the code UR calculated at the bottom is input from the terminal 26, and the puja addition is performed, and V(jl+c(jl) is output from the terminal 24.

Figure 9 shows how the received word Rj is converted to the original received word C on the receiving side.
In the diagram showing the process of extracting r(jl= (Kjl, CU), 25 is the receiving vector r equivalent to V(jl+c(jl) on the transmitting side. (jl part, 26 is Kjl on the transmitting side
rz (part of jl, 27 is the internal reproduction check vector C (part of jl, 28 is r. 29
is the element Q(jl, 6
0 is the j element Q of the decoded Ua (jlk is the check vector C of the Cr received word reproduced by addition of the received vector puja)
(It is jl.

★In addition, Fig. 10 is a diagram explaining all the hardware operations until all 28 vectors Qijl are extracted in Fig. 9, and 31
62 is an information input terminal, 62 is an information output terminal, 66 is a counter, 34U 4-bit latch register, 65 is an adder that performs all puja additions in correspondence with bits, 66 is a serial/parallel converter, 67 is a parallel/serial converter, Dr is G
(Division circuit by Xl=l+X+X', F,, F!,
F8. F4 is a 1-bit flip-flop, Qt,
Q2. Qa, contents of Q4id shift register, E
X, l EX2 is an exclusive OR gate, S, switches p, , p2H switch terminals. First, division is executed by the received word Rii divider Dr, which is serially input from the information input terminal 61. The counter 63' counts up to the number of information bits = 11, and the 11th bit division result is C(
j) and (4, Q, , Q, , Q4 are latched into the latch register 64.

Receiving vector checking section r. (jl is serial/parallel converted to become 4-bit parallel data, and the latched data C (jl and Q (jl) are added to the serial data and input to the parallel/serial converter 67 and output as serial data to terminal P and switch Ssk. It passes through and is output from the output terminal 62.

〔Effect of the invention〕

As explained above, according to the present invention, the inspection part of the original code is regarded as part of the information, and the entire superimposed code is created and it is used as an additional fee for the puja, so that part of the inspection part is always Since it becomes an all-zero vector and can be removed from the transmission vector, is the code length? It can be shortened without using gold foil, and has the effect of greatly improving the reliability of transmitted information.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram of an embodiment of this invention, FIG. 2 is a hardware configuration diagram of an encoding device of this invention, and FIG. 8 is an encoding process of this invention. The model diagram shown in Figure 4 is the decoding hardware of this invention? The block diagram shown in Fig. 5 is the decoding process of this invention? 6 is a reliability explanatory diagram of the information parts A and B of this invention, and FIG. 7 is a model diagram showing the reliability of information parts A and B of this invention. FIG. FIG. 8 is a circuit diagram showing an example of hardware that executes all the processes of cause 7, and FIG.
jl? Model diagram showing the process of separating and extracting gold, 1st
FIG. 0 is a block diagram of a hardware circuit that executes the entire process shown in FIG. 9, and FIG. 11 is an explanatory diagram of a conventional encoding format. In the figure, 6 is a Cr encoder, 7 is a (Ja encoder, 8 is a transmission word memory, Asfd encoder, Ao, As i'
j: a puja adder, 9 a receiving memory, 10 a ur decoder, 11 a UR decoder, and 12 a Cr decoder. Note that the same parts or corresponding parts are indicated by the same reference numerals. Patent Applicant Mitsubishi Electric Corporation Figure 3 (a) (b) (c) Box A1 Figure 5 (f) Figure 6 Figure 7 Figure 8: (i) 11] ] ( A1: 2 Addition date y8- Figure 9-1-27

Claims (1)

[Claims] a C_r encoder that adds (n-K) symbols of check symbols to encode K-symbol input information into an n-symbol codeword in a first direction; and a C_r codeword encoded by the C_r encoder. Of the test symbols obtained by overlapping N test symbols to form a code word C_o, K test symbols are converted into a code U in the second direction.
A composite code vector is generated through an N-symbol U_R encoder that encodes the information symbol of _R and creates (N-K) check symbols, and an adder that performs puja addition on the check part of the C_r code word. and an encoding device that transmits the information of the received word of the composite code vector transmitted from the encoding device, and reproduces an internal reproduction check vector from the information part of the received word of the composite code vector transmitted from the encoding device, and converts the check vector part of the K C_r codewords into the information of the U_R received word as it is. a regenerator for reproducing the regenerated vector; a U_R decoder for decoding the regenerated vector; and a regenerator for reproducing the regenerated vector; An encoding and decoding device comprising an adder for reproducing symbols and a decoder for decoding the received word, and reproducing information of the original N×K symbols transmitted.