JPH0555929A - Decoder - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by allowing an UR reproducing device to apply a UR code reproduction processing to a reception vector from which a zero vector part is eliminated while taking the zero vector part into account so as to reduce a code length without decreasing the error correction capability. CONSTITUTION:The decoder is provided with an UR reproducing device 10, in which an internal reproduction check vector is prepared from an information part of a received reception vector and an internal reproduction check vector is added to the reception vector in which a check part is added with the zero vector part eliminated at a sender side to reproduce the reception vector of a superimposing code, an UR decoder 11 decoding the superimposing code from the reception vector of the reproduced superimposing code, adders A1, A3 adding the decoded superimposing code and the reception vector to reproduce a code word Co and a Cr decoder 12 decoding input information from the code word Co. Thus, a signal resulting from eliminating a zero vector from a signal whose check part is all zero vector is received and the signal is decoded by taking the zero vector into account.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code decoding device.

[0002]

2. Description of the Related Art FIG. 12 shows a codeword format of a conventional error correction code. In the figure, 1 indicates an information symbol portion, 2 indicates a check symbol portion, and 3 indicates a coding direction of the code Cr.

The error of the information added on the transmission path is corrected by the code Cr on the decoding side of the transmission signal. That is, the code symbol Cr is divided into the information symbol portion 1 and the check symbol portion 2 along the coding direction 3 to be inspected. As a result, if there is an error, the information symbol is corrected and then decoded.

[0004]

Since the conventional encoding and decoding apparatus is constructed as described above, there is a problem that the redundant portion is large with respect to a predetermined correction capability and the transmission efficiency and reliability are lowered. was there. In addition, as prior art, IEEE TRANSACTIONS ON INF (IEEE TRANSACTIONS ON INF
ORMATION THEORY) IT-22, Volume 4, No. 4 (1976)
P. 462-468.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a decoding device capable of handling a code having a shortened code length while maintaining the correction capability.

[0006]

A decoding device according to the present invention includes a code word generated by adding a check symbol to input information and a check section for the coded code word. A decoding device that receives a composite code word obtained by adding the created superposed code by modulo 2 excluding the zero vector part, and reproduces the original input information. An internal reproduction inspection vector is created from the information portion of the received vector, and the internal reproduction inspection vector is modulo 2 added to the received vector inspection portion to which the zero vector portion removed on the transmitting side is added. A U _R regenerator for reproducing the reception vector of the superposition code, a U _R decoder for decoding the superposition code from the reception vector of the reproduced superposition code, a superposition code decoded by this U _R decoder and the received Receiving An adder for reproducing a code word and a vector modulo-2 addition to, those provided with a decoder for decoding the input information from the reproduced codewords.

[0007]

According to the present invention, the U _R regenerator performs the U _R code reproduction processing on the reception vector from which the zero vector part is removed, taking the zero vector part into consideration.

[0008]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a decoding device according to an embodiment of the present invention together with an encoding device, FIG. 2 is a block diagram of the encoding device, and FIG. 3 is an explanatory diagram for explaining an encoding process.

[0009] In Figures 1 and 2, the information input terminal 4, the information output terminal 5, 6 Cr encoder, 7 U _R encoder, the transmission word memory 8, the received word memory 9, the 10 U _R
Reproducer, 11 is a U _R decoder, 12 is a Cr decoder, A ₁ ,
A ₃ is an adder of the method 2, A ₂ is a transmission line, 13 is noise, A _S
Is an encoding device, B _R is a decoding device, 14 is an address / data / control signal bus, and 15 is a control circuit. Further, in FIG. 3, 16 check symbols portion of the superimposed code U _R, 17 is information portion of overlapped symbols as Cr codeword omitted from transmission vector.

Next, the operation will be described. First, the information input from the information input terminal 4 is encoded by the Cr encoder 6 every K bits and converted into an n-bit code word.
When this operation is repeated N times, a code word C ₀ of N × n symbols as shown in FIG. 3B is formed.

Next, the superposition code U _R is encoded.
The U _R encoder 7 regards the K symbols in the check part of the code word C ₀ as information and generates the check symbols of N−K symbols on GF (2 ^nk ) to create N symbol code words. Then, a rectangular arrangement of N × k symbols as shown in FIG. 3C is obtained.

Next, in the adder A ₁ , the check section of the code word C ₀ and each symbol of the code U _R are modulo 2 added bit by bit. Then, the composite code word C _Z shown in FIG. _3D is obtained. This process will be described in more detail below.

On the transmitting side, the Cr encoder 6 creates a C ₀ codeword. The vector representation of the i-th row of the C ₀ codeword is C
If r (i), Cr (i) is represented by the equation (1). Cr (i) = ( I (i), C (i)) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (1)

The symbol Qi of the superposition code U _{R in} the i-th row is 1
When ≦ i ≦ K, it is represented by the equation (2). Qi = C (i) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (2) When K + 1 ≤ i ≤ N, the equation (3) is obtained. Qi = V (i) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ ( 3) However, V (i), the inspection obtained by the encoding algorithm code U _R Is a vector.

Let ξ _{i be} the vector representation of the i-th row of the combined code word C _{Z, which is the combination} of the C ₀ code word and the superposition code U _R. 1
When ≦ i ≦ K ξ _i = ( I (i), 0) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (4) When K + 1 ≤ i ≤ N ξ = ( I ( i), C (i) + V (i)) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (5)

Since the zero vector in equation (4) does not need to be sent as information, the transmission vector C (i) is 1 ≦ i ≦
When K is C (i) = ( I (i)) ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (6) When K + 1 ≤ i ≤ N C (i) = ( I ( i), C (i) + V (i)) ..................... (7).

In this manner, the information part 17 of the Cr code word and the superposition code in which the vector Ci of the i-th row is omitted from the transmission vector of FIG. 3 (d) is obtained, and the rectangular symbol part is an all-zero vector. Understand that And I understand that this part doesn't always have to be sent.

FIG. 4 is a block diagram of the decoding device, and FIG. 5 is an explanatory diagram for explaining the decoding process. In FIG. 4, 9 is a received word memory, 10 is a U _R regenerator, and 11 is a U _R.
Decoder, 12 is a Cr decoder, and 19 is a control circuit.

The reception vectors are arranged as shown in FIG. The reception vector C _{Z, RCV} is expressed by equation (8). _{C Z, RCV = (R 1} , R 2, ‥‥, R N) ‥‥‥‥‥‥‥‥‥‥‥ (8)

Each element R _i has R _i = ( r _i (1), 0) R _i = ( r _i (2), 0) :: R _K = ( r _i (K), 0) R _{K + 1} = ( r _i (K + 1), r _C (K + 1)) :: _RN = ( r _i (N), r _C (N))

That is, it is assumed that there is a zero vector in the upper right part of FIG. In other words, the U _R regenerator 1
At 0, the zero vector is added to the actual received vector. Here, the error vector added on the transmission path is expressed by the equation (9), and E i = ( e _i , e _C ) .................................................................................................. And However, when 1 ≦ i ≦ K, e _C = 0.

Therefore, r _i (j) = I (j) + e _i (j) (1≤j≤K) r _C (j) = 0 (〃) ... (10) r _i (j ) = I (j) + e _i (j) (K + 1 ≦ j ≦ N) r _C (j) = C (j) + V (j) + e _C (j) (〃) ‥‥‥‥‥‥‥‥‥ (11 ) Is.

The U _R regenerator 10 creates an internal reproduction inspection vector C _RCV (j) from the information part of the received vector (FIG. 5).
(B)). C _RCV (j) = C (j) + S (j) ‥‥‥‥‥‥‥‥‥‥‥‥‥ (12)

Here, S (j) is an additional error caused by an error in the information section, and is referred to as a correction syndrome here. When the internal reproduction inspection vector created in this way is modulo 2 added to the inspection unit of the reception vector, the reception vector U _{R, RCV of} the code U _R is reproduced (FIG. 5).
(D)).

UR _{, RCV} (j) = C (j) + S (j) + e _C (j) ... (13) When 0 ≤ j ≤ K, e _C (j) = 0 ... ‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (14). Playback error _{S (j) + e C (} j) the sign U _R correction capability range codewords sent in a long if all corrected sender U _R is U _R regenerator 10 symbols U _R (j) (FIG. 5E).

The Cr decoder 12 modulo 2 adds the codeword U _R correctly decoded by the U _R decoder 11 to the received vector to obtain the received word C _{0, RCV} of the codeword C ₀ (FIG. 6). ..

The element on the j-th row is C _{r, RCV} (j) = ( I (j) + e _i (j), C (j)) ... (15) j when 1 ≦ j ≦ K > when K, a _{C r, RCV (j) =} (I (j) + e i (j), C (j) + e C (j)) ‥‥‥ (16).

This error e _i (j) or e _i (j) + e
_C (j) is corrected by the error correction capability of the code Cr.

As described above, the information section K × (n−k) symbols of the superposition code is always 0 on the transmission side, so that part need not be transmitted from the transmission side. That is, the code length of the composite code is N × k + from the conventional N × n symbols.
It is shortened to (D-1) · (nk) symbols.

FIG. 7 is an explanatory diagram for explaining the difference in reliability between the information portions A and B. Focusing on the difference between the information parts A and B in FIG. 6, the information part A conventionally corrects t errors with an n-bit codeword, but in the method of the present invention, the information of the checker is sent. Since there is no error rate, the error rate is reduced by the vector of the check portion.

That is, since no error occurs in the communication path in the inspection section, it is only necessary to correct the error Si with the superposition code U _R and then to correct the error in the K symbol portion with the Cr code word.

Now, assuming that the code Cr has t-fold error correction capability, the correction failure probability Pf in the original Cr codeword is (1
It is expressed by the equation 7).

[0033]

[Equation 1]

However, the code correction failure probability Pff in the present invention is expressed by the equation (18).

[0035]

[Equation 2]

That is, it is improved by the amount represented by the equation (3).

[0037]

[Equation 3]

Next, the process of actually adding the superposition code and extracting the information on the decoding side will be described in detail.
Now, the pick Hamming code encoding direction 3 shown in FIG. 12 as reference numeral Cr, as a code U _R GF (2 ⁴⁾ on the R
Suppose you choose the S (Reed Solomon) code. Also, the code C
The generator polynomial of r is G (X) = 1 + X + X ⁴ .

FIG. 8 is an explanatory diagram showing that the check symbol Qj of the code U _R is superimposed on the check unit of one code word Cr (j) of the code Cr. In the figure, 20 is Cr (j) Inspection of codeword, 21 U _R codeword check symbols Qj,
Reference numeral 22 is a part of the vector V (j) + C (j) in which both are superimposed. When Qj is a check vector of a Cr code word, it becomes a 0 vector, and since it does not need to be transmitted, this process can be omitted.

FIG. 9 is a block diagram of hardware for executing the process shown in FIG. 8. 23 is an information input terminal, 24 is an information output terminal, A ₁ is a modulo 2 adder, and D _S is G (X) = 1+
Division circuit by X + X ⁴ , S ₁ and S ₂ are switches,
E _X1 and E _X2 are exclusive OR gates, F ₁ , F ₂ , F ₃ and
F ₄ is a shift register including a 1-bit flip-flop.

First, the switch S ₁ is closed, the switch S ₂ is open, and the information I (i) is input from the information input terminal 23.
Division is performed by the division circuit D _S. For example, when K = 11 bits of information is input, the division result of n−k = 4 bits is accumulated in the flip-flops F ₁ , F ₂ , F ₃ , and F ₄ .

Next, the switch S _{1 is} opened and the switch S ₂ is closed, and the input information and C (i) are modulo 2 added by the modulo 2 adder A ₁ . At this time, from the terminal 23, the check vector V of the already calculated code U _R is calculated.
Since (j) is input, V (j) + C (j) is the terminal 2
It is output from 4.

FIG. 10 shows from the received word Rj on the receiving side.
The original code word Cr (j) = (I (j), C (j))
It is explanatory drawing which shows the process which projects. In the figure, 25
Is the reception vector equivalent to V (j) + C (j) on the transmission side
r_CThe part (j), 26 corresponds to I (j) on the transmitting side
r_i(J) part, 27 is the internal reproduction inspection vector C_{RC V}
(J) part, 28 is r_C(J) and C_RCVFrom (j)
Played U_RElement Q of the jth line of the received word_RCV(J),
29 is the code U_RElement Q decoded by error correction
(J), 30 is the decoded U_RReceive j element Q (j) of
Detection of the Cr received word reproduced by adding the vector and modulus 2.
Check vector C_RCV(J).

FIG. 11 is a configuration diagram showing a configuration for performing the process until the vector _QRCV (j) is _extracted . In the figure, 31 is an information input terminal, 32 is an information output terminal,
33 is a counter, 34 is a 4-bit latch register, 3
5 is an adder for bit 2 modulo 2 addition, 36 is a serial / parallel converter, 37 is a parallel / serial converter, Dr is a division circuit by G (X) = 1 + X + X ⁴ , F
₁ , F ₂ , F ₃ and F ₄ are 1-bit flip-flops,
Q ₁ , Q ₂ , Q ₃ , and Q ₄ are the contents of the shift register,
_{EX 1} and EX ₂ are exclusive OR gates, S ₃ is a switch, P
₁ and P ₂ are terminals of the switch.

The received word R _i serially input from the information input terminal 31 is divided by the divider Dr. The counter 33 counts up to the information bit number K = 11. Then, the division result of the 11th bit becomes C _RCV (j), and Q
₁ , Q ₂ , Q ₃ , and Q ₄ are latched in the latch register 34.

The reception vector check unit r _C (j) is serial / parallel converted by the serial / parallel converter 36 and becomes 4-bit parallel data. Then, Q _RCV (j), which is the result of modulo 2 addition of the data and the latched data C _RCV (j), is input to the parallel / serial converter 37. Therefore, _QRCV (j) is output as serial data from the output terminal 32 through the terminal P ₂ and the switch S ₃ .

[0047]

As described above, according to the present invention, the inspection part of the original code is regarded as a part of the information, superposed codes are formed, and they are modulo 2 added so that a part of the inspection part is all-in-one. Receive the one that has become the zero vector with the zero vector removed, and perform decoding considering the zero vector.
Since the decoding device is configured, the code length can be shortened without deteriorating the error correction capability, and there is an effect that the transmission efficiency is improved and the reliability is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a decoding device and an encoding device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of an encoding device.

FIG. 3 is an explanatory diagram illustrating an encoding process.

FIG. 4 is a configuration diagram showing a configuration of a decoding device.

FIG. 5 is an explanatory diagram for explaining a decoding process.

FIG. 6 is an explanatory diagram showing received words.

7 is an explanatory diagram for explaining the reliability of the code handled by the encoding device and the decoding device shown in FIG. 1. FIG.

FIG. 8 is an explanatory diagram showing how check symbols of a code U _R are added to a check unit of a code word Cr (j).

9 is a block diagram showing a detailed configuration example of a portion of the encoding device which performs the processing shown in FIG. 8.

FIG. 10 is an explanatory diagram showing how a code word Cr (j) is extracted from a received word R (j).

11 is a block diagram showing a detailed configuration example of a portion of the decoding device which performs the processing shown in FIG.

FIG. 12 is an explanatory diagram showing an example of a conventional codeword.

[Explanation of symbols]

10 U _R regenerator 11 U _R decoder 12 Cr decoder (decoder) A ₃ adder

Claims (1)

[Claims] 1. A method 2 in which a codeword generated by adding a check symbol to input information is encoded, and a superposition code generated from a check unit of the coded item is modulo 2
In the decoding device that receives the synthesized codeword obtained by addition except the zero vector part and reproduces the original input information, the internal reproduction check vector is calculated from the information part of the received reception vector. The internal reproduction inspection vector is modulo 2 to the inspection vector of the received vector added with the zero vector portion removed on the transmission side.
A U _R regenerator that adds and reproduces the received vector of the superposed code, a U _R decoder that decodes the superposed code from the regenerated received vector of the superposed code, and a superposed code decoded by this U _R decoder. A decoding device comprising: an adder that modulo-2 adds the received received vector to reproduce a codeword; and a decoder that decodes the input information from the reproduced codeword.