JPH07114370B2 - Encoder - Google Patents

Description

The present invention relates to an error correction code encoding and decoding device.

[Conventional technology]

FIG. 11 shows a codeword format using a code of a conventional device of this kind. In the figure, 1 indicates an information symbol portion, 2 indicates a check symbol portion, and 3 indicates a coding direction of C _r .

As shown in the figure, the error added on the information transmission path is corrected by the code C _r on the decoding side of the transmission signal. That is,
Along the coding direction 3 of the code C _r, the information symbol portion 1 and the check symbol portion 2 are divided and checked, and as a result,
Only when there is an error, the method of correcting and then decoding is adopted.

[Problems to be solved by the invention]

Since the conventional encoding / decoding device is configured as described above, there is a problem that the redundancy is large with respect to a predetermined correction capability and the reliability is lowered.

The present invention has been made to solve the above problems, and regards a check symbol portion which is redundant with respect to a correction capability in decoding as a part of information in a superposition code and combines the information symbol and the check symbol. Encoding into a superposition code, modulo 2 addition to the code word ₀ of the original code C _r , and canceling a part of the check symbol from the transmission vector to shorten the overall code length while maintaining the correction capability. And to obtain a decoding device.

[Means for solving problems]

The encoding / decoding device according to the present invention has a C _r of n symbols.
Coder and the N superimposed encodes the K of the test symbol as superimposed code U _R information symbols, a portion of the test vectors of the original sum alms source code modulo 2 to the code word C ₀ It does not need to be sent.

[Action]

In the present invention, the information vector of the superposition code and the original
Since the check vector of the C _r code is completely the same, the result of addition by the modulo 2 is always all zero, and the information can be omitted from the transmission vector by that much, so the overall code length can be reduced without reducing the capability. It is a thing.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First, FIG. 1 is a block connection diagram showing a control circuit of an embodiment of the present invention, FIG. 2 is a hardware configuration diagram of an encoding device of the present invention, and FIG. 3 is a description of an encoding process of the present invention. It is a model figure.

Next, in FIGS. 1 and 2, 4 is an information input terminal, 5
Is an information output terminal, 6 is an information _Cr encoder, 7 is a U _R encoder, 8
Is a transmission word memory, 9 is a reception word memory, 10 is a U _R regenerator, 11 is a U _R decoder, 12 is a C _r decoder, A ₁ and A ₃ are modulo 2 adders, A ₂ is a communication channel, 13 is noise, A _S is an encoder, B _R is a decoder, 14 is an address / data / control signal bus, and 15 is a control circuit. Also, in FIG. 3, 16
Is the check symbol part of the superposition code U _R , and 17 is the information part of the C _r codeword and the superposition code omitted from the transmission vector.

Next, the operation of the present invention will be described. First, the information input from the information input terminal 4 in FIG.
It is encoded by the C _r encoder 6 and converted into an n-bit code word. When this operation is repeated N times, a code word C ₀ of N × n symbols as shown in FIG. 3B is formed. Next, the superposition code U _R is encoded, but the U _R encoder 7 considers the K symbols as information from the inspection unit of the code word C ₀ and generates the inspection symbols of N−K symbols on GF (2 ^nk ). , N symbol codewords are created. Thus, as shown in FIG. 3 (c),
A code U _{R of} N × (n−k) symbols is generated.

Then made in modulo 2 adder shown in FIG. 1 A ₁ code word C ₀
And the symbols of the code U _R are modulo 2 added in bit correspondence.

Then, the composite code word C _z shown in FIG. 3 (d) is obtained.
This process will be described in more detail below.

That is, on the transmitting side, a C ₀ code word is produced by the C _r encoder 7, and the vector expression of the i-th row is C _r (i), then the equation (1) is obtained.

C _r (i) = ( I (i), C (i)) (1) When the symbol Qi of the superposition code U _R of the i-th row is 1 ≦ i ≦ K,
It is expressed by equation (2). Q i = C (i) (2) When K + 1 ≦ i ≦ N, the formula (3) is obtained.

Qi = V (i) (3) where V (i) is a check vector calculated by the coding algorithm of the code U _R. Let ξ be the vector representation of the i-th row of the composite code word C _z .

When 1 ≦ i ≦ K ξ = ( I (i), 0) (4) When K + 1 ≦ i ≦ N ξ = ( I (i), C (i) + V (i)) …… (5) Since it is not necessary to send the zero vector as information in the above equation (4), the transmission vector C (i) is C (i) = ( I (i)) when 1 ≦ i ≦ K. ) When K + 1 ≦ i ≦ N C (i) = ( I (i), C (i) + V (i)) ………
(7)

In this way, the information part of the C _r codeword and the superposition code in which the vector C _i of the i-th row is omitted from the transmission vector of FIG. 3 (d)
17 is obtained, and it can be understood that the rectangular symbol portion becomes an all-zero vector. And I can understand that this part does not always need to be sent.

Next, FIG. 4 is a block diagram showing the decoding side hardware, and FIG. 5 is a model diagram for explaining the decoding process. Fourth
In the figure, 9 is a received word memory, 10 is a U _R regenerator, and 11 is a U _R.
Decoder, 12 is a _Cr decoder, and 19 is a control circuit.

Further, the reception vector is arranged as shown in FIG. The reception vector _z is expressed by equation (8). _{z = (R 1, R 2} , ..., R N) ......... (8) Each element R _i is R = (r (1), 0) R = (r (2), 0) · · · R K = ( R (K), 0) R _{K + 1} = ( r (K + 1), r _c (K + 1)) _··· R _N = ( r (N), r _c (N)) That is, FIG. It is assumed that there is a zero vector in the upper right part of).

Here, the error vector added on the transmission path is represented by the equation (9), and E _i = ( e , e _c ) ... (9).

However, when 1 ≦ i ≦ K, e _c = 0.

Next, from the information part of the received vector
Create (j) (Fig. 5 (b)).  (J) =C(J) + S (j) ... (12) where S (j) is caused by an error in the information section.
This is an additional error and is referred to as a correction syndrome here.
Receive the internal reproduction vector created in this way.
Add mod 2 to the check part of the tor. Code U_RReceiving vector
Le_RIs reproduced (FIG. 5 (d))._R (J) =C(J) +S(J) +e _c(J) ………
(13) e for 0 ≦ j ≦ K_c(J) = 0 ... (14). Code U_RError of (j) S (j) + e_c(J) is a sign
U_RWithin the range of correction capability of
Codeword U_RIs U_RReproduced by the regenerator 10 (Fig. 5
(E)).

When U is in correctly decoded _R decoder 11 the codeword U _R into the receive vector modulo 2 adds, received word C ₀ of the code word C ₀ is obtained (FIG. 5 (f)).

The element in the j-th row is 1 ≦ j ≦ K, and _r (j) = ( I (j) + e (j), C (j)).
... (15) when _{j> K, r (j)} = (I (j) + e (j), C (j) + e c (j)) ...
(16) This error e (j) or e (j) + e _c (j) is a code
Corrected with the error correction capability of C _r .

Since the information section K × (nk) symbols of the superposition code is always 0 on the transmitting side, there is no need to send it on the transmitting side. That is, the code length of the composite code is N × n from the conventional N × n symbols.
It is shortened to k + (D−1) · (n−k) symbols.

FIG. 6 is a diagram for explaining the difference in reliability of the information parts A and B of the present invention. That is, paying attention to the difference between the sixth information parts A and B, the information part A has conventionally corrected t errors with n bit codewords, but since this method does not send the information of the check part. The error rate is reduced by the vector of the check portion. That is, since there is no error in the communication path, the checking unit may correct the error S _i with the superposition code U _R and then correct the error in the K symbol portion of the C _r codeword. Now, assuming that the code C _r has t-fold error correction capability, the correction failure probability P f in the original C _r code word is expressed by (17).

However, the correction failure probability Pff of the code of the present invention is (18).

Next to It will be doubled.

Next, the hardware for actually adding the superposition code and for extracting the original information on the decoding side will be described below.

Now, _suppose that the code C _r is selected as the Hamming code of (control circuit 15, U _R is the decoder 11, coding direction 3 of the code C _r ), and the code U _R GF
(2 ⁴ ) Select the RS (Reed-Solomon) code above. The generator polynomial of the code C _r is G (X) = 1 + X + X ⁴ .

7 is an explanatory diagram for superposing a check symbols Qj code U _R to the inspection portion one codeword C _r (j) of the code C _r. 20 in the figure is C
_r (j) Inspection of codeword, 21 U _R codeword check symbols Qj, 22 are both superimposed vector V (j) + C (j )
Part of. When Qj is the check vector of the C _r codeword, it is a 0 vector, and this process can be omitted because it does not need to be transmitted.

FIG. 8 is a block diagram of the hardware for executing the process of FIG. 7. 23 is an information input terminal, 24 is an information output terminal, A ₁ is an adder of modulus 2, D _S is G (X) = 1 + X + X ⁴ , S ₁ and S ₂ are switches, E _x1 and E _x2 are exclusive OR gates,
F ₁ , F ₂ , F ₃ , and F ₄ are shift registers by flip-flops of 1 bit. Initially switch S ₁ is closed, switch S ₂
When opened, the information I (i) is input from the information input terminal 23, and the division circuit D _S executes division. Then, K = 11 bits of information are inputted n-k = 4 bits of the division result is stored in the flip-flop _{F 1, F 2, F 3} , F 4. Then, the switch S _{1 is} opened and the switch S ₂ is closed, and the modulo 2 addition is executed by the input information and the modulo 2 adder A ₁ . At this time, the already-calculated check vector V (j) of the code U _R is input from the terminal 23, the modulo 2 addition is executed, and V (j) + C (j) is output from the terminal 24.

Figure 9 shows the original received word C from the received word Rj on the receiving side.
FIG. 25 is a diagram showing a process of extracting _r (j) = (I (J), C (j)), where 25 is a portion of the reception vector r _c (j) equivalent to V (j) + C (j) on the transmission side, 26 is a part of r (j) corresponding to I (j) on the transmitting side, 27 is a part of internal reproduction check vector (j), 28 is U _R reproduced from r _c (j) and (j)
The element (j) on the j-th row of the received word, 29 is the element Q (j) decoded by error correction with the code U _R , and 30 is j of the decoded U _R.
It is the check vector (j) of the C _r received word reproduced by adding the received vector method 2 to the element Q (j).

Further, FIG. 10 is a diagram for explaining the operation of the hardware until the vector (j) of 28 is taken out in FIG. 9, 31 is an information input terminal, 32 is an information output terminal, 33 is a counter, and 34 is 4
Bit latch register, 35 adder for bit 2 modulo 2 addition, 36 serial / parallel converter, 37 parallel / serial converter, D _r G (X) = 1 + X + X ⁴ division circuit, F ₁ , F ₂ , F ₃ , F ₄ are 1-bit flip-flops, Q ₁ , Q ₂ , Q ₃ , Q ₄ are shift register contents, E _x1 , E _x2
Is an exclusive OR gate, S ₃ is a switch P ₁ , P ₂ is a switch terminal. First, the received word R serially input from the 31 information input terminals is divided by the divider D _r . The counter 33 counts up to the information bit number K = 11, and the division result of the 11th bit is (j), so that Q ₁ , Q ₂ , Q ₃ , and Q ₃ are latched in the latch register 34.

The received vector check unit r _c (j) is serial / parallel converted into 4-bit parallel data, and the latched data (j) and the modulo 2 added (j) are parallel / parallel.
The data is input to the serial converter 37, passes through the terminal P ₂ switch S ₃ as serial data, and is output from the output terminal 32.

〔The invention's effect〕

As described above, according to the present invention, the check section of the original code is regarded as a part of the information, the superposed code is formed, and the modulo 2 is added. Since it becomes an all-zero vector and can be removed from the transmission vector, there is an effect that the code length can be shortened without lowering the capability and the reliability of the transmission information is greatly improved. It is also possible to obtain the effect that the reliability of the information part corresponding to the zero vector can be further improved.

[Brief description of drawings]

FIG. 1 is a block connection diagram of an embodiment of the present invention, FIG. 2 is a hardware configuration diagram of an encoding device of the present invention, FIG. 3 is a model diagram showing an encoding process of the present invention, and FIG. FIG. 5 is a block diagram showing the decoding side hardware of FIG. 5, FIG. 5 is a model diagram showing the decoding process of the present invention, FIG. 6 is a reliability explanatory diagram of the information parts A and B of the present invention, and FIG. The check symbol of the code U _{R in} the check part of one code word C _r (j)
FIG. 8 is an explanatory diagram of modulo 2 addition of Qj, FIG. 8 is a circuit diagram showing an example of hardware for executing the process of FIG. 7, and FIG. 9 is a diagram showing the original received word _r (j) from the received word Rj on the receiving side. FIG. 10 is a model diagram showing a process of separating and taking out, FIG. 10 is a hardware circuit configuration diagram for executing the process of FIG. 9, and FIG. 11 is an explanatory diagram of a conventional encoding format. In the figure, 6 is a C _r encoder, 7 is a U _R encoder, 8 is a transmission word memory, A _S is a coding device, A ₁ and A ₃ are modulo 2 adders, 9 is a reception memory, and 10 is U. _r decoder, 11 is a U _R decoder, and 12 is a C _r decoder. The same parts or corresponding parts are designated by the same reference numerals.

Claims (1)

[Claims] 1. Input information of N × k digits consisting of N rows having k symbols in the row direction is encoded for each row to add a (n−k) symbol inspection section to N × n. A Cr encoder that generates a code word C0 of a symbol, and a K number of symbols in each column of the N × (n−k) symbol check unit in the code word C0 are regarded as information symbols, and encoded in each column. To generate (N−K) check symbols, and N × (n−k)
An encoding device including a U _R encoder that generates a U _R code of a symbol and an adder that modulo 2 adds the U _R code and a check unit of the code word C0.