JPS61170104A - Intermediate frequency amplifier circuit - Google Patents

Intermediate frequency amplifier circuit

Info

Publication number
JPS61170104A
JPS61170104A JP1057185A JP1057185A JPS61170104A JP S61170104 A JPS61170104 A JP S61170104A JP 1057185 A JP1057185 A JP 1057185A JP 1057185 A JP1057185 A JP 1057185A JP S61170104 A JPS61170104 A JP S61170104A
Authority
JP
Japan
Prior art keywords
agc
stage
amplifier
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1057185A
Other languages
Japanese (ja)
Inventor
Katsuharu Kimura
克治 木村
Yoshiharu Tamura
田村 儀晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1057185A priority Critical patent/JPS61170104A/en
Publication of JPS61170104A publication Critical patent/JPS61170104A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a circuit having an electric field detecting function with excellent linearity of an electric field detection voltage and temperature characteristic by constituting the circuit with an AGC circuit comprising multi-stage AGC amplifiers and using an AGC control voltage when the output voltage of the final stage is constant so as to detect the input electric field level of an intermediate frequency amplifier circuit. CONSTITUTION:n-Stages of AGC amplifies are provided, an output of each stage is connected to an input of the next stage, and an AGC control voltage is impressed from an AGC control voltage generator 2 to all the AGC amplifiers of the n-stage in common so that the output of the AGC amplifier of the n-th stage. Then the said AGC control voltage has a pseudo logarithmic characteristic to the input voltage of the 1st AGC amplifier. The output voltage Vo is controlled by the AGC control circuit 2 so that output voltage Vo is constant after it is rectified by a capacitor Crec with a load RL connected to the n-th stage of the output section. Thus, the pseudo logarithmic characteristic with excellent linearity is obtained over a wide range. Thus, the input electric field level to the intermediate frequency amplifier is detected by the AGC control voltage and the pseudo logarithmic characteristic with excellent linearity is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、受信機の中間周波増幅器の構成に関し、特に
、移動無線或いはテレメータ等に使用するのに適した受
信機の受信電界検出の方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the configuration of an intermediate frequency amplifier of a receiver, and in particular to a method of detecting a received electric field of a receiver suitable for use in mobile radio, telemeters, etc. It is.

従来の技術 本発明の先行技術としては、例えば゛、Micro −
electronics and Re1iabili
ty、  vol、  16 、  PP、 45〜3
66、 Pergamon Press、 1977 
 が存在する。本発明の従来例として開示されている第
3図の回路構成は上記文献に示されているOA 308
9なるIC中の一部を抽出したものである。その他上記
文献中における本明細書の第3図と関係する部分はF”
igl。
Prior art Prior art to the present invention includes, for example, ゛, Micro-
electronics and
ty, vol, 16, PP, 45-3
66, Pergamon Press, 1977
exists. The circuit configuration of FIG. 3, which is disclosed as a conventional example of the present invention, is the OA 308 shown in the above-mentioned document.
This is an extracted part of IC No. 9. Other parts in the above document that are related to FIG. 3 of this specification are F”
igl.

Fig 2 、 Fig 10 、 Fig 11 、
 Fig 12及びその説明文である。
Fig2, Fig10, Fig11,
Fig. 12 and its explanatory text.

従来、この種の電界検出機能を有する中間周波増幅器の
構成は、第3図に示すように、多段の増幅器(トランジ
スタQl/〜Q10′から成る第1段;トランジスタQ
11′〜Q19′から成る第2段喜トランジスタQ20
′〜Q27′から成る第3段)の各段の出力をコンデン
サ(G8’ 、 09’ 、 (310’ )を介して
整流し、夫々の段の整流電圧を加算して、電界レベル情
報を出していた。
Conventionally, the configuration of an intermediate frequency amplifier having this type of electric field detection function is as shown in FIG.
2nd stage transistor Q20 consisting of 11' to Q19'
The output of each stage (3rd stage consisting of '~Q27') is rectified via capacitors (G8', 09', (310'), and the rectified voltages of each stage are added to output electric field level information. was.

発明が解決しようとする問題点 しかしながら、各段の整流電圧を加算した部分の線形性
が悪くなり、第4図に示すように、電界検出電圧に凸凹
が出ることが、しばしば見られる。
Problems to be Solved by the Invention However, it is often seen that the linearity of the sum of the rectified voltages of each stage deteriorates, and as shown in FIG. 4, unevenness appears in the electric field detection voltage.

また、信号の電流はダイオード(Q28’ 、 Q29
’ 。
Also, the signal current flows through diodes (Q28', Q29
'.

Q30’ IQ32 、 Q33 、 Q34 + Q
35’、 Q36’、 Q37’)を使って行っている
ので、特に温度特性が悪くなり、温度特性を補償するに
は回路が複雑になるという欠点がある。
Q30' IQ32, Q33, Q34 + Q
35', Q36', Q37'), the disadvantage is that the temperature characteristics are particularly poor and the circuit becomes complex to compensate for the temperature characteristics.

寸だ、整流器には各々にコンデンサ(08’、 09’
In fact, each rectifier has a capacitor (08', 09'
.

C1o’)が必要となり、従って、中間周波数を下げる
と大きなコンデンサが必要となってIC化されているの
は中間周波数が10.7MHzであるのが一般的である
。この場合、中間周波数を下げると、コンテンプの内蔵
は難しくなり、各段毎に整流器用の外付コンデンサ用の
端子が必要になる結果、 IC化には不利であった。更
に壕だ、中間周波数を高くすれば、当然各段の増幅器に
電流を流さないと増幅度が取れないために、低消費電流
化は困難であった。
Therefore, if the intermediate frequency is lowered, a large capacitor is required, and the intermediate frequency of the IC is generally 10.7 MHz. In this case, if the intermediate frequency was lowered, it would be difficult to incorporate the compensator, and a terminal for the external capacitor for the rectifier would be required for each stage, which was disadvantageous for IC implementation. Furthermore, if the intermediate frequency is raised, it is difficult to achieve amplification unless current is passed through each stage of amplifier, making it difficult to reduce current consumption.

本発明は従来の技術に内在する上記欠点を改善する為に
なされたものであり、従って本発明の目的は、電界検出
電圧の直線性および温度特性に優れ、さらに、低電流で
動作し、外付は部品の少ない電界検出機能を有する新規
な中間周波増幅回路を提供することにある。
The present invention has been made in order to improve the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to have excellent linearity and temperature characteristics of electric field detection voltage, operate with low current, and The object of the present invention is to provide a novel intermediate frequency amplification circuit having an electric field detection function with fewer parts.

問題点を解決する為の手段 上記目的を達成する為に、本発明に係る中間周波増幅回
路は、第1の一対のトランジスタの夫々のエミッタがそ
れぞれ抵抗を介して共通に接続された第1の差動増幅器
と、上記第1の一対のトランジスタの一方のトランジス
タのコレクタに第2の一対のトランジスタの夫々のエミ
ッタがそれぞれ抵抗を介して共通に接続された第2の差
動増幅器と、上記第1の一対のトランジスタの他方のト
ランジスタのコレクタに第3の一対のトランジスタの夫
々のエミッタがそれぞれ抵抗を介して共通、  に接続
された第3の差動増幅器と、上記第2及び第3の差動増
幅器の出力が互いに逆になる様に上記第2及び第3の一
対のトランジスタのコレクタに夫々接続された抵抗とか
ら成るAGC増幅器をn段持ち、第1段目のAGC増幅
器の出力が第2段目のAGC増幅器の入力に接続され、
順次第(n−1)段目のAGC増幅器の出力が第n段目
のACTO増幅器の入力に接続され、第n段目のAGC
増幅器の出力が一定となる様に第1段目のAG(j増幅
器から第n段目のAGC増幅器捷でのn段のAGC増幅
器全てに共通のACTO制御電圧が印加される様に構成
されたAGC回路において、上記第1段目のA(′TC
増幅器の入力電圧に対して、上記AGC回路のAGC制
御電圧が擬似対数特性を有することを特徴とする。
Means for Solving the Problems In order to achieve the above object, the intermediate frequency amplification circuit according to the present invention includes a first pair of transistors in which the respective emitters of the first pair of transistors are connected in common through respective resistors. a differential amplifier; a second differential amplifier in which the emitters of each of the second pair of transistors are commonly connected to the collector of one of the first pair of transistors via a resistor; a third differential amplifier in which the respective emitters of the third pair of transistors are commonly connected to the collectors of the other transistors of the first pair of transistors through respective resistors; It has n stages of AGC amplifiers each consisting of a resistor connected to the collectors of the second and third pair of transistors so that the outputs of the dynamic amplifiers are opposite to each other, and the output of the first stage AGC amplifier is Connected to the input of the second stage AGC amplifier,
Sequentially, the output of the (n-1) stage AGC amplifier is connected to the input of the n-th stage ACTO amplifier, and the n-th stage AGC amplifier is connected to the input of the n-th stage ACTO amplifier.
In order to keep the output of the amplifier constant, a common ACTO control voltage was applied to all n-stage AGC amplifiers from the first stage AG (j amplifier to the n-th stage AGC amplifier switch). In the AGC circuit, the first stage A('TC
The AGC control voltage of the AGC circuit has a pseudo-logarithmic characteristic with respect to the input voltage of the amplifier.

発明の原理 本発明の原理は、中間周波増幅回路を多段のAGC増幅
器から成るAGC回路で構成し、AGC回路の最終段の
出力電圧が一定となるときのAGC制御電圧により、中
間周波増幅回路の入力電界レベルを検出するものである
Principle of the Invention The principle of the present invention is that the intermediate frequency amplifier circuit is configured with an AGC circuit consisting of multi-stage AGC amplifiers, and that the intermediate frequency amplifier circuit is controlled by the AGC control voltage when the output voltage of the final stage of the AGC circuit is constant. It detects the input electric field level.

発明の実施例 次に本発明をその好筐しい一実施例について第1図、第
2図を参照しながら具体的に説明する。
Embodiment of the Invention Next, a preferred embodiment of the present invention will be specifically explained with reference to FIGS. 1 and 2.

第1図は本発明の一実施例を示す回路構成図である。本
実施例においては、n段のAGC増幅器から構成される
AGC回路を考える。
FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. In this embodiment, an AGC circuit composed of n-stage AGC amplifiers will be considered.

第n段の出力部に接続される負荷をRLとみなすと、出
力電圧Voは整流用コンデンサ(3recにより整流さ
れた後に出力電圧■0が一定となる様にAGC制御回路
2によって制御される。本発明によるAGC回路は十分
な直線性が得られる。以下にこのことを数式を用いて説
明する。
If the load connected to the output section of the n-th stage is regarded as RL, the output voltage Vo is controlled by the AGC control circuit 2 so that the output voltage 0 becomes constant after being rectified by the rectifying capacitor (3rec). The AGC circuit according to the present invention can obtain sufficient linearity.This will be explained below using mathematical expressions.

このAGC回路の利得gは次式で表わせる。The gain g of this AGC circuit can be expressed by the following equation.

■0 ” = V1丁 ・・・・・・・  ・・・ (1) ・ ・ ・・・・・ (2) ここで ・−・−・・ ・・・・・・ (3) とおくと と表わせる。■0 ” = V1 block ...... (1) ・ ・・・・・・・(2) here ・−・−・・・・・・・・(3) And then It can be expressed as

とおくと となる。g′は(4)式かられかる通り、利得gをtL (工、+RC) (Rc I 1)n  で正規化した
利得である。
It becomes. As can be seen from equation (4), g' is the gain obtained by normalizing the gain g by tL (E, +RC) (Rc I 1)n.

g’(aB表示)のに依存性をl、nをパラメータにし
て示すと第2図となる。ここで(5)式よりAGC制御
電圧VAG aはkに比例するから、第2図は利得g′
のAGC制御電圧VAGC依存性を示すと解釈できる。
Figure 2 shows the dependence of g' (indicated by aB) using l and n as parameters. Here, from equation (5), the AGC control voltage VAG a is proportional to k, so the gain g′ in FIG.
This can be interpreted as indicating the AGC control voltage VAGC dependence of .

第2図かられかる様に、REIll =O(l−0)に
比して例えば、ノー2あるいはl−3とすると、広い範
囲で直線性の良い擬似対数特性が得られる。
As can be seen from FIG. 2, compared to REIll =O(l-0), if, for example, No 2 or l-3 is set, a pseudo-logarithmic characteristic with good linearity can be obtained over a wide range.

又、段数nに比例して利得〆の擬似対数特性領域が拡大
される。
Further, the pseudo-logarithmic characteristic region of the gain limit is expanded in proportion to the number of stages n.

発明の詳細 な説明した様に、本発明は中間周波増幅回路を多段のA
GC増幅器からなるAGC回路で構成し、AGC回路の
最終段の出力電圧が一定となるときのAGC制御電圧に
より、中間周波増幅回路の入力電界レベルを検出するも
のであり、整流器も1つで済む。従って、整流器用のコ
ンデンサも1個で済み、中間周波数を下げた時にコンデ
ンサが内蔵出来なくても、外付コンデンサ用の端子を1
本追加するのみで対処出来る。また、中間周波数を下げ
た場合には中間周波増幅器の各段に流す電流値も少なく
ても必要な利得が得られ、低消費電流化が可能となる。
As described in detail, the present invention provides an intermediate frequency amplification circuit with a multi-stage A
It consists of an AGC circuit consisting of a GC amplifier, and the input electric field level of the intermediate frequency amplifier circuit is detected using the AGC control voltage when the output voltage of the final stage of the AGC circuit is constant, and only one rectifier is required. . Therefore, only one capacitor is required for the rectifier, and even if a capacitor cannot be built in when lowering the intermediate frequency, the terminal for an external capacitor can be connected to one terminal.
This can be solved by simply adding this book. Further, when the intermediate frequency is lowered, the necessary gain can be obtained even if the current value flowing through each stage of the intermediate frequency amplifier is small, and current consumption can be reduced.

また、電界検出電圧は整流電圧の加算等を行っていない
ので、入力電界レベルに対して擬似対数圧縮されて、は
ぼ直線的な変化となシ、単調関数となる。まだ、大入力
電界に対する飽和レベルも向上するので検出電界のダイ
ナミックレンジも十分に取れる。
Further, since the electric field detection voltage is not subjected to addition of rectified voltage, etc., it is pseudo-logarithmically compressed with respect to the input electric field level, and does not change almost linearly, but becomes a monotone function. However, since the saturation level for a large input electric field is improved, a sufficient dynamic range of the detected electric field can be obtained.

更にまた、電界検出電圧の温度特性も単調な1次直線と
なるので、温度補償も容易に行なえる。
Furthermore, since the temperature characteristic of the electric field detection voltage also becomes a monotonous linear straight line, temperature compensation can be easily performed.

以上をまとめると、本発明によれば、中間周波増幅回路
への入力電界レベルをAGC制御電圧により検出出来、
しかも直線性の良い擬似対数特性の関係で得られ、広い
ダイナミックレンジの入力電界レベルを検出出来、温度
特性に優れ、低消費電流で動作する外付は部品の少ない
中間周波増幅回路が得られる。
To summarize the above, according to the present invention, the input electric field level to the intermediate frequency amplifier circuit can be detected by the AGC control voltage,
Furthermore, it is possible to obtain an intermediate frequency amplification circuit with few external components, which is obtained due to the relationship of pseudo-logarithmic characteristics with good linearity, can detect input electric field levels in a wide dynamic range, has excellent temperature characteristics, operates with low current consumption, and has few external components.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を部分的にブロック図で示し
た回路図である。 ■IN・・・入力電圧、Vo・・・出力電圧、 VAG
C・AGC制御電圧、VCC−・電源電圧、Q ]−1
、・Q 16 、  ・Qnl +・・・′暢6・・・
トランジスタ、Rc、 REI 、 RE2・・・抵抗
、RI、・・・等価負荷抵抗、工1・・・定電流源、0
rec・・・整流用コンデンサ、1・・・整流器、2・
・・AGC制御電圧発生器第2 CHd第1 図に於ケ
ルVAGa、!:g = Vo/VIN  トの関係を なるに、lをパラメータにして示した図である。 第3図は従来の回路例を示す図である。 Ql/ 〜Q50′・・トランジスタ、D1′・・ダイ
オード、R1’〜R43′・・抵抗、C31’〜C11
′・・・コンデンサ、Vcc・・・電源電圧、S −M
ETEROUT・・パ電界検出出力端子 第4図は第3図に於けるS −METEROUTの出力
電圧を工FINのレベルV工Nについて示したものであ
る。
FIG. 1 is a circuit diagram showing a partial block diagram of an embodiment of the present invention. ■IN...Input voltage, Vo...Output voltage, VAG
C・AGC control voltage, VCC-・Power supply voltage, Q ]-1
, ・Q 16 , ・Qnl +・・・' 6...
Transistor, Rc, REI, RE2...Resistance, RI,...Equivalent load resistance, Engineering 1...Constant current source, 0
rec... rectifying capacitor, 1... rectifier, 2...
...AGC control voltage generator 2nd CHd 1st figure shows VAGa,! :g=Vo/VIN This is a diagram showing the relationship between g and VIN using l as a parameter. FIG. 3 is a diagram showing an example of a conventional circuit. Ql/~Q50'...Transistor, D1'...Diode, R1'~R43'...Resistor, C31'~C11
'... Capacitor, Vcc... Power supply voltage, S -M
ETEROUT...P electric field detection output terminal FIG. 4 shows the output voltage of S-METEROUT in FIG. 3 with respect to the level V of FIN.

Claims (1)

【特許請求の範囲】[Claims] 第1の一対のトランジスタの夫々のエミッタがそれぞれ
抵抗を介して共通に接続された第1の差動増幅器と、上
記第1の一対のトランジスタの一方のトランジスタのコ
レクタに第2の一対のトランジスタの夫々のエミッタが
それぞれ抵抗を介して共通に接続された第2の差動増幅
器と、上記第1の一対のトランジスタの他方のトランジ
スタのコレクタに第3の一対のトランジスタの夫々のエ
ミッタがそれぞれ抵抗を介して共通に接続された第3の
差動増幅器と、上記第2及び第3の差動増幅器の出力が
互いに逆になる様に上記第2及び第3の一対のトランジ
スタのコレクタに夫々接続された抵抗とからなるAGC
増幅器をn段持ち、第1段目のAGC増幅器の出力が第
2段目のAGC増幅器の入力に接続され、順次第(n−
1)段目のAGC増幅器の出力が第n段目のAGC増幅
器の入力に接続され、第n段目のAGC増幅器の出力が
一定となる様に第1段目のAGC増幅器から第n段目の
AGC増幅器までのn段のAGC増幅器全てに共通のA
GC制御電圧が印加される様に構成されたAGC回路に
おいて、上記第1段目のAGC増幅器の入力電圧に対し
て、上記AGC回路のAGC制御電圧が擬似対数特性を
有することを特徴とする中間周波増幅回路。
a first differential amplifier in which the emitters of each of the first pair of transistors are connected in common via a resistor; a second differential amplifier whose respective emitters are commonly connected via a resistor; and a third pair of transistors whose emitters each have a resistor connected to the collector of the other transistor of the first pair of transistors. a third differential amplifier commonly connected through the transistor, and a third differential amplifier connected to the collectors of the second and third pair of transistors, respectively, such that the outputs of the second and third differential amplifiers are opposite to each other. AGC consisting of a resistor
It has n stages of amplifiers, and the output of the first stage AGC amplifier is connected to the input of the second stage AGC amplifier.
1) The output of the AGC amplifier at the first stage is connected to the input of the AGC amplifier at the nth stage, and the output from the AGC amplifier at the first stage to the AGC amplifier at the nth stage is connected so that the output of the AGC amplifier at the nth stage is constant. A common to all n-stage AGC amplifiers up to
In the AGC circuit configured to apply a GC control voltage, the AGC control voltage of the AGC circuit has a pseudo-logarithmic characteristic with respect to the input voltage of the first stage AGC amplifier. Frequency amplification circuit.
JP1057185A 1985-01-23 1985-01-23 Intermediate frequency amplifier circuit Pending JPS61170104A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1057185A JPS61170104A (en) 1985-01-23 1985-01-23 Intermediate frequency amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1057185A JPS61170104A (en) 1985-01-23 1985-01-23 Intermediate frequency amplifier circuit

Publications (1)

Publication Number Publication Date
JPS61170104A true JPS61170104A (en) 1986-07-31

Family

ID=11753921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1057185A Pending JPS61170104A (en) 1985-01-23 1985-01-23 Intermediate frequency amplifier circuit

Country Status (1)

Country Link
JP (1) JPS61170104A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474371B1 (en) * 2000-10-31 2005-03-08 매그나칩 반도체 유한회사 Linear gain control amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474371B1 (en) * 2000-10-31 2005-03-08 매그나칩 반도체 유한회사 Linear gain control amplifier

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