JP2974057B2 - Logarithmic IF amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logarithmic IF amplifier used in a receiver, and more particularly to a logarithmic IF amplifier having a reception electric field detecting function.

[0002]

2. Description of the Related Art In general, for example, a logarithmic IF amplifier circuit shown in FIG. 5 is known as a logarithmic IF amplifier circuit having a reception electric field detecting function (Japanese Patent Publication No. 6-59017).
Referring to FIG. 5, in the logarithmic IF amplifier circuit shown in the figure, the outputs (V ₁ , V ₂ ,... V _n ) of the n-stage differential amplifier are sequentially input to the next stage (Q ₂₁ , Q _{22 ,.} , _Qn2 ) is connected to the base of a differential pair composed of transistors having emitters having a predetermined ratio, and the collector current of the differential pair is added by an adder circuit. To detect the electric field.

That is, in the logarithmic IF amplifier circuit shown in FIG. 5, the differential amplifiers of the first to n-th stages sequentially amplify an input signal V _IN and output it as an output signal V _OUT . Meanwhile, the differential pair of first through composed predetermined transistor pair emitter size (n + 1) and receives the input signal or the output signal of the differential amplifier of each stage, the transistors Q _13,
The collector currents of the transistors Q ₂₃ ,..., Q _n3 , Q _{(n + 1) 3} are added by an adding circuit including transistors Q ₀₁ and Q ₀₂ , converted to a voltage V _LOG by a resistor R ₀₁ , and output.

In this logarithmic IF amplifier circuit, the input signal V _IN
, The collector current of the transistor Q _{(n + 1) 3} forming the _{(n + 1) th} differential pair sequentially saturates,
Finally collector current of the transistor Q ₁₃ constituting the first differential pair is saturated. Each collector current has a half-wave rectification characteristic and a saturation characteristic with respect to the input signal. Therefore, the respective collector currents of the transistors Q ₁₃ , Q ₂₃ ,..., Q _n3 , Q _{(n + 1) 3} are added. If smoothing is performed, a logarithmic characteristic approximated by a broken line with respect to the level of the input signal V _IN can be obtained.

[0005]

In the above-mentioned logarithmic IF amplifier circuit, the dynamic range of the logarithmic characteristic can be changed in magnitude and inclination, but the input level is shifted while maintaining the predetermined logarithmic characteristic. Is difficult to do. That is, it is difficult to adjust the input dynamic range.

Further, in the above-described logarithmic IF amplifier circuit, the addition circuit for obtaining the detection output has a capacitance and a resistor, but the time constant of the addition circuit is not increased due to the use of half-wave rectification. This causes a problem that ripples are generated and the detection output is not stable.

An object of the present invention is to provide a logarithmic IF amplifier circuit capable of adjusting an input dynamic range and stabilizing a detection output.

[0008]

According to the present invention, there are provided first to n-th stage (n is an integer of 2 or more) differential amplifiers and first to n-th differential pairs. The outputs of the first to n-th stage differential amplifiers are sequentially connected so as to be input to the next-stage differential amplifier, and the output of the n-th stage differential amplifier is an output signal. The first to n-th stage differential amplifiers have first and second transistors, respectively, and the first and second transistors have their emitters connected to each other to form a common emitter. , The first to n-th
Has a third transistor and a fourth transistor, respectively, an emitter resistor is connected to the emitter of the fourth transistor, and the emitter size ratio of the third and fourth transistors is N ( N is a non-zero number) to 1
Wherein the common emitters of the first to n-th stage differential amplifiers are connected to the bases of fourth transistors of the first to n-th differential pairs, respectively. A reference voltage is applied to the base of the third transistor of the n-th differential pair, and the first to the n-th
In this differential pair, an output voltage is obtained from the collectors of the third and fourth transistors, whereby a logarithmic IF amplifier circuit is obtained.

That is, according to the present invention, N stages of differential amplifiers are connected so that the outputs of the n stages of differential amplifiers are sequentially input to the next stage, and the common emitter of each differential amplifier has a predetermined emitter size. The differential pair is composed of a transistor having a ratio N and a transistor having an emitter size ratio of 1 and having an emitter resistance, and the collector currents of the n-stage differential pair are added. The output is stabilized using full-wave rectification.

[0010] The dynamic range of a differential pair composed of transistors having an emitter resistance shifts by an amount corresponding to the value of the emitter resistance. Accordingly, the dynamic range of the logarithmic IF amplifier circuit composed of n stages of differential pairs also shifts because it is the sum of the dynamic ranges of the individual differential pairs.

Further, since the output from the common emitter of the n-stage differential amplifier has a full-wave rectified waveform, the output can be operated more stably than a circuit using half-wave rectification.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, the illustrated logarithmic IF amplifier circuit includes an n-stage (first to n-th) differential amplifiers and first to n-th differential pairs. First and second transistors each Q ₁₁ in the first stage to each of the n-th stage of the differential amplifier has first and second transistors (first-stage differential amplifier and Q ₁₂ Similarly, the first and second transistors are represented by Q _n1 and Q _n2 in the n-th stage differential amplifier, respectively, and the first and second transistors are represented by the first and n-th stage differential amplifiers. The emitters of the second transistor are connected to each other to form a common emitter. The constant current sources _{IEEE11 to IEEE1} are connected to these common emitters, respectively.

[0014] In the first stage of the differential amplifier, the collectors of the first and second transistors are connected to a power supply line Vcc through respective resistors R ₁₁ and R _12, in the same way, the difference between the n-th stage In the dynamic amplifier, the collectors of the first and second transistors are connected to a power supply Vcc via resistors _Rn1 and _Rn2 , respectively. Then, the input signal Vin is provided between the bases of the first-stage differential amplifier.

The first to n-th stage differential amplifiers have the collectors of the first and second transistors of the preceding stage differential amplifier, respectively, and the second and first stage differential amplifiers of the next stage. The output signal Vout is obtained from between the collectors of the first and second transistors in the n-th stage differential amplifier connected to the bases of the transistors. That is, the first to n-th stage differential amplifiers sequentially amplify the input signal Vin and output it as the output signal Vout.

The first to n-th differential pairs have third and fourth transistors, respectively (the third and fourth transistors in the first differential pair are Q ₁₃ and Q ₁₄ , respectively).
Similarly, the third and fourth transistors in the n-th differential pair are represented by Q _n3 and Q _n4 , respectively, and the emitters of the fourth transistor in the first to n-th differential pairs are each is connected to the emitter resistor R ₁₃ to R _n3, emitters of the third and fourth transistors are connected to each other through an emitter resistor R ₁₃ to R _n3. Each of these emitters has a constant current source _{IEEE12 to IEE12 to IEE12.
EEn2} is connected.

In the first to n-th differential pairs, the base of the third transistor is connected to the reference voltage _VREF, and the base of the fourth transistor is connected to the common emitter of the differential amplifier of each stage. Is connected. Further, in the first to n-th differential pairs, the collector of the third transistor is connected to the power supply line Vcc via a smoothing circuit (addition circuit) including a resistor R and a capacitor C. On the other hand, the collector of the fourth transistor is connected to the power supply line Vcc. Then, as described later, the first
To the n-th differential pair are added, and the voltage V
The voltage V _RSSI is output as _RSSI , and has a logarithmic characteristic with respect to the input signal.

The first to fourth transistors are NP
N transistor.

Now, focusing on the n-th differential pair, assuming that the emitter resistance R _n3 = 0 of the _n -th differential pair, _Equations 1 and 2 hold.

[0020]

(Equation 1)

[0021]

(Equation 2) Where V _id is the differential input voltage of the nth differential pair,
It is represented by Equation 3.

[0022]

(Equation 3) Also, V _BEn3 and V _BEn4 are each base-emitter voltage of the transistor Q _n3 and Q _n4, I _sn3 and I
_sn4 , I _cn4 and I _cn4 represent the saturation current and the collector current of the transistor Q _n3 and the transistor Q _n4 , respectively. Then, V _T is expressed by Expression 4.

[0023]

(Equation 4) When Equation 2 is further transformed, Equation 5 is obtained.

[0024]

(Equation 5) On the other hand, _{assuming that} the amplification factor of the transistors Q _n3 and Q _n4 is α _F , _Equation 6 holds.

[0025]

(Equation 6) Therefore, Equations 7 and 8 hold from Equations 5 and 6.

[0026]

(Equation 7)

[0027]

(Equation 8) Here, N = I _sn3 / I _sn4 and the transistor Q _n3
And the emitter size ratio of Q _n4 .

Such a relationship is expressed by the first to (n-1) th
Holds for the differential pair.

FIG. 2 shows only the n-th stage differential amplifier.
Figure 2 also with reference, when the transistor Q _n1 and both phases input V _in to the base of Q _n2 is input, the transistor Q _n1 and Q _n2 of the differential amplifier of the n-stage is saturated, this time, the common emitter output voltage V _n from is a full-wave rectified waveform of the input voltage V _in. When this rectified wave is input to the n-th differential pair, the current shown in Expression 7 or 8 flows through each collector of the n-th differential pair. Since the collectors are connected in n stages, this current is added and averaged to the output of the n-th differential pair by an adder circuit (smoothing circuit) composed of a resistor R and a capacitor C. Here, the sum of the collector currents I _O (bar)
Is shown by Equation 9.

[0030]

(Equation 9) Further, the output voltage V _RSSI is represented by _Expression 10.

[0031]

(Equation 10) Equations 9 and 10 show that the output exhibits logarithmic characteristics.

[0032] Now, as the input waveform V _in it is represented by the number 11.

[0033]

[Equation 11] The output voltage V _RSSI, since it can be considered as the average of the sum of the input waveform V _in, the number 12 is established.

[0034]

(Equation 12) As is clear from Equation 12, the output voltage V _RSSI can be represented by a simple equation.

FIG. 3 shows the current waveform at this time. As described above, since the input is a full-wave rectified waveform, the average value is higher and more stable than the average value of the half-wave rectified waveform.

If the emitter resistance R _n3 of the transistor Q _n4 of the n-th differential pair is a predetermined value R _E (≠ 0),
Is given by Expression 13.

[0037]

(Equation 13) Input dynamic range at this time, as shown in FIG. 4, is shifted, the value of R _E, input dynamic range can be adjusted to the desired range.

Further, the transistor Q _n4 of the n-th differential pair through which the sum current I _O flows through the addition circuit (smoothing circuit) shown in FIG.
Replaced with the collector side, connecting the collector of Q _n3 to V _CC, it is possible to the characteristics of the dynamic range as shown in FIG. 4 and negative slope.

Further, the logarithmic IF amplifier circuit shown in FIG.
Compared to the logarithmic IF amplifier circuit shown in FIG. 5, since the upper differential amplifier and the lower differential pair are connected in series, the capacitive load by the transistor is small, the frequency characteristics are excellent, and the band is wide.

[0040]

As described above, according to the present invention, a multi-stage IF amplifier having good linearity of logarithmic characteristics and capable of temperature compensation is connected to a differential pair having an emitter size having a predetermined ratio and an emitter resistance. Then, since the collector current is added, the input dynamic range can be adjusted, which has the effect of adjusting the input level.

Further, in the present invention, the NPN transistor is used for the differential amplifier and the differential pair, that is, since the PNP transistor is not used, the circuit scale can be reduced, and as a result, the IC is configured. IC
There is an effect that can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a logarithmic IF amplifier circuit according to the present invention.

FIG. 2 is a diagram for explaining an operation of the n-th stage differential amplifier shown in FIG. 1;

FIG. 3 is a diagram for explaining an operation of an n-th differential pair in FIG. 1;

FIG. 4 is a diagram for explaining a shift of an input dynamic range in the logarithmic IF amplifier circuit shown in FIG. 1;

FIG. 5 is a circuit diagram showing a conventional logarithmic IF amplifier circuit.

[Explanation of symbols]

Q ₁₁ to Q _n1 transistors Q ₁₂ to Q _n2 transistor Q ₁₃ to Q _n3 transistor Q ₁₄ to Q _n4 transistor R resistor R ₁₁ to R _n1 resistor R ₁₂ to R _n2 resistors R ₁₃ to R _n3 emitter resistor C capacitors I _EE11 ~ I _EEn1 constant current source I _{EE12 to} I _EEn2 constant current source

Claims (6)

(57) [Claims] A first stage to an n-th stage (where n is an integer of 2 or more) and a first to an n-th differential pair; Are connected so that the respective outputs of the differential amplifiers are sequentially input to the next-stage differential amplifier, and the output of the n-th differential amplifier is used as an output signal.
The first to n-th stage differential amplifiers have first and second transistors, respectively, and the first and second transistors have their emitters connected to each other to serve as a common emitter. The n-th differential pair is the third and fourth
And an emitter resistor is connected to the emitter of the fourth transistor. The emitter size ratio of the third and fourth transistors is N (N is a number other than zero) to 1. The common emitters of the first to n-th stage differential amplifiers are connected to the bases of fourth transistors of the first to n-th differential pairs, respectively; A reference voltage is applied to the base of the third transistor in the n-th differential pair, and an output voltage is obtained from the collectors of the third and fourth transistors in the first to n-th differential pairs. A logarithmic IF amplifier circuit characterized in that: 2. The logarithmic IF amplifier circuit according to claim 1, further comprising an adding means for adding the collector currents of said first to n-th differential pairs to obtain said output voltage. Logarithmic IF amplifier circuit. 3. The logarithmic IF amplifier circuit according to claim 1, wherein an input signal is provided between bases of said first and second transistors constituting said first stage differential amplifier. A logarithmic IF amplifier circuit characterized in that: 4. The logarithmic IF amplifying circuit according to claim 3, wherein the first and the n-th differential amplifiers are connected to each other when the first and the n-th differential amplifiers are connected. The collector of the second transistor is connected to the bases of the second and first transistors of the differential amplifier located at the next stage, respectively, and the first and second transistors are connected at the n-th stage differential amplifier. A logarithmic IF amplifier circuit wherein the output signal is obtained from between the collectors of the transistors. 5. The logarithmic IF amplifier circuit according to claim 1, wherein said N is defined by a saturation current of said third and fourth transistors. 6. The logarithmic IF amplifying circuit according to claim 1, wherein said first to fourth transistors are NPN transistors.