JP3355839B2 - Logarithmic conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logarithmic conversion circuit, and more particularly to a logarithmic conversion circuit for performing logarithmic conversion using a logarithmic relationship established between a collector current (Ic) of a transistor and a forward voltage (V _BE ). .

[0002]

2. Description of the Related Art When an analog signal such as an audio output or an output from a sensor has a wide output range, it is often log-compressed and displayed. A logarithmic conversion circuit performs the logarithmic compression. The conversion circuit generally uses the fact that the forward current and the forward voltage of the semiconductor PN junction have a logarithmic relationship. FIG. 4 is a circuit diagram showing the most basic conventional example of the logarithmic conversion circuit. In this circuit, an input voltage Vin is input to an inverting input terminal of an operational amplifier OP via a resistor R, and a non-inverting terminal of the operational amplifier OP is grounded.
The collector of the logarithmic conversion transistor Q is connected to the inversion terminal, the emitter of the transistor Q is connected to the output terminal, and the reference potential V1 is applied to the base.

In the logarithmic conversion circuit shown in FIG. 4, a current Ia of Vin / R flows through a resistor R. Transistor Q
Is equal to the current Ia flowing through the transistor Q. By the way, the current Ib flowing through the transistor Q is expressed by the following equation (1).

[0004]

(Equation 1)

Since Ia = Ib, the following equation (2) is established.

[0006]

(Equation 2)

The output voltage Vou is obtained from the above equation (2).
The following mathematical expression 3 for obtaining t can be obtained.

[0008]

(Equation 3)

In the conventional logarithmic conversion circuit shown in FIG. 4, there is a transistor Is in the equation (3) for calculating the output voltage Vout, and this Is has a variation due to the transistor, so that an error occurs in the output voltage Vout. There was a disadvantage that it occurred. Therefore, as shown in FIG. 5A, an attempt has been made to improve a logarithmic conversion circuit in which such an error is reduced by using a difference ΔV _BE between V _BE of two transistors Qa and Qb. Qa is connected between the collector and the base,
The emitter receives the reference voltage V1, the base and the emitter are connected, and a current proportional to the input voltage (input current)
A transistor in which Iin flows as a collector current, Qb is a transistor having a base connected to the base and emitter of transistor Qa, from which the output of the logarithmic conversion circuit is taken. A constant current source (I1) is connected to the emitter of the transistor Qb so that a constant current I1 flows.

The output voltage Vout of this logarithmic conversion circuit is expressed by the following equation (4).

[0011]

(Equation 4)

FIG. 5B is an input / output characteristic diagram of the logarithmic conversion circuit shown in FIG. As is clear from the input / output characteristic diagram, when the input current Iin becomes smaller than the value obtained by dividing the constant current source I1 by 1 + current amplification factor h _fe , the transistor Qb turns off, and the output voltage Vout becomes zero. That is, the lower limit of the dynamic range of the logarithmic conversion circuit is determined by a value obtained by dividing I1 by 1 + h _fe .

The V of two transistors Qa and Qb
As another improvement of the logarithmic converter having a small error Kakaru using the difference [Delta] V _BE of _BE, there is shown in FIG. 6 (A). This logarithmic conversion circuit is different from the logarithmic conversion circuit of FIG. 5A in that a constant current source I1 is connected to the collector side of a transistor Qa, and an input current Iin flows as an emitter current to a transistor Qb. The only difference is in the point. The output voltage V of the logarithmic conversion circuit shown in FIG.
out is represented by the following equation (5).

[0014]

(Equation 5)

FIG. 6B is an input / output characteristic diagram of the logarithmic conversion circuit shown in FIG. 5A. As is apparent from the input / output characteristic diagram, when the input current Iin is larger than the product of the constant current source current I1 and h _fe +1, no current flows through the transistor Qa. The current is intercepted and the output voltage Vout falls to the ground level. That is,
The upper limit of the dynamic range of the logarithmic conversion circuit is 1 + h
_It is determined by the product of _fe and the current I1 of the constant current source.

[0016]

Each of the logarithmic conversion circuits shown in FIGS. 5 and 6A has a smaller error than the logarithmic conversion circuit shown in FIG. Thus, there is a problem that the dynamic range is narrow. That is, the logarithmic conversion circuit of FIG. 5 (A), the lower limit of the dynamic range is defined by dividing a value obtained by the current I1 of the constant current source 1 + h _fe, also logarithmic converter of FIG. 5 (B), h _fe The upper limit is defined by the product of +1 and the current value I1 of the constant current source.

The present invention has been made in order to solve such a problem, and has a problem that the collector current (I
An object of the present invention is to provide a logarithmic conversion circuit that performs logarithmic conversion using a logarithmic relationship that is established between c) and a forward voltage (V _BE ), while widening the dynamic range while eliminating errors due to variations in Is.

[0018]

According to a first aspect of the present invention, there is provided a logarithmic conversion circuit comprising: a transistor Q1 in which an input current Iin flows as an emitter current; a transistor Q2 having the base connected to the transistor Q2; and a base connected to the emitter of the transistor Q1. A reference transistor is applied to the emitter, and a feedback transistor Q3 for controlling the base current supplied to the transistors Q1 and Q2 to be kept constant, and a base connected to the emitter of the transistor Q2 to reduce the emitter potential of the transistor. and transistor Q4 to shift in the direction to cancel the V _bE, the transistor Q
A transistor Q5 for supplying a base current to the transistors Q1 and Q2, and a constant current source I1 for supplying a collector current of the transistor Q3 and a base current of the transistor Q3.
And characterized by the following.

The logarithmic converter of claim 2 is the logarithmic converter of claim 1, wherein, a transistor Q6 which V _BE shifting the potential of the collector of the transistor Q1, the transistor Q6 and base over scan each other are connected, the transistor Q2 the collector potential and having a transistor Q7 which V _bE shift. A logarithmic conversion circuit according to a third aspect is characterized in that, in the logarithmic conversion circuit according to the second aspect, a transistor Q8 has a base connected to the collector of the transistor Q2 and an emitter connected to the collector of the transistor Q4.

[0020]

SUMMARY OF] According to the logarithmic converter of claim 1, since the use of the difference [Delta] V _BE of V _BE of the transistor Q1 and Q2 to logarithmic conversion, eliminating errors due to variations in V _BE · base current characteristics of the transistor Therefore, the error can be reduced as compared with the logarithmic conversion circuit shown in FIG. And
The output voltage is shifted by the feedback transistor Q3 by the V _{BE of} the transistor Q3. However, the transistor Q4 is provided on the output side and the V _BE shifted by the V _BE.
, There is no possibility that the output voltage is offset by the V _BE by the feedback transistor Q3.
Further, the base currents of the transistors Q1 and Q2 are fed back by the feedback transistor Q3 so that a constant value is always maintained for the same input current, thereby reducing the output voltage error due to the base current fluctuation. Besides, the lower limit of the dynamic range of the input current Iin that can be converted can be widened as compared with the conventional circuit shown in FIG.

Further, according to the logarithmic conversion circuit of the first aspect,
Transistors Q1, Q2 by feedback transistor Q3
Is controlled via the transistor Q5, the upper limit of the dynamic range can be increased to h _fe +1 times that of the transistor Q5, and the dynamic range can be further increased. According to the logarithmic conversion circuit of claim 2, the transistor Q
The collectors of 1 and Q2 can be made to have the same potential by transistors Q6 and Q7.
1, Q2 both can be equal by the V _BE of the collector-emitter voltage, it is possible to eliminate substantially the error of output voltage caused by the change of the h _fe due to fluctuations in the voltage. That is, an error due to the Early effect can be eliminated.

According to the logarithmic conversion circuit of the third aspect, the collector of the transistor Q4 for outputting a signal is connected to the transistor Q4.
8 makes it possible to securely hold the value V _BE shifted from the collector of the transistor Q2 and the collector-emitter voltage of the transistor Q4 in a substantially constant, therefore,
The Early effect of the transistor Q4 can also be canceled.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 is a circuit diagram showing one embodiment of the logarithmic conversion circuit of the present invention. The input voltage Vi is provided before the logarithmic conversion circuit.
There is a voltage / current conversion circuit that converts n into a current (input current) Iin proportional thereto. This voltage-current conversion circuit uses an operational amplifier OP1 to allow the current Iin (= Vin / R) obtained by dividing the input voltage Vin by the input resistance R to flow as an output, and this current is the input current for the logarithmic conversion circuit. Becomes

Next, the logarithmic conversion circuit will be described. Q
Reference numeral 1 denotes a first transistor, which is of an npn type (the transistors of the embodiments in FIGS. 1 and 3 are all npn type),
In addition, the input current Iin flows as an emitter current. Its collector is connected to the power supply voltage terminal (plus). Q2 is a second transistor,
Its base is connected to the base of the first transistor Q1, and its emitter is grounded via the constant current source I2. Q3 is a third transistor having a base connected to the emitter of transistor Q1, receiving a predetermined reference potential V1 at the emitter, and receiving a collector current from constant current source I1. This transistor Q3, together with a fifth transistor Q5 to be described later,
1 and 2 serve as a feedback transistor that controls the base current by applying feedback so as to always keep the base current constant for the same input current.

Q4 is a fourth transistor having a base connected to the emitter of the second transistor Q2, a collector connected to the power supply terminal, an emitter grounded via a constant current source I3, and Is the output point of this logarithmic conversion circuit. The transistor Q4 is a transistor for canceling the shift of the output voltage Vout by the V _BE of the transistor Q3. Q5 is a fifth transistor. The base is connected to the connection point between the transistor Q3 and the constant current source I1, the collector is connected to the power supply terminal, and the emitter is connected to the emitter of the transistor Q2 and the bases of the transistors Q1 and Q2. I have.

The transistor Q3, together with the transistor Q5, plays a role in maintaining a constant base current for the same input current of the transistors Q1 and Q2. That is, if the base current of the transistor Q1 with respect to the input current increases, the base potential of the transistor Q3 rises. Then, the collector current of the transistor Q3 increases. Then, the base current of the transistor Q5 decreases by the increased amount, and the base current supplied to the transistor Q1 via the transistor Q5 decreases. As described above, the transistor Q3 functions as a feedback transistor that detects the base potential of the transistor Q1 and negatively feeds it back to keep the base current for the same input current constant.

Next, a non-inverting amplifier circuit for amplifying the output voltage Vout of the logarithmic conversion circuit will be described. OP2 is an operational amplifier whose non-inverting input terminal is connected to the emitter of the transistor Q4, which is the output point of the logarithmic conversion circuit, and receives the reference potential V1 at the inverting input terminal. R1 is an input resistor connected to the inverting input terminal, and R2 is a feedback resistor connected between the output terminal and the inverting input terminal. Vout ′ is the output voltage of the non-inverting amplifier circuit.

In this logarithmic conversion circuit, the voltage rises by 2V _BE above the reference voltage at the transistors Q3 and Q1,
Then, the transistor Q2, Q4 down 2V _BE and Δ
V _BE is obtained and logarithmically converted. By the way, the output voltage Vout of the logarithmic conversion circuit is obtained by the following equation (6).

[0029]

(Equation 6)

It should be noted that V _BE 1, V _BE 2, V _BE 3, V
_BE 4 is V _BE , I of transistors Q1, Q2, Q3, Q4.
1, I2 and I3 are current values of the constant current sources I1, I2 and I3. Then, in Equation 6, I2 and I3 may be reversed. In Equation 6, the first term (1) is the reference voltage, the second
The term (2) is a logarithmic conversion value, and the third term (3) is an offset. As is apparent from this equation, there is no large variation Is in the transistor. Therefore, there is no error due to Is as in the logarithmic conversion circuit of FIG.

Since the base currents of the transistors Q1 and Q2 with respect to the same input current are controlled to be constant by applying feedback by the transistors Q3 and Q5 as described above, the output voltage Vout and the input current I
The error caused by the change of in is Iin / (h _fe +1)
^It becomes ² and can be made very small. The dynamic range of the logarithmic conversion circuit is I1 / h _fe <Iin <(h _fe +1) ² · I 1 on the basis of an error of 6 dB. That is, the lower limit is that the base current of the feedback transistor Q3 is equal to the input current Iin and the error is 6 dB, and the upper limit is that the base current of the transistor Q5 is equal to I1 and the feedback is cut off and the operation stops.

FIG. 2 shows the dynamic range of this logarithmic conversion circuit. When this dynamic range is compared with that of the logarithmic conversion circuit shown in FIG. 5A, the lower limit is widened. Of course, the error increases near the lower limit,
This error can be reduced by calibration or the like.
The upper limit is wider than that of the logarithmic conversion circuit shown in FIG. As described above, according to the logarithmic conversion circuit, the output voltage Vout does not depend on Is, there is no error due to the change in Vin, and the dynamic range can be widened.

FIG. 3 is a circuit diagram showing another embodiment of the logarithmic conversion circuit of the present invention. This circuit includes transistors Q6 and Q6.
7 and Q8 are provided on the collector side of the transistors Q1, Q2 and Q4, and the voltage between the collector and the emitter of each of the transistors Q1, Q2 and Q4 is made substantially equal to V _BE so that the voltage between the collector and the emitter is reduced. It is kept constant, and h _fe does not fluctuate. That is,
The error is reduced by preventing the fluctuation of h _fe (Early effect) due to the fluctuation of the voltage between the collector and the emitter to prevent the fluctuation of h _fe .

Specifically, the transistor Q6 has an emitter connected to the collector of the transistor Q1, a collector connected to the power supply terminal, and a base connected to the base of the transistor Q7. Transistor Q7 has an emitter connected to the collector of transistor Q2, a collector connected to the emitter of transistor Q5, and an emitter of transistor Q5 connected to the bases of transistors Q6 and Q7. Thereby, the transistor Q
1, the collectors of Q2 are made substantially the same potential, and hence the collector-emitter voltage is made substantially equal, so that the Early effect can be suppressed. Also, the transistor Q8
Has an emitter connected to the collector of transistor Q4, a collector connected to the power supply terminal, and a base connected to the collector and base of transistor Q2. Therefore, the voltage between the collector and the emitter of the transistor Q4 is kept at V _BE , and the Early effect is suppressed.

The above logarithmic conversion circuit performs ΔV _BE using four transistors Q1, Q2, Q3, and Q4 to perform logarithmic conversion. However, ΔV _BE is determined by a combination of even more than four transistors. You may make it and perform logarithmic conversion. In the above embodiment, each transistor of the logarithmic conversion circuit is an npn transistor.
It goes without saying that the logarithmic conversion circuit may be constituted by pnp transistors.

[0036]

According to the logarithmic conversion circuit of the first aspect, since the difference ΔV _BE between V _BE of the transistors Q1 and Q2 is used for logarithmic conversion, an error caused by variation in V _BE and base current characteristics of the transistors. Can be eliminated, and the error can be reduced as compared with the logarithmic conversion circuit shown in FIG. The output voltage is shifted by the feedback transistor Q3 by the V _{BE of} the transistor Q3. However, since the transistor V4 is provided on the output side to cancel the shifted V _BE by the V _BE , the feedback transistor Q3 is used. There is no possibility that the output voltage is offset by V _BE due to Q3. Further, the base currents of the transistors Q1 and Q2 with respect to the same input current are fed back by the feedback transistor Q3 so as to be kept constant, so that the error of the output voltage due to the fluctuation of the base current can be reduced and the input which can be converted. The lower limit of the dynamic range of the current Iin can be reduced.

Further, according to the logarithmic conversion circuit of the first aspect,
Transistors Q1, Q2 by feedback transistor Q3
Is controlled via the transistor Q5, the upper limit of the dynamic range can be increased to h _fe times that of the transistor Q5, and the upper limit of the dynamic range can be further increased. According to the logarithmic conversion circuit of claim 2, the transistors Q1 and Q2
Of the collectors can be made the same potential by transistors Q6 and Q7.
And the collector-emitter voltage of
An error in the output voltage due to a change in _hfe due to the voltage change can be substantially eliminated. That is, an error due to the Early effect can be eliminated.

According to the logarithmic conversion circuit of the third aspect, the collector of the transistor Q4 for outputting a signal is connected to the transistor Q4.
8 makes it possible to securely hold the value collector or V _BE shift of the transistor Q2 and the collector-emitter voltage of the transistor Q4 in a substantially constant, therefore, can be canceled also Early effect of the transistor Q4.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a logarithmic conversion circuit of the present invention.

FIG. 2 is an input / output characteristic diagram of the embodiment.

FIG. 3 is a circuit diagram showing another embodiment of the logarithmic conversion circuit of the present invention.

FIG. 4 is a circuit diagram showing a basic conventional example of a logarithmic conversion circuit.

5 (A) and 5 (B) show one improved example of the logarithmic conversion circuit shown in FIG. 4, and FIG. 5 (A) is a circuit diagram,
(B) is an input / output characteristic diagram.

FIGS. 6A and 6B show another example of an improvement to the logarithmic conversion circuit shown in FIG. 4; FIG.
(B) is an input / output characteristic diagram.

[Explanation of symbols]

Q1~Q8 transistor I1~I3 constant current source Iin input current V1 reference potential Vout output voltage V _BE between the base and the emitter voltage

Continuation of front page (56) References JP-A-1-303807 (JP, A) JP-A-57-206107 (JP, A) JP-A-61-16312 (JP, A) JP-A-56-137717 (JP, A) JP-A-56-144612 (JP, A) JP-A-5-37260 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03G 11/08 H03F 3/343

Claims (3)

(57) [Claims] 1. A first transistor in which a current (input current) proportional to an input voltage flows as an emitter current, a second transistor having a base connected to the base of the first transistor, A base is connected to the emitter of the first transistor, a reference potential is applied to the emitter, and feedback control is performed to maintain a constant base current supplied to the first and second transistors for the same input current. and third transistor, the emitter potential emitter to the base is connected to the second transistor, a fourth transistor that shifts in a direction of canceling the base-emitter voltage of said third transistor, said first And the base current for the second transistor
A fifth transistor for supplying, a collector current of the third transistor, and a fifth transistor .
A constant current source for supplying a base current of the transistor; 2. A sixth transistor to the base-emitter voltage shifted the potential of the collector of the first transistor, the sixth transistor preparative base over scan each other above SL is connected, the collector of the second transistor logarithmic converter according to claim 1, wherein a, a seventh transistor of a voltage shifted base-emitter potential 3. The logarithmic conversion circuit according to claim 2 , further comprising: an eighth transistor having a base connected to the collector of the second transistor and an emitter connected to the collector of the fourth transistor.