JPS61166207A - Intermediate frequency amplifier circuit with electric field strength detecting function - Google Patents

Abstract

PURPOSE:To obtain an electric field detecting function over a wide dynamic range by connecting a transistor pair inserted with an emitter resistor in parallel with a transistor (TR) pair being the 1st input of the 1st stage double balanced differential amplifier so as to detect up to a large signals input. CONSTITUTION:TRs Q1-Q14 constitute the 1st stage full wave rectifier, TRs Q15-Q26 constitute the 2nd stage, TRs Q27-Q38 constitute the 3rd stage and TRs Q39-Q50 constitute the 4th stage of full wave rectifier, Q51, Q52 constitute a current mirror circuit adding load currents of the 1st 4th stage full wave rectifiers and output a DC voltage Vs smoothed by a resistor R23 and a capaci tor C1. After an IF input signal VIN is amplified by the 1st stage differential amplifier comprising the TRs Q1, Q2, the result is subjected to level shift by the TRs Q3, Q4, amplification and level shift are repeated sequentially and outputted as an IF output V0 by an output of the TRs Q41, Q42. On the other hand, when the IF input signal VIN is increased gradually, the double balanced differential amplifiers are saturated sequentially from the 4th stag, the post- stage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of an intermediate frequency amplifier of a receiver, and in particular to a receiving electric field detection method suitable for use in mobile radios, telemeters, and the like.

Prior art The prior art of the present invention includes, for example, Micro-e
electronics and Re1iabi1it
y, vol, 16. pp, 345-366° Perga
mon Press, 1g77 exists. The circuit configuration shown in FIG. 3, which is disclosed as a conventional example of the present invention, is a part of an IC called CA3089 shown in the above-mentioned document. Others - The portions in the above document that are related to FIG. 3 of this specification are Fig. 1 and Fig. 2.

FiglO, Figll, Figl2 and their explanatory text.

Conventionally, the configuration of an intermediate frequency amplifier with an electric field detection function is as follows:
As shown in Figure 3, a multi-stage amplifier (transistor Q
1'-Q1o', transistor Q11'
- a second stage consisting of Q19', transistors Q20' to Q;
The output of each stage of the third stage consisting of 27' is connected to a capacitor (0
8', 09', 010'), and the rectified current waveforms of each stage were added to output electric field level information.

Problems to be Solved by the Invention In the configuration of the above-mentioned conventional intermediate frequency amplifier, rectification of the S direct signal is performed using diodes (Q28', Q29', Q30').
; Q32', Q33', Q34';Q35', Q36
', Q37'), the temperature characteristics deteriorate and the circuit becomes complicated to compensate for the temperature characteristics.

In addition, since the rectifier is a half-wave rectifier using diodes as described above, each capacitor (08',
09', CIO'). Therefore, lowering the intermediate frequency requires a correspondingly larger capacitor. Therefore, when integrated into an IC, the chip size becomes large in order to form the above-mentioned capacitor. Furthermore, in order to reduce the chip size by attaching an external capacitor, an external capacitor is required for each stage. For this reason, the number of external capacitor terminals increased, which was disadvantageous for IC implementation.

In addition, the regulator uses diodes as described above, and therefore can only detect signal input up to the point where the first stage differential amplifier consisting of transistors Ql' to QlO' is saturated. Even if the total gain of the differential amplifier was increased by increasing the number of stages in order to widen the dynamic range, the maximum input level was determined at the above-mentioned saturation level, and a sufficient dynamic range could not be obtained.

First, in order to reduce the deviation from the linearity of the input signal detection voltage with respect to the lock characteristic, the gain per stage of the above-mentioned differential amplifier is generally lowered and the stage is multi-stage, and the above-mentioned rectifier is The number of stages must also match the number of stages of the differential amplifier. Therefore, as many capacitors as the number of rectifier stages are required as described above, and the above-mentioned drawbacks are further magnified.

The present invention was made in view of the above-mentioned conventional circumstances.
Therefore, it is an object of the present invention to improve the above-mentioned drawbacks and to provide an electric field with a wide dynamic range that operates from a low intermediate frequency, has ambiguous temperature characteristics of the input electric field detection voltage, and operates even at high input signal levels with poor linearity. An object of the present invention is to provide a novel intermediate frequency amplification circuit having a detection function on a small circuit scale.

Means for Solving the Problems In order to achieve the above object, the field strength detection function according to the present invention includes an intermediate frequency amplification circuit having n stages of differential amplifiers each consisting of a pair of transistors whose emitters are commonly connected; A first intermediate frequency amplifier is constructed in which the output of each differential amplifier is sequentially connected to the input of the next stage, and the input signal at each stage of the differential amplifier is the first human power. There are n double-balanced differential amplifiers each corresponding to the differential amplifier, each consisting of an input pair and a second input pair whose second input is the output signal of each stage of the differential amplifier, and the n An intermediate frequency jI1 width circuit which has the function of outputting a DC voltage corresponding to an input current transformation signal by a circuit that adds the positive phase output iI currents of each of the double balanced differential amplifiers. The first input pair of the double-balanced differential amplifier of the vJ stage includes a first differential transistor pair whose emitters are commonly connected not through an emitter resistor, and a first differential transistor pair whose emitters are commonly connected through an emitter resistor. The present invention is characterized in that n 20th differential transistor pairs are connected in parallel to each other.

Embodiment of the Invention Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and is a circuit configuration diagram for a four-stage configuration.

・In FIG. 1, transistors Ql-Q14 constitute a first-stage double-wave rectifier, and transistors Q15-Q26
constitutes the second stage double-wave rectifier, and transistor Q27
-Q38 constitute a third-stage double-wave rectifier, transistors Q39-Q50 constitute a fourth-stage double-wave rectifier, and transistors Q51. Q52 constitutes a current mirror circuit that adds the load currents of the double-wave rectifiers from the first stage to the fourth stage, and outputs the smoothed DC voltage as Vs to the resistor R23 and capacitor C1. There is.

Now, the IP input 1N signal Vtpt#: t) is amplified by the first stage sliding amplifier consisting of 7:z sister QISQ2.
't: After that, the level is shifted by the transistors Q3 and Q4, the +1st order increase m and the level shift are repeated, and the output of the transistors Q41 and Q42 is outputted as the IF output vO.

- When the IP input signal Vry gradually increases, the double-balanced differential amplifiers gradually become saturated starting from the fourth stage.

First, the saturation level of the fourth stage double-balanced differential amplifier will be explained. Since the double-balanced differential amplifier described above is a multiplier, the first input V4, ! is input to the base pair of transistors Q47, Q48. : Second input input to the base pair of transistors Q43 to Q460■0
It is saturated for any n.

[7] Since the relationship between the input level v1 and the output level vO of the fourth differential amplifier is 0≧v4, the fourth
The saturation of the double-balanced differential iv1 width amplifier in the second stage is determined by the first input v.
The amplitude of 4 is determined by xF>n. At this time, the saturation amplitude is: ■1≧2Vr・・・・・・・・・・・・・・・・・・
・・・－・・・・・・・・・・・・・・・・・・・・・
・(1).

However, Vr = kT/q k: Borckmann constant T: Absolute temperature q Two unit electron charges Similarly, for the third stage double-balanced differential amplifier, v3≧2Vr ・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・ (2
) Similarly for the second stage double-balanced differential amplifier, ■3≧2Vr ・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
(3) The first stage double-balanced differential amplifier is as follows.

First, regarding the differential amplifier composed of the constant current source 13, ■IN≧2Vr・・・・・・・・・・・・・・・・・・
・－・・・・・・・・・・・・・・・・・・ Song・・・・・・
...(4) Difference IklJ il composed of constant current source I3
For a 1-width device, R□R7=RE1, Vrpt≧2Vr +it kr 113...
・・・・・・・・・・・・・・・・・・・・・・・・(5
) Here, if 2■1"〈几EIIa is selected, the saturation of the first stage double-balanced differential amplifier is: ■IN≧2Vr -1−REII I s...
・・・・・・・・・－・・・・・・・・・・・・・・・・・・
...(6) This occurs for an input signal level of (6). That is, the saturation level of the first stage double-balanced differential amplifier is 2.
01 og (1+2 v, ) d B improved. In other words, the field strength detectable input signal level of the IP amplifier is improved.

The solid line in FIG. 2 shows the %i of the output sink current Is in FIG. 1 with respect to the input signal level Vtpt (dB value). Break@U,) Langister Qll.

The case is shown in which Q12, resistors R6 and R7, and constant iut source I3 are removed.

Effects of the Invention As explained in the embodiments, according to the present invention, by connecting in parallel a pair of transistors in which an emitter resistor is inserted in a pair of transistors serving as the first input of a double-balanced differential amplifier at the first stage. , it can detect up to large signal inputs and provides electric field detection functionality over a wide dynamic range.

Also, as shown in Figure 1, by using a double-balanced differential amplifier as a double-wave rectifier, the phases can be matched, and the rectifier for each stage, which was required in the case of the half-wave rectifier described above, can be adjusted. A capacitor can be omitted.

Therefore, according to the present invention, the rectifier capacitor is
There is also the advantage that there is no need for integration on a C chip, and that an electric field strength detection function that operates from low frequencies can be realized with a small chip area.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an example of the present invention in which the fabric is constructed in four stages and has nine stages. Q1~Q52---Transistor, R11~R23---
・Resistance, C1... Capacitor, Vcc *... Power supply voltage, I=, b, I-... Constant current source) I
B@... Output section sink current, VIN +1 @・IF
Input signal, ■...IF output signal. Figure 2 shows the output sink current I in the circuit configuration of Figure 1.
The characteristic (solid line) of s vs. IP input voltage VIN is shown, and the output voltage Vl is determined by Va=Vcc-R23#Is. The broken line in Figure 2 is the transistor Q in Figure 1.
ll, Q12, resistors R6, R7, constant current source, [s
The characteristics when removed are shown below. FIG. 3 shows an example of a conventional circuit consisting of a three-stage differential amplifier circuit. Ql'~Q50'...e transistor, D1'...
Diode, rti'~R43' Resistance, C
1'~C11'/-9 capacitor, S-MBTEf
'L OUT・φ・Electric field detection level output terminal, VCC conflict・・Power supply voltage. Patent Applicant NEC Co., Ltd. Agent Patent Attorney Yutabe Kumagai Unexamined Patent Publication No. GL-IGG207 (6) Procedural Amendment, Kae, May 20, 1985 Patent Application No. 6844 2 Title of the Invention Electric field strength detection function (=j intermediate frequency amplification circuit 3 Relationship with the case of the person making the amendment Special agreement applicant address 5-33-1 Shiba, Minato-ku, Tokyo Name (42)
3) NEC Corporation Representative President Tadahiro Sekimoto 4 Agent Address No. 2407 Dia Palace Noborito, 1632 Shukugawara, Tama-ku, Yozaki City, Kanagawa Prefecture April 30, 1985 6 Subject of amendment l Jf. Detailed Explanation Column 7 Contents of Amendment ■, Lines 11 to 13 of the Specification No. 2 [For example, Micro-,...
1977 exists in the phrase ``For example, Microelectronics and Reliability, No. 16,
Pages 345-366, Pergamon Press, 1977
Published in (Mjcroelectronics and
Re1iabi…yevol-16+PP, 345
~366, Pergam On Press, 1977. ” he corrected.

Claims (1)

[Claims] There are n stages of differential amplifiers each consisting of a pair of transistors whose emitters are connected in common, forming an intermediate frequency amplifier in which the output of each differential amplifier is sequentially connected to the input of the next stage. a first input pair whose first input is the input signal of each stage of the differential amplifier; and a second input pair whose second input is the output signal of each stage of the differential amplifier. There are n balanced differential amplifiers corresponding to the differential amplifiers, and a circuit that adds the positive-sequence output currents of the n double-balanced differential amplifiers outputs a DC voltage with respect to the input AC signal level. In the intermediate frequency amplification circuit having a function capable of controlling 1. An intermediate frequency amplification circuit with an electric field strength detection function, characterized in that a second differential transistor pair whose emitters are connected in common through an emitter resistor are connected in parallel to each other.