JP3147986B2 - Expansion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a decompression circuit having a characteristic of converting to a raised level.

[0002]

2. Description of the Related Art Conventionally, there has been a circuit of this type as shown in FIG. Hereinafter, the circuit shown in FIG. 2 will be described. In the circuit shown in FIG. 2, 10 is an operational amplifier, 11 is a MOS transistor having a gate connected to a drain, 12 is a resistor, 13 is an input terminal, 14 is an output terminal of the operational amplifier 10, 15 is an inverting input terminal of the operational amplifier 10, 16 Is a non-inverting input terminal. The resistor 12 is connected between the output terminal 14 and the inverting input terminal 15. Input terminal 13 is MO
Connected to the drain of S transistor 11. The source of the MOS transistor 11 is connected to the inverting input terminal 15 of the operational amplifier 10. The other non-inverting input terminal 16 of the operational amplifier 10 is connected to a reference potential point, for example, a common potential point Vcom.

In this circuit, when an input voltage Vin is applied to an input terminal 13, the MOS transistor 11 operates in a saturation region.

[0004]

(Equation 1)

[0005] Here, Vth is the threshold voltage of the MOS transistor 11, W1 is the width of the channel, L
1 is the length of the channel and K 'is the gain factor.

Here, for simplicity of description, the common potential V
com is an intermediate potential Vcom = 0 between the positive power supply voltage VDD and the negative power supply voltage VSS not shown in FIG. Even in this case, the generality of the operation description and the equation is not lost.

Therefore, (1) can be rewritten as (1) 'equation.

[0008]

(Equation 2)

On the other hand, assuming that the output voltage of this circuit is Vout, the output terminal 14 is connected to the inverting input terminal 1 of the operational amplifier 10.
The current Iout flowing toward 5 is given by Iout = Vout / R (2) From the relational expression of Iin = −Iout, the relation between Vout and Vin is given by the following equation (3).

[0010]

(Equation 3)

In the equation (3), if Vth is neglected, this circuit becomes a square root circuit having an expansion characteristic that generates an output proportional to the square of the input level.

[0012]

However, in this circuit, it is difficult to control the gain coefficient K 'of the MOS transistor 11 and the resistance 12 when forming an LSI, and the elongation characteristics vary depending on the process, which is not practical. There was one disadvantage.

Further, as a second disadvantage, the MOS transistor 11 becomes non-conductive in a direction opposite to the current of Iin in the equation (1), that is, for a current flowing from the source to the drain of the MOS transistor 11,
The relationship of equation (3) does not hold. That is, the current Iin
When the input voltage Vin <0 is in such a direction, the extension characteristic cannot be obtained.

Therefore, a normal analog signal input that changes positively or negatively around the common potential point Vcom cannot be handled and is not practical.

As a third disadvantage, as can be seen from equation (3), the output voltage Vout of the circuit is

[0016]

(Equation 4)

The output changes nonlinearly in proportion to the input voltage Vin, resulting in a non-linear output and harmonic distortion. In an ordinary device for limiting a signal frequency band with a low-pass filter, the original waveform cannot be transmitted accurately, which is not practical.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a decompression circuit according to the present invention is a first gain control circuit for amplifying an analog input signal at a predetermined gain and outputting the amplified signal. A first gain control circuit in which the amplification factor changes in accordance with the change, a rectifier circuit for rectifying an output of the first gain control circuit, and an output of the rectifier circuit and a reference voltage. A control signal generation circuit that outputs the control signal in accordance with the following, and a second gain control circuit that amplifies an input analog signal at a predetermined amplification rate and outputs the amplified signal, and according to a change in the control signal, A second gain control circuit whose amplification rate changes at a rate equal to that of the first gain control circuit;
A differential amplifier circuit that amplifies a difference between the analog input signal and the output of the second gain control circuit and outputs the amplified signal to the second gain control circuit. In which an expanded signal is obtained.

[0019]

According to the present invention, when the input signal level is lower than the reference level, the signal is attenuated, and when the input signal level is higher than the reference level, the signal is amplified. It is possible to obtain an output signal which varies depending on the output signal.

[0020]

1 is a diagram showing the basic configuration of a decompression circuit according to the present invention, and FIG.
Is a diagram showing input / output conversion characteristics of the present invention, and the present invention will be described below with reference to these drawings.

In FIG. 1, GC1 and GC2 are gain control circuits, REC is a rectifier circuit, MEAN is an averaging circuit, and DF
AMP is an amplifier circuit.

Referring to FIG. 1, connection of the gain control circuit GC1 will be described.

In the gain control circuit GC1, IN is an input terminal, OUT1 is an output terminal, R113 is a resistor, AMP1
Reference numeral 15 denotes an operational amplifier, and RV114 denotes a voltage variable resistor.

The voltage variable resistor RV114 has a control electrode, the value of which changes according to the applied voltage applied to the control electrode, and is used for gain control. The resistance value decreases as the applied voltage increases, The resistance value increases as the applied voltage decreases, and can be configured by, for example, a MOS transistor or the like.

The input signal IN is input to the input terminal IN. The input signal Vin of the gain control circuit GC1 is divided by a resistor R113 and a voltage variable resistor RV114, one of which is connected to a common potential point Vcom, and an operational amplifier AMP115
, And is amplified by the gain (G115) of the operational amplifier AMP115 and output to the output terminal OUT1.

For the sake of simplicity, the common potential point Vcom is an intermediate potential point between the positive power supply voltage VDD and the negative power supply voltage VSS, not shown in FIG. 1, and Vcom = 0.

The output signal Vout1 of the gain control circuit GC1 is

[0028]

(Equation 5)

[0029]

(Equation 6)

## EQU1 ## Here, G1 is a gain control circuit GC
1, the ratio of the output voltage to the input voltage, that is, the gain control circuit G
The gain of C1.

In FIG. 1, this output Vout1 is input to a rectifier circuit REC.

As will be described later, level detection is performed on Vout1 to keep the input signal constant.

The level detection includes a method of detecting a peak value and an average power value. Hereinafter, an example of a method of detecting the average power value will be described. In general, the power is | V / √2 | ² / R, where V is the voltage of the resistor R. Therefore, the power may be converted to the absolute value of the voltage. This is usually the common potential point V
For example, a negative voltage of an input signal that changes to positive or negative with respect to com can be converted to an absolute value | Vout1 |

In FIG. 1, the full-wave rectified signal VRE
C = | Vout1 | is input to the averaging circuit MEAN.

The averaging circuit MEAN has an input terminal INMEA
N, a reference value input terminal INVPMEAN, an output terminal OMEAN, an analog subtractor SUB, a low-pass filter LPF, and an integrator INTEG.

The analog subtractor SUB has an input terminal INME
From the AN input signal VREC, the reference value input terminal INVPMEAN
Then, the error signal VERR is created by subtracting the reference value voltage VPMEAN of

When the full-wave rectified signal VREC is equal to the reference voltage VPMEA
If it is larger than N, VERR> 0, and if it is smaller than the reference value voltage VPMEAN, VERR <0, and power can be detected.

Here, the detection of the average value of the power, that is, the average power value is the same even if the voltage of the error signal VERR is averaged.

On the other hand, if the peak value of the input signal of the rectifier circuit REC is Vp and the sine wave signal has a period T, for example, the reference value VPMEAN of the average voltage is the following value as the average value of the signal VREC after full-wave rectification. Is sought.

[0040]

(Equation 7)

A sine wave signal having an average value represented by the equation (6) is a sine wave signal having a voltage peak value of VP, and the relationship between the reference value VPMEAN and the peak value VP is represented by the equation (6). It is.

The error signal VERR described above is represented by VERR = | Vout1 | -VPMEAN (7)

The error signal VER of the analog subtractor SUB
R is input to the low-pass filter LPF. The low-pass filter averages the error signal VERR in equation (7).

Next, the output of the low-pass filter LPF is
Input to the integrator INTEG.

One purpose of the integrator is to perform accurate control by integrating and increasing the error signal VERR, and the other is to use a variable voltage resistor of a gain control circuit that varies depending on the process when the LSI is implemented. Instead of directly outputting the average value of the error signal VERR as the control voltage, the control voltage is brought to the optimum value by the action of the integrator.

For example, when the average voltage of the absolute value | Vout1 | of the output is greater than the reference voltage VPMEAN, the output VCG of the integrator becomes positive when the average value of the error signal VERR is obtained, and the output voltage VCG of the integrator INTEG becomes Going up.

Conversely, the average power of the output Vout1 is equal to the reference value VPMEA.
If it is less than N, VCG goes down.

In FIG. 1, the output VCG of OMEAN at the output terminal of the integrator INTEG is input to the control input terminals GCC1 and GCC2 of each gain control circuit, and each of the voltage variable resistors RV11
4. Control the RV 124.

Therefore, when the absolute value | Vout1 | of the output of the gain control circuit GC1 is larger than the reference voltage VPMEAN, the output VREC of the rectifier circuit REC rises, and the resistance of the voltage variable resistor RV114 decreases, and As can be seen, the gain of the gain control circuit GC1 decreases and the output voltage Vout1 decreases.

Conversely, when the absolute value | Vout1 | of the output of the gain control circuit GC1 is smaller than the reference voltage VPMEAN, the output VREC of the rectifier circuit REC decreases and the voltage variable resistor RV11
The resistance of No. 4 increases, and as can be seen from equation (4), the gain of the gain control circuit increases and the output voltage Vout1 increases.

As can be seen from the above description, the output of the integrator INTEG, that is, the output VCG of the averaging circuit MEAN is the absolute value | Vout1 | of the output of the gain control circuit GC1.
The voltage variable resistor RV114 is controlled so that the average voltage of the reference voltage VmEAN approaches the reference level of the reference average voltage VPMEAN.

Further, according to the equation (6), in the case of a sine wave signal, the reference voltage VPMEAN is equivalent to the reference peak level VP, so that the output Vout1 of the gain control circuit GC1 has a constant level Vp.

Therefore, equation (4) can be expressed as follows: Vout1 = Vin · (G1) = Vp (8) That is, G1 = (Vp / Vin) (9)

In the gain control circuit GC2 shown in FIG.
1 is an input terminal, 126 is an output terminal, RV124 is a voltage variable resistor, R123 is a resistor, and AMP125 is an operational amplifier.

Here, the voltage variable resistor RV124 is a voltage variable resistor having the same characteristics as the voltage variable resistor RV114 of the gain control circuit GC1, that is, showing the same resistance value for the same applied voltage. The operational amplifier AMP125 is an operational amplifier A
Operational amplifier having the same gain as MP115, resistor R123
Has the same resistance value as the resistor R113.

The operation is the same as that of the gain control circuit GC1, and the input signal V121 of the gain control circuit GC2 is a voltage variable resistor RV having one end connected to the common potential point Vcom and one end connected to the common potential point Vcom.
The voltage is divided at 124 and applied to the input terminal 122 of the operational amplifier AMP125, and the gain of the operational amplifier AMP125 (G1
25) and is output to the output terminal 126.

The output signal V126 at the output terminal 126 of the gain control circuit GC2 is

[0058]

(Equation 8)

## EQU5 ## Here, G2 is a gain control circuit GC
A gain of 2.

The output terminal 12 of the gain control circuit GC2
6 is connected to the input terminal 131 of the amplifier circuit DFAMP.

In FIG. 1, the amplification circuit DFAMP comprises an operational amplification circuit having a gain of G135. Also,
In FIG. 2, 131 to 132 are input terminals, 136 is an output terminal, and an input terminal 131 is an operational amplifier AMP13.
5, the input terminal 132 is a non-inverted input terminal, and the output terminal 136 is an output terminal.

Further, the output terminal 1 of the amplifier circuit DFAMP
36 is connected to the input terminal 121 of the gain control circuit GC2.

The gain control circuit GC2 and the amplifier circuit DF shown in FIG.
In connection with the AMP, the output V13 of the amplifier circuit DFAMP is
6 passes through the gain control circuit GC2 expressed by the equation (11), the output voltage becomes V126, and the amplifier circuit DFAM
Negative feedback is applied to the input terminal 131 of P, that is, the inverting input terminal 131 of the operational amplifier AMP135. On the other hand, the input signal Vin input to the input terminal 132 is
The input terminal 135 of the AMP, that is, the non-inverting input terminal of the operational amplifier 135 is input. This gain control circuit GC2
The connection between the amplifier and the amplifier circuit DFAMP is a general negative feedback circuit, and the following (12) and (13) are established.

V136 = (Vin−V126) · G135 (12) V126 = V136 · G2 (13) where G2 is represented by (11).

From the above equation,

[0066]

(Equation 9)

Here, if G135≫1, V136 = Vin · (1 / G2) (15) As described above, by setting the gain G135 of the amplifier circuit DFAMP to a sufficiently large value, the negative feedback circuit The opposite characteristic of the gain of the gain control circuit GC2 can be obtained. The gain G135 can be realized by a normal operational amplifier.

Here, the gain control circuit GC1 and the gain control circuit GC2 are the same circuit. As shown in FIG. 1, the output VCG of the averaging circuit MEAN is applied to the control terminals GC1 and GC2, so that the RV114 The resistance of the RV 124 is equal, and from the equations (5) and (11), G1 = G2 (16) The equations (16) and (9) are substituted into the equation (15), and V136 = Vin · (1 / G2) ) = Vin · (1 / G1) = Vin · {1 / (Vp / Vin)} (17) When the above equation is rewritten,

[0069]

(Equation 10)

Is obtained. Here, V136 is the output terminal OUT
Since Vout is Vout, Vout = V136, and

[0071]

[Equation 11]

Is obtained.

In the above equation (19), since the exponent is 2, V
in / Vp <1, ie, input signals smaller than Vp are attenuated, and Vin / Vp> 1, ie, input signals larger than Vp, are amplified.

That is, the input signal is expanded by the square characteristic of the equation (19).

FIG. 3 shows an example of the elongation characteristic of the present invention (1).
9) A graph of the equation, which is shown in logarithmic representation.
The vertical axis represents 20 · log (Vout / Vp), that is, an output signal, and the horizontal axis represents 20 · log (Vin / Vp), that is, an input signal. The unit is decibel [DB].

When Vin = Vp, Vout = Vp, and X
The scales of the axis and the Y axis are both 0 [DB].

In FIG. 3, a straight line A represents the elongation characteristic with a slope of 2 in equation (19).

The straight line B and the straight line C are added for easy understanding.

A straight line B is obtained by directly converting the input signal Vin without converting it.

The straight line C represents the output Vou of the gain control circuit GC1.
This shows t1 and indicates that it is one constant output level Vp described in the equation (8).

As described above, the straight line A in FIG. 3 is obtained by amplifying or attenuating the straight line B indicating the input signal level by the gain control circuit GC1 to obtain a straight line C having one constant output level Vp, thereby obtaining the gain G1. At the same time, a linear A, that is, an extended output signal can be extracted by attenuating or amplifying the gain G1 by the negative feedback operation of the amplifier circuit DFAMP and the gain control circuit GC2 for the input signal. It is.

FIG. 4 is a circuit diagram of the gain control circuit GC2 and the amplifier circuit DFAMP shown in FIG.
That is, the operational amplifier 12 of the gain control circuit GC2 in FIG.
5 is omitted.

In FIG. 4, GC3 is a resistor R153,
Gain control circuit including voltage variable resistor RV154, DFA
MP is an amplification circuit including an operational amplifier AMP165 and an attenuation circuit ATT, and the attenuation circuit ATT includes a resistor R16
2. It consists of a resistor R161.

First, it is shown below that the configuration shown in FIG. 4 can be obtained by modifying the equations (12) and (13) representing the relationship between the gain control circuit GC2 and the amplifier circuit DFAMP in FIG.

Equation (12) representing the relationship between the input signal Vin and the output signal V136 of the amplifier circuit DFAMP is modified as follows.

[0086]

(Equation 12)

Is obtained.

On the other hand, the input signal V13 of the gain control circuit GC2
In equation (13) expressing the relationship between 6 and the output signal V126, V126 = V136 · G2, and both sides are divided by G125, and rewritten as follows.

[0089]

(Equation 13)

From (12) and (13), (12) 'and (13)' were obtained.

First, the first term of the equation (12) 'is that the input signal Vin is attenuated by 1 / G125 and the operational amplifier AMP
135, the second term of the equation being equivalent to attenuating the output signal V126 of the gain control circuit GC2 by 1 / G125 and inputting it to the inverting input terminal of the operational amplifier AMP135. . Here, the second term of the latter is obtained by the gain control circuit GC2 as shown in the equation (11).
Since the gain has already been amplified by only G125, the operational amplifier AMP125 in the gain control circuit GC2 is omitted, and the attenuation of 1 / G125 is omitted.
A connection point 121 between the resistor 123 of the gain control circuit GC2 and the voltage variable resistor RV124 in FIG.
This is equivalent to inputting to the inverted input terminal 35.

The gain G135 'on the right side of the equation (12)'
Is replaced by the gain of the operational amplifier 125.

Further, the left side of the equation (13) 'is the output V126 of the operational amplifier 125 and the gain G1 of the operational amplifier 125.
Since it is divided by 25, it is equal to the input voltage of the operational amplifier 125, that is, the voltage of the connection point 122.

From the equation (11), the right side of the equation (13) 'is
Gain G125 of operational amplifier 125 of gain control circuit GC2
Is omitted, the resistor 123 and the voltage variable resistor RV12
4 is equal to the voltage at node 122.

As described above, from the above (12) '
In (13) ′, the input signal Vin is attenuated by 1 / G125, so that the equation omits the operational amplifier 125 of the gain control circuit GC2.

Further, the calculation is continued to find a condition that is the same as the equation (15).

By substituting (13) ′ into equation (12) ′,

[0098]

[Equation 14]

By rewriting equation (20), the following equation (21) is obtained.
An expression is obtained.

[0100]

(Equation 15)

Here, substituting equation (11) for G2,

[0102]

(Equation 16)

Is as follows.

If the gain G135 'of the operational amplifier is made sufficiently large, equation (22) becomes

[0105]

[Equation 17]

The following is obtained.

The equation (23) is the same as the equation (15) representing the gain of the negative feedback circuit composed of the gain control circuit GC2 and the amplifier DFAMP.

That is, in the gain control circuit GC2 of FIG. 1, the operational amplifier AMP125 is omitted, and the resistance of the gain control circuit GC3 of FIG. 4 is made the same as RV154 = RV124 (24) R153 = R123 (25). As described above, the input signal Vin of the gain control circuit GC3 of FIG. 4 is attenuated by the gain G125 of the operational amplifier AMP125 to become 1 / G125.
Is connected to the attenuating circuit ATT, and its output is connected to the non-inverting input terminal of the operational amplifier 165.

The resistors R161 and R162 of the attenuation circuit ATT
Is as follows.

1 / G125 = R161 / (R161 + R162) (26) That is, by setting (24) to (26), FIG.
The gain control circuit GC2 and the amplifier circuit DFAMP can be replaced with FIG.

Since equation (23) is the same as equation (15), FIG. 5 shows the gain control circuit GC2 and the amplifier circuit DF shown in FIG.
Even if AMP is replaced with FIG. 5, the elongation characteristics are exactly the same as those indicated by the straight line A in FIG.

FIG. 5 shows a specific embodiment of the expansion circuit of the present invention.

This expansion circuit comprises gain control circuits GC1, GC
2. Rectifier circuit REC, averaging circuit MEAN, amplifier circuit D
It consists of FAMP.

The gain control circuit GC2 and the amplification circuit DF
The AMP employs the configuration described with reference to FIG.

In the gain control circuit GC1, IN is a signal input terminal, OUT1 is a signal output terminal, and GCC1 is a control signal input terminal. The input signal Vin is supplied to the signal input terminal IN
Is connected to the drain electrode of the N-channel MOS transistor Tr114 via the resistor R113. Tr1
Is connected to a common potential point Vcom, and the gate electrode of Tr114 is connected to a control signal input terminal GC.
Connect to C1.

The drain electrode of Tr114 is connected to the non-inverting input terminal of operational amplifier AMP115, the output terminal of operational amplifier AMP115 is connected to the inverting input terminal of operational amplifier AMP115 via resistor R112, and further via resistor R111. To the common potential point Vcom.

Here, the characteristics of the N-channel MOS transistor will be described with reference to FIGS. In FIG. 6, the D (drain) terminal of the first electrode and the S (
In the (source) terminal, the G (gate) terminal of the control electrode, and the SUB of the substrate terminal, the S terminal of the second electrode and the S of the substrate terminal
Connect the UB terminal to a common ground. Here, the current flowing through the D terminal of the first electrode is IDS, the voltage between the grounds is VDS, and the voltage between the G terminal of the control voltage and the ground is VG.
S.

The first control voltage VGS is used as a parameter.
FIG. 7 shows the current IDS and voltage VDS characteristics of the D terminal of the electrode. Here, VGS1 to VGS4, Vth (Vth is
The threshold voltage of the MOS transistor is the control voltage VGS, and VGS4>VGS3>VGS2>VGS1> Vt
h. FIG. 7 shows a well-known N-channel type MOS.
In the voltage-current characteristics of the transistor, if VDS increases, the transistor goes from a linear region to a saturation region (constant current region), and the relationship between the voltage VDS and the current IDS becomes non-linear. However, a small area ± Δ centered on VDS = 0V
VDS, ± ΔIDS, fixed control voltage VG
For S, it can be considered that the relationship between VDS and current IDS is linear, that is, it shows a resistance characteristic independent of VDS.

If the resistance between the first electrode and the second electrode of the transistor in this region is Ron, the characteristics shown in FIG. 8 are obtained.
When the control voltage VGS = Vth, Ron becomes infinite, and as the control voltage VGS increases, the resistance Ron decreases. That is, the resistance can be varied by the control signal VGS.

Here, regarding the voltage applied to the resistor Ron,
A description will be given by taking the gain control circuit GC1 of FIG. 5 as an example. As will be described later, the operational amplifier AMP is controlled by the reference voltage VpMEAN.
The output voltage of 115 is limited. Operational amplifier AMP1
15 as Vout1max, the voltage Vin + applied to the non-inverting input terminal + of the operational amplifier AMP115
Is Vin + = Vout1max / (1 + R112 / R111)
Therefore, Vout1max = ± 1 [V], (1 + R112 /
R111) = 100, −0.01 <Vin + <
A small voltage range of 0.01 [V] can be obtained. Vin +
Is equal to the resistance Ron, that is, the voltage applied to the transistor Tr114, and can be operated in the linear region ± ΔVDS described above.

Returning to the description of the specific embodiment of the expansion circuit of the present invention, the gain control circuit GC1 shown in FIG.
Tr114 is a voltage-variable resistor described above. If the resistance is RV114, the output terminal voltage Vout1 of the operational amplifier AMP115 can be calculated in the same manner as in the equation (4).

[0122]

(Equation 18)

It is assumed that

In FIG. 5, the output Vout1 of the gain control circuit GC1 is input to a rectifier circuit REC.

The rectifier circuit REC includes an operational amplifier AMP43
5, resistors R433, R434, constant current sources I436, I4
37, and bipolar transistors Q430, Q431, and Q432 whose collectors are connected to the positive power supply VDD.

One of the output terminals OUT1 of the gain control circuit GC1 is connected to the base of the transistor Q431. The emitter of the transistor Q431 is commonly connected at a connection point 437 to the emitter of the transistor Q432 whose base is connected to the common potential point Vcom, and further connected to the non-inverting input terminal of the operational amplifier AMP435. The constant current I436 is a bias current of the transistors Q431 and 432, and is connected between the negative power supply VSS and the connection point 437.

The output line 439 of the operational amplifier AMP is
It is connected to the output OUT1 of the gain control circuit GC1 through the resistors R434 and R433. A connection point 450 between the resistors R434 and R433 is connected to the base of the transistor Q430. The emitter of the transistor Q430 has an inverting input terminal of the operational amplifier AMP435 and the other end connected to the negative power supply VSS.
To the constant current source I437 connected to the.

With the above connection, the operation of the rectifier circuit REC will be described below.

When the output voltage Vout1 of the gain control circuit GC1 is V
When out1> Vcom, the transistor Q431 conducts,
432, the voltage at the non-inverting input terminal of the operational amplifier AMP435 becomes Vout1-VBE431 (29), where VBE431 is the voltage drop between the base and the emitter of the transistor Q431.

The output of the operational amplifier AMP435 is
Since the resistor R434 and the base and the emitter of the transistor Q430 are connected to the inverting input terminal of the operational amplifier AMP435, a negative feedback operation is performed. Therefore, the inverting input terminal voltage of the operational amplifier AMP435 is equal to the above (2)
It becomes equal to the non-inverting input terminal voltage (Vout1-VBE431) in the expression 9). Therefore, the connection point 45 between the resistors R434 and R433
If the base-emitter voltage of the transistor Q430 is VBE430, the voltage V450 of 0 is as follows: V450 = Vout1−VBE431 + VBE430 (30) Here, if the current values of the constant currents I436 and I437 are made equal, VBE430 = VBE431 (31), so that the voltage V450 at the connection point 450 becomes V450 = Vout1 (32), which is equal to the output voltage Vout1 of the gain control circuit GC1. Therefore, the voltage between both ends of the resistor R433 becomes 0,
Since no current flows, the voltage drop across the resistor R434 also becomes zero. That is, the output voltage of the operational amplifier AMP435 becomes equal to the output voltage Vout1 of the gain control circuit GC1.

That is, when Vout1> Vcom (= 0), the rectifier circuit REC operates as a buffer circuit that outputs the input voltage as it is.

Conversely, when Vout1 <Vcom (= 0), the transistor Q431 is turned off and the transistor Q432 is turned on. Therefore, if the voltage drop between the base and the emitter of the transistor Q432 is VBE432, the non-inverting input of the operational amplifier AMP435 is obtained. The voltage at the terminal is Vcom-VBE432 = -VBE432 (33). As described above, the resistor R434 and the transistor Q4
Operational amplifier AMP4 through base-emitter of 30
Due to the negative feedback operation of 35, the voltage at the inverting input terminal of the operational amplifier AMP435 becomes equal to the non-inverting input terminal voltage −VBE432 (34) in the equation (33). Therefore, the voltage V450 at the connection point 450 between the resistors R434 and R433 is V450 = -VBE432 + VBE430 (35). Here, since the current values of the constant currents I436 and I437 are equal and VBE432 = VBE430 (36), the voltage V450 at the node 450 becomes V450 = 0 (37). As a result, a current (−Vout1 / R433) flows from the connection point 450 toward the output terminal OUT1 of the gain control circuit GC1. This current is equal to the current flowing through the resistor R434, and the output voltage of the operational amplifier AMP435 is a positive output of (−Vout1 / R433) · R434 (38). Here, if R433 = R434 (39), the output voltage VREC of the operational amplifier AMP435 becomes -Vout1 (40). That is, when Vout1 <Vcom (= 0), the rectifier circuit REC operates as a circuit that inverts and outputs an input voltage. The above operation is shown in FIGS. 9A to 9C.

The waveform Vout1 of FIG. 9A is a full-wave rectified waveform of FIG. 9B in which the negative voltage is turned to the positive side, that is, VREC = | V
out1 |.

The output of the rectifier REC is averaged by an averaging circuit M
Input to the EAN input terminal IMEAN.

As described above, the averaging circuit MEAN has an input terminal INMEAN, a reference voltage input terminal INVpMEAN, an output terminal OMEAN, an analog subtractor SUB, and an integrator INTE.
Consists of G.

Further, the analog subtractor SUB includes a resistor R
444, R445, and an operational amplifier AMP446,
The integrator INTEG includes a resistor R447 and a capacitor C44.
8, consisting of an operational amplifier AMP449.

In the analog subtractor SUB, the resistance R4
44 is connected between the input terminal IMEAN and the inverting input terminal 442 of the operational amplifier AMP446, the resistor R445 is connected between the inverting input terminal 442 and the output 443 of the operational amplifier AMP446, and the reference voltage input terminal INVpMEAN is connected to the operational amplifier AMP446. To the non-inverting input terminal 441.

In the integrator INTEG, the resistance R447
Is connected between the output terminal 443 of the operational amplifier AMP446 and the inverting input terminal 451 of the operational amplifier AMP449, and the capacitor C448 is connected between the output terminal OMEAN and the inverting input terminal 451 of the operational amplifier AMP449.

The reference voltage input terminal INVpMEAN is connected to the non-inverting input terminal 441 of the operational amplifier AMP446 and the non-inverting input terminal 452 of the operational amplifier AMP449.

Hereinafter, the operation of the averaging circuit MEAN will be described.

In the analog subtractor SUB, R444
= R445, the output voltage V of the rectifier circuit REC
A voltage obtained by subtracting the voltage VpMEAN of the reference voltage input terminal from REC is inverted with respect to VpMEAN and output to the terminal 443. Assuming that this voltage is V443, V443 = (VpMEAN− (VREC−VpMEAN)) (41) = 2 · VpMEAN−VREC

Output terminal 443 of analog subtractor SUB
Is input to the integrator INTEG.

In the integrator INTEG, the output of the analog subtractor SUB is used to calculate the voltage VpM of the reference voltage input terminal.
An error current I ERR obtained by subtracting EAN and dividing by the resistance R447 flows to the capacitor C448. Assuming that this current is IERR, IERR = ｛(2 · VpMEAN−VREC) −VpMEAN) / R447 = (VpMEAN−VREC) / R447 (42)

That is, in the averaging circuit MEAN,
When the output voltage VREC of the rectifier circuit is higher than the reference voltage VpMEAN, an error current IERR flows from the output terminal of the AMP449 of the operational amplifier in a direction passing through the capacitor C448 and the resistor R447, and the voltage of the output terminal OMEAN of the operational amplifier becomes
To rise.

On the other hand, when the output voltage VREC of the rectifier circuit is smaller than the reference voltage VPMEAN, the error current IERR becomes equal to the resistance R4
47, through the capacitor C448, the operational amplifier 4
The voltage flows toward the output terminal 49 and the voltage at the output terminal OMEAN of the operational amplifier 449 drops. As described above, the averaging circuit MEAN can have the function of detecting the level of the analog subtractor SUB in FIG.

Next, the integrator INTEG is connected to the operational amplifier A
It is also a low-pass filter composed of MP449, capacitor C448, and resistor R447. The error current IERR can be averaged by selecting the values of the capacitor C448 and resistor R447 to be longer than the output voltage Vout1 of the gain control circuit.

The above operation will be described with reference to the following equation (43) and FIGS. 9A to 9C.

The output VCG of the averaging circuit MEAN is obtained after a time T, when the output Vout1 of the gain control circuit GC1 is a sine wave signal having a period T, and the initial value of the output terminal voltage VCG of the integrator INTEG is VCG0.

[0149]

[Equation 19]

Is obtained.

In equation (43), the peak value of Vout1 =
In the case of Vp (signal waveform 700 in FIG. 9A, signal waveform 701 in FIG. 9B), from equation (6), one term in equation (43) is 0, and the average of the output VCG is shown in line 702 in FIG. 9C. Constant and does not change.

At the signal level of the peak value of Vout1> Vp (signal waveform 710 in FIG. 9A, signal waveform 711 in FIG. 9B), one item of equation (43)> 0 and the average of output VCG> VCG0
And the voltage VCG at the output terminal OMEAN of the operational amplifier rises as shown by a signal waveform 712 in FIG. 9C.

At the signal level of Vout1 <Vp (signal waveform 720 in FIG. 9A and signal waveform 721 in FIG. 9B), (43)
If one term of the equation <0, then the average of the output VCG <VCG0, and the voltage VCG at the output terminal OMEAN of the operational amplifier falls as shown by the line 722 in FIG. 9C.

Further, the averaging circuit MEAN also functions as an integrator including an operational amplifier AMP449, a capacitor C448, and a resistor R447. The error current IERR is converted into a voltage and integrated into the capacitor C448. Therefore, by integrating when the error signal IERR continues,
The control voltage becomes large, and the control accuracy can be improved.

The control voltage of the voltage variable resistor of the gain control circuit is determined at a point where the average value of the error current IERR becomes 0, as will be described later. There is no need to control the voltage, and the accuracy is determined by the level detection of the averaging circuit MEAN, and there is no need to specifically control the process of the MOS transistor.

In FIG. 5, the output VCG of the averaging circuit MEAN is connected to the control input terminals GCC1 and GC
Input to C2.

Therefore, the output Vout1 of the gain control circuit GC1
Is higher than the reference voltage VpMEAN, the output VCG of the averaging circuit MEAN rises, the resistance V114 of the transistor Tr114 decreases as shown in FIG. 8, and the gain control circuit can be understood from the equation (27). The gain of GC1 decreases, and the output voltage Vout1 decreases.

Conversely, when the average voltage of the output Vout1 of the gain control circuit GC1 is lower than the reference voltage VpMEAN, the output VCG of the averaging circuit MEAN drops and the transistor Tr1
The resistance RV114 of the gain control circuit 14 increases, the gain of the gain control circuit increases, and the output voltage Vout1 increases, as can be seen from equation (27).

As can be seen from the above description, the voltage at the control input terminal is determined at the point where the average value of the error current IERR becomes 0, so that the output Vout1 of the final stage gain control circuit is obtained.
Is controlled so that the average voltage of the reference input terminal voltage becomes a constant level of the reference input terminal voltage VpMEAN.

Further, according to equation (6), in the case of a sine wave signal, the average voltage VpMEAN is equivalent to the reference peak level Vp, so that the output Vout1 of the gain control circuit GC1 has a constant level Vp.

Therefore, equation (27) can be expressed as follows: Vout1 = Vin · (G1) = Vp (44) That is, G1 = (Vp / Vin) (45)

In the gain control circuit GC2 shown in FIG.
1 is an input terminal, 126 is an output terminal, Tr 124 is an MO
The S transistor and R123 are resistors.

Here, MOS transistor Tr124
Is the MOS transistor Tr11 of the gain control circuit GC1.
It is assumed that the resistor R123 has the same characteristics as the resistor R4, that is, the same resistance value for the same applied voltage, and the resistor R123 has the same resistance value as the resistor R113.

In operation, the input signal V121 of the gain control circuit GC2 has a resistor R123 and one of which is connected to the common potential point V.
The voltage is divided by the resistance RV124 of the MOS transistor Tr124 connected to the output terminal com and is output to the output terminal 126.

The output signal V126 of the gain control circuit GC2 is expressed as follows: V126 = V121 · (RV124 / (RV124 + R123)) = V121 · G2 (46) where G2 = (RV124 / (RV124 + R123)) (47) Here, G2 is the attenuation gain of the gain control circuit GC2.

The output of the gain control circuit GC2 is
Output to FAMP.

In FIG. 5, an amplification circuit DFAMP includes an input terminal 131, an input terminal IN, an output terminal 136, and a gain G.
135 operational amplifier AMP135, resistors R131, R1
Consists of 32. The input terminal 131 is connected to the operational amplifier AMP1
35 inverting input terminals. The resistor R131 is connected between the input terminal IN and the non-inverting input terminal of the operational amplifier AMP135, and the resistor R132 is connected between the non-inverting input terminal and the common potential point Vcom. The output terminal of the operational amplifier AMP 135 is connected to the output terminal 136.

Further, the output terminal 1 of the amplifier circuit DFAMP
36 is connected to the input terminal 121 of the gain control circuit GC2.

The gain control circuit GC2 and the amplifier circuit DF shown in FIG.
In connection with AMP, the output terminal 1 of the operational amplifier 135
36 passes through a gain control circuit GC2 represented by the equation (47), and its output V126 is connected to the inverting input terminal 1 of the operational amplifier.
31 has a negative feedback. On the other hand, the input signal Vin is
After being divided by the resistors R131 and R132, the operational amplifier 1
This is a general negative feedback circuit input to a non-inverting input terminal 132 of the LCD.

The following equations (48) and (49) hold.

V136 = {Vin · R131 / (R131 + R132) −V126} · G135 (48) V126 = V136 · G2 (49) Here, G2 is represented by equation (47).

From equations (48) and (49),

[0173]

(Equation 20)

Here, assuming that G135≫1, that is, the gain of the operational amplifier 135 is sufficiently large,

[0175]

(Equation 21)

By rewriting by substituting equation (47) for G2 in the above equation,

[0177]

(Equation 22)

As shown in FIG. 5, since the output VCG of the averaging circuit MEAN is applied to the control terminals GC1 and GC2, the resistances of RV114 and RV124 are equal, and RV114 = RV124 (53) The control circuits GC1 and GC2 and the resistors R123, R131, R13 of the amplifier circuit DFAMP
2 is as follows: R113 = R123 (54) R111 = R131 (55) R112 = R131 (56) From (53) to (56) to (52),

[0179]

(Equation 23)

In the above equation (57), the denominator is equal to G1 in equation (28).

[0181]

(Equation 24)

The output terminal 1 of the amplifier circuit DFAMP
36, the reverse characteristic of the gain control circuit GC1 can be obtained.

Further, substituting equation (9) for G1, = 1 / (Vp / Vin) (58) The above equation (58) can be rewritten as follows.

[0184]

(Equation 25)

In FIG. 5, since Vout = V136,

[0186]

(Equation 26)

In the above equation (60), since the exponent is 2, V
in / Vp <1, ie, input signals smaller than Vp are attenuated, and Vin / Vp> 1, ie, input signals larger than Vp, are amplified.

That is, the input signal is expanded by the square characteristic of the equation (60).

Equations (60) and (19) have the same characteristics, that is, the extension characteristic of the straight line A in FIG. 3 has been obtained.

[0190]

As described above, according to the present invention, the LSI
Therefore, no special process control is required, and a decompression circuit having no variation in characteristics can be realized.

Further, it is possible to handle general analog signals which change positively or negatively around the common potential point Vcom.

Further, since it is not directly influenced by the input voltage Vin, it is possible to realize an extension characteristic with less nonlinear distortion.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a decompression circuit according to the present invention.

FIG. 2 is a diagram showing a conventional decompression circuit.

FIG. 3 is a diagram showing an example of an elongation characteristic according to the present invention.

FIG. 4 is a diagram showing an example of a gain control circuit and DFAMP.

FIG. 5 is a diagram showing a specific example of a decompression circuit according to the present invention.

FIG. 6 illustrates an operation of a MOS transistor.

FIG. 7 illustrates an operation of a MOS transistor.

FIG. 8 illustrates an operation of a MOS transistor.

FIG. 9 is a diagram for explaining the operation of the decompression circuit of the present invention.

[Explanation of symbols]

 GC1 gain control circuit GC2 gain control circuit REC rectifier circuit MEAN averaging circuit DFAMP amplifier circuit

Continuation of front page (56) References JP-A-54-17610 (JP, A) JP-A-1-269186 (JP, A) JP-A-1-318308 (JP, A) JP-A-55-104143 (JP, A) , A) JP-A-55-45230 (JP, A) JP-A-55-49010 (JP, A) JP-A-63-107065 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H03G 7/00-11/08 G06G 7/20 H04B 1/64

Claims (1)

(57) [Claims] A first gain control circuit that amplifies and outputs an analog input signal at an amplification factor according to a change in a control signal; a rectifier circuit that rectifies an output of the first gain control circuit; A control signal generating circuit that compares an output of the circuit with a reference voltage and outputs the control signal in accordance with a result of the comparison; the analog input signal as a first input signal;
A differential amplifier that amplifies the difference between the input signal and the second input signal and outputs the expanded analog input signal; and outputs the output of the differential amplifier with an amplification factor according to a change in the control signal. And a second gain control circuit for amplifying and outputting as a second input signal of the differential amplifier.