CN212518924U

CN212518924U - Intermediate frequency gain control circuit for navigation receiver

Info

Publication number: CN212518924U
Application number: CN202021529467.2U
Authority: CN
Inventors: 刘波; 夏景; 陈瑞波
Original assignee: Compass Navigation Jiangsu Communication Technology Co ltd
Current assignee: Compass Navigation Jiangsu Communication Technology Co ltd
Priority date: 2020-07-28
Filing date: 2020-07-28
Publication date: 2021-02-09
Anticipated expiration: 2030-07-28

Abstract

The utility model discloses an intermediate frequency gain control circuit for navigation receiver. The circuit comprises a two-stage cascaded gain amplification chip AD8367, wherein a gain control voltage end of a first-stage gain amplification chip AD8367 is electrically connected with a gain control end of a second-stage gain amplification chip AD8367, and the second-stage gain amplification chip AD8367 provides gain control voltage for the first-stage gain amplification chip AD8367, so that the first-stage gain amplification chip AD8367 works in a VGA state, the second-stage gain amplification chip AD8367 works in an AGC state, the gain ratio of the two-stage amplifier can be regulated and controlled through a voltage division circuit, and the linearity and the high gain balance of the whole amplification circuit are further ensured.

Description

Intermediate frequency gain control circuit for navigation receiver

Technical Field

The utility model relates to a navigation positioning field especially relates to an intermediate frequency gain control circuit for navigation receiver.

Background

An intermediate frequency gain control circuit of a navigation receiver usually faces the problem of nonlinearity caused by high gain and adverse effects such as noise coefficient increase and harmonic generation, so that comprehensive consideration needs to be given to gain control, and signals still keep good characteristics without distortion in the gain amplification process.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the main technical problem who solves provides an intermediate frequency gain control circuit for navigation receiver, linear distortion, harmonic control scheduling problem that appear in the gain control of the intermediate frequency circuit among the solution navigation receiver prior art.

For solving above-mentioned technical problem, the utility model discloses a technical scheme provide an intermediate frequency gain control circuit for navigation receiver, including the cascaded gain amplifier chip AD8367 of two-stage, wherein first order gain amplifier chip AD 8367's gain control voltage end and second level gain amplifier chip AD 8367's gain control end electric connection, provide gain control voltage to first order gain amplifier chip AD8367 by second level gain amplifier chip AD8367 to make first order gain amplifier chip AD8367 work in the VGA state.

Preferably, the gain control terminal DETO of the second stage gain amplification chip AD8367 is electrically connected to the gain control voltage terminal thereof, and the gain control terminal of the second stage gain amplification chip AD8367 is also electrically connected to a voltage control capacitor and then grounded, the voltage control capacitor integrates the current output by the gain control terminal of the second stage gain amplification chip AD8367 to generate a control voltage, and the gain control voltage terminal of the second stage gain amplification chip AD8367 is gain-controlled and operated in an AGC state.

Preferably, a first voltage dividing resistor is connected in series between the gain control end of the second-stage gain amplifying chip AD8367 and the gain control voltage end of the first-stage gain amplifying chip AD8367, and the gain control voltage end of the first-stage gain amplifying chip AD8367 is also electrically connected to the second voltage dividing resistor and then grounded.

Preferably, the first voltage-dividing resistor is 38k ohms and the second voltage-dividing resistor is 15k ohms.

Preferably, the signal input ends of the first-stage gain amplification chip AD8367 and the second-stage gain amplification chip AD8367 are electrically connected with a filter network.

Preferably, the filter network includes a filter inductor and a filter capacitor, the filter inductor and the filter capacitor are both electrically connected to the signal input terminal, and the other end of the filter capacitor is grounded.

The utility model has the advantages that: the utility model discloses an intermediate frequency gain control circuit for navigation receiver includes the cascaded gain amplifier chip AD8367 of two-stage, wherein first order gain amplifier chip AD 8367's gain control voltage end is connected with second gain amplifier chip AD 8367's gain control end electricity, provide gain control voltage to first order gain amplifier chip AD8367 by second gain amplifier chip AD8367, thereby make first order gain amplifier chip AD8367 work at the VGA state, second gain amplifier chip AD8367 work is at the AGC state, and can also regulate and control the gain ratio of these two-stage amplifiers through bleeder circuit, and then guarantee whole amplifier circuit's linearity and high gain's balance.

Drawings

Fig. 1 is a circuit diagram of an embodiment of an if gain control circuit for a navigation receiver according to the present invention.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described in more detail with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It is to be noted that, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Fig. 1 shows a circuit diagram of an embodiment of the intermediate frequency gain control circuit for a navigation receiver according to the present invention. In fig. 1, the circuit includes a two-stage cascaded GAIN amplifier chip AD8367, wherein a GAIN control voltage terminal GAIN of the first stage GAIN amplifier chip AD8367 is electrically connected to a GAIN control terminal DETO of the second stage GAIN amplifier chip AD8367, and the second stage GAIN amplifier chip AD8367 provides a GAIN control voltage to the first stage GAIN amplifier chip AD8367, so that the first stage GAIN amplifier chip AD8367 operates in a VGA state, that is, in a voltage control GAIN amplifier state.

Preferably, the GAIN control terminal DETO of the second stage GAIN amplifying chip AD8367 is electrically connected to the GAIN control voltage terminal GAIN thereof, and the GAIN control terminal DETO of the second stage GAIN amplifying chip AD8367 is further electrically connected to a voltage control capacitor C1 and then grounded, the voltage control capacitor C1 integrates the current output from the GAIN control terminal DETO of the second stage GAIN amplifying chip AD8367 to generate a control voltage, and performs GAIN control on the GAIN control voltage terminal GAIN of the second stage GAIN amplifying chip AD8367, and operates in an AGC state, that is, in an automatic GAIN control state.

Through the cascade mode of the two gain amplification chips AD8367, although the input signal at the first stage has a large fluctuation range, the input signal with the fluctuation range of 80dBm can be effectively amplified and stably output through the AGC of the second stage chip.

Preferably, a first voltage dividing resistor R1 is connected in series between the GAIN control terminal DETO of the second stage GAIN amplifier chip AD8367 and the GAIN control voltage terminal GAIN of the first stage GAIN amplifier chip AD8367, and the GAIN control voltage terminal GAIN of the first stage GAIN amplifier chip AD8367 is also electrically connected to the second voltage dividing resistor R2 and then grounded.

The gain of the first-stage amplification and the gain of the second-stage amplification can be regulated and controlled by reasonably setting the resistance values of the divider resistors, and the smaller the ratio of the first-stage gain to the second-stage gain is, the higher the gain of the first-stage amplifier is, and when a high-power signal is input, the self-excitation phenomenon can be caused. In addition, harmonic distortion problems also arise. For this, the ratio of the first-stage gain to the second-stage gain is controlled reasonably. Preferably, the ratio is determined by the first voltage dividing resistance and the second voltage dividing resistance, namely: the gain ratio is R1/(R1+ R2).

Preferably, the first divider resistor R1 is 38k ohms and the second divider resistor R2 is 15k ohms. The corresponding gain ratio is 15/53-0.72.

Preferably, the filter network includes a filter inductor and a filter capacitor, the filter inductor and the filter capacitor are both electrically connected to the signal input terminal, and the other end of the filter capacitor is grounded. The filter inductance is 120nH, and the filter capacitance is 5 pF.

Therefore, the utility model discloses an intermediate frequency gain control circuit for navigation receiver includes the cascaded gain amplifier chip AD8367 of two-stage, wherein first order gain amplifier chip AD 8367's gain control voltage end and second level gain amplifier chip AD 8367's gain control end electricity are connected, provide gain control voltage to first order gain amplifier chip AD8367 by second level gain amplifier chip AD8367, thereby make first order gain amplifier chip AD8367 work in the VGA state, second level gain amplifier chip AD8367 work is in the AGC state, and can also regulate and control the gain ratio of these two-stage amplifiers through bleeder circuit, and then guarantee whole amplifier circuit's linearity and high gain's balance.

The above only is the embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structure changes made in the specification and the attached drawings or directly or indirectly applied to other related technical fields are included in the same principle as the present invention.

Claims

1. The intermediate-frequency gain control circuit for the navigation receiver is characterized by comprising a two-stage cascaded gain amplification chip AD8367, wherein a gain control voltage end of a first-stage gain amplification chip AD8367 is electrically connected with a gain control end of a second-stage gain amplification chip AD8367, and the second-stage gain amplification chip AD8367 provides gain control voltage for the first-stage gain amplification chip AD8367, so that the first-stage gain amplification chip AD8367 works in a VGA state.

2. The if gain control circuit of claim 1, wherein the gain control terminal DETO of the second stage gain amplifier chip AD8367 is electrically connected to the gain control voltage terminal thereof, and the gain control terminal of the second stage gain amplifier chip AD8367 is further electrically connected to a voltage control capacitor and then grounded, and the voltage control capacitor integrates the current output from the gain control terminal of the second stage gain amplifier chip AD8367 to generate the control voltage, so as to perform gain control on the gain control voltage terminal of the second stage gain amplifier chip AD8367 and operate in the AGC state.

3. The IF gain control circuit for a navigation receiver of claim 2, wherein a first voltage divider resistor is connected in series between the gain control terminal of the second stage AD8367 and the gain control voltage terminal of the first stage AD8367, and the gain control voltage terminal of the first stage AD8367 is further electrically connected to the second voltage divider resistor and then grounded.

4. The if gain control circuit of claim 3 wherein the first divider resistor is 38 kohms and the second divider resistor is 15 kohms.

5. The IF gain control circuit for a navigation receiver according to claim 1, wherein the signal input terminals of the first stage AD8367 and the second stage AD8367 are electrically connected to a filter network.

6. The IF gain control circuit for a navigation receiver as set forth in claim 5, wherein said filter network includes a filter inductor and a filter capacitor, both of which are electrically connected to the signal input terminal, and the other end of said filter capacitor is grounded.