JPH0119289B2 - - Google Patents

Info

Publication number
JPH0119289B2
JPH0119289B2 JP55162279A JP16227980A JPH0119289B2 JP H0119289 B2 JPH0119289 B2 JP H0119289B2 JP 55162279 A JP55162279 A JP 55162279A JP 16227980 A JP16227980 A JP 16227980A JP H0119289 B2 JPH0119289 B2 JP H0119289B2
Authority
JP
Japan
Prior art keywords
transistor
resistors
collector
whose
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55162279A
Other languages
Japanese (ja)
Other versions
JPS5787219A (en
Inventor
Yoshiaki Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP55162279A priority Critical patent/JPS5787219A/en
Publication of JPS5787219A publication Critical patent/JPS5787219A/en
Publication of JPH0119289B2 publication Critical patent/JPH0119289B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G1/00Details of arrangements for controlling amplification
    • H03G1/0005Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers

Landscapes

  • Processing Of Color Television Signals (AREA)
  • Control Of Amplification And Gain Control (AREA)

Description

【発明の詳細な説明】 本発明は入力信号を、制御信号によつて所定の
期間、増幅又は減衰可能となした可変利得制御回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable gain control circuit that can amplify or attenuate an input signal for a predetermined period of time using a control signal.

従来アナログ信号を所定期間制御信号により増
幅又は減衰させる回路としては、先ず前記アナロ
グ信号をタイミング信号によつて所定の期間抜き
取り、これを増幅器にて増幅する構成が採用され
ていた。
Conventionally, as a circuit for amplifying or attenuating an analog signal for a predetermined period of time using a control signal, a configuration has been adopted in which the analog signal is first extracted for a predetermined period using a timing signal and then amplified by an amplifier.

本発明は、可変利得増幅回路をダブル差動型の
増幅回路で構成し、その利得を決定する抵抗の値
を等しく設定することで、抵抗値のバラツキに起
因する利得の変動を除去した新規な可変利得増幅
回路を提供するものである。
The present invention is a novel system in which the variable gain amplifier circuit is configured with a double differential amplifier circuit, and the values of the resistors that determine the gain are set equally, thereby eliminating fluctuations in gain caused by variations in the resistance values. A variable gain amplifier circuit is provided.

以下図面に従つて本発明を説明すると、第1図
は本発明の可変利得増幅回路のブロツク図、第2
図は同回路の一実施例、第3図イ,ロ,ハは第2
図の各部波形図、第4図は制御信号のレベルが低
いときの第2図の等価回路、第5図は制御信号が
高いときの第2図の等価回路、第6図は制御信号
の極性と反転した出力を得る場合の一実施例、第
7図イ,ロ,ハは第6図における各部波形図、第
8図は機能停止信号端子を備えた本発明回路の実
施例、第9図イ〜ニは第8図の各部波形を示す。
The present invention will be explained below with reference to the drawings. Figure 1 is a block diagram of the variable gain amplifier circuit of the present invention, and Figure 2 is a block diagram of the variable gain amplifier circuit of the present invention.
The figure shows an example of the same circuit, and Figure 3 A, B, and C are the second embodiment.
Waveform diagrams of each part in the figure, Figure 4 is the equivalent circuit of Figure 2 when the level of the control signal is low, Figure 5 is the equivalent circuit of Figure 2 when the control signal is high, Figure 6 is the polarity of the control signal. 7A, 7B, and 7 are waveform diagrams of each part in FIG. 6, FIG. 8 is an embodiment of the circuit of the present invention equipped with a function stop signal terminal, and FIG. A to D show waveforms of various parts in FIG.

図面において、1,2は各々第1及び第2バイ
アス源、3,4は各々第1及び第2差動対、5,
6は第1及び第2負荷、7,8は各々第1及び第
2スイツチング回路、9は波形整形回路、10は
定電流源、11は入力端子、12は制御端子、1
3は出力端子を示す。
In the drawing, 1 and 2 are first and second bias sources, respectively, 3 and 4 are first and second differential pairs, respectively, and 5,
6 are first and second loads, 7 and 8 are first and second switching circuits, 9 is a waveform shaping circuit, 10 is a constant current source, 11 is an input terminal, 12 is a control terminal, 1
3 indicates an output terminal.

第2図は、第1図の一実施回路例を示し、各々
のバイアス源1,2をトランジスタ14,15で
各々の差動対3,4をトランジスタ16,17及
び18,19で、各々のスイツチング回路7,8
をトランジスタ20,21で、波形整形回路9を
トランジスタ22,23で、インピーダンス変換
段をトランジスタ24で、構成した例である。
FIG. 2 shows an example of an implementation circuit of FIG. 1, in which the bias sources 1 and 2 are transistors 14 and 15, and the differential pairs 3 and 4 are transistors 16, 17 and 18, 19, respectively. Switching circuit 7, 8
In this example, the waveform shaping circuit 9 is configured with transistors 22 and 23, and the impedance conversion stage is configured with a transistor 24.

第3図イは、入力端子11に加えられる入力信
号vi、ロは制御端子12に加えられるパルス状と
なした制御信号vc、ハは出力端子13から得ら
れる出力信号voを示す。
3A shows the input signal vi applied to the input terminal 11, b shows the pulsed control signal vc applied to the control terminal 12, and c shows the output signal vo obtained from the output terminal 13.

次に前記制御信号が低レベルのときと高レベル
のときについて説明する。
Next, a description will be given of when the control signal is at a low level and when the control signal is at a high level.

() 制御信号が低レベルの場合 第4図は第2図の等価回路図を示し、第2図に
おいてトランジスタ23のベースが、その立上り
電圧VBE以上に達せずカツトオフ状態、トランジ
スタ14,22は分圧回路25にて所定電位にバ
イアスされてオン状態になり、このとき抵抗26
における電圧降下を充分大きくとつておけば、ス
イツチング回路7のトランジスタ20はオン、2
1はオフとなる。
() When the control signal is at a low level FIG. 4 shows an equivalent circuit diagram of FIG . It is biased to a predetermined potential by the voltage dividing circuit 25 and turns on, and at this time the resistor 26
If the voltage drop at
1 is off.

定電流源用のトランジスタ10の電流IOは全て
トランジスタ20に流れ、トランジスタ21及び
トランジスタ18,19には電流が流れないた
め、この場合トランジスタ16,17のみより成
る差動対を形成し、差動増幅器として動作するこ
とになり、そのときの出力信号電圧vo1は、抵抗
5,6の値R8,R9及びエミツタ抵抗の値R10
R11,R12,R13を次式の如く R8=R9=RC R10=R11=R12=R13=RE とすると vo1=RC/2REvi ……(1) に近似できる。
The current I O of the constant current source transistor 10 flows entirely to the transistor 20, and no current flows to the transistor 21 and the transistors 18 and 19. Therefore, in this case, a differential pair consisting only of the transistors 16 and 17 is formed, and It will operate as a dynamic amplifier, and the output signal voltage vo 1 at that time will be determined by the values R 8 , R 9 of the resistors 5 and 6 and the values R 10 , of the emitter resistance.
If R 11 , R 12 , and R 13 are expressed as follows, R 8 = R 9 = R C R 10 = R 11 = R 12 = R 13 = R E , then vo 1 = R C /2R E vi...(1 ) can be approximated.

但しRE≫re1,hFB≒1とする。 However, R E ≫re 1 and h FB ≒1.

(re1はIE=IO/2のときのトランジスタ17の
エミツタ抵抗、hFBはベース接地電流増幅率を示
す。) () 制御信号が高レベルの場合 第5図は第2図の等価回路図を示し、第2図に
おいて、制御信号vcの波高値がトランジスタ2
2のベース・エミツタ間立上り電圧VBEより充分
大きいとすると、波形整形回路9のトランジスタ
23がオン、トランジスタ22がオフとなり、ト
ランジスタ23のコレクタ電圧はトランジスタ1
4のエミツタ電圧と等しく、又トランジスタ22
のコレクタ電圧は抵抗26における電圧降下がな
いため、ほぼトランジスタ14のエミツタ電圧に
等しくなる。
(re 1 is the emitter resistance of transistor 17 when I E = I O /2, and h FB is the common base current amplification factor.) () When the control signal is at a high level Figure 5 is the equivalent of Figure 2. A circuit diagram is shown, and in Fig. 2, the peak value of the control signal vc is
2, the transistor 23 of the waveform shaping circuit 9 is turned on, the transistor 22 is turned off, and the collector voltage of the transistor 23 is the same as that of the transistor 1.
4 and the emitter voltage of transistor 22
Since there is no voltage drop across the resistor 26, the collector voltage of is approximately equal to the emitter voltage of the transistor 14.

従つて次段のスイツチング回路のトランジスタ
20,21には、それぞれ抵抗27,26を介し
てほぼトランジスタ14のエミツタ電圧に等しい
電圧がベースバイアスとして加わるため、これら
のトランジスタ20,21にはIO/2の電流が流
れることになり、第5図に示すようにトランジス
タ16,17及び18,19の4個のトランジス
タで差動増幅器として動作し、このときの出力信
号電圧vo2は vo2=RC/REvi ……(2) に近似できる。
Therefore, a voltage approximately equal to the emitter voltage of transistor 14 is applied as a base bias to transistors 20 and 21 of the next stage switching circuit via resistors 27 and 26, respectively, so that these transistors 20 and 21 have an I O / As shown in FIG. 5, the four transistors 16, 17 and 18, 19 operate as a differential amplifier, and the output signal voltage vo 2 at this time is vo 2 =R. C / R E vi ...... can be approximated as (2).

但しRE≫re2,hFB≒1とする。 However, R E ≫re 2 , h FB ≒1.

(re2はIE=IO/2のときのトランジスタ17の
エミツタ抵抗、hFBはベース接地電流増幅率を示
す。) 従つて式(1),(2)から端子12に加える制御信号
に応じて出力信号電圧を2段階に変化させること
が可能となる。
(re 2 is the emitter resistance of transistor 17 when I E = I O /2, and h FB is the common base current amplification factor.) Therefore, from equations (1) and (2), the control signal applied to terminal 12 is Accordingly, it becomes possible to change the output signal voltage in two stages.

又このときの出力端子13に現われる直流レベ
ルは、常にVCC−RCIO/2となり、一定となる。
Further, the DC level appearing at the output terminal 13 at this time is always V CC -R C I O /2, which is constant.

次に電圧利得はエミツタ抵抗の値REとコレク
タ抵抗の値RCによつて任意に設定出来るが、特
に4個のエミツタ抵抗の値R10,R11,R12,R13
と、2個のコレクタ抵抗の値R8,R9をそれぞれ
等しく設定すれば、その利得の比は、 V02/V01=2 ……(3) V01/V02=1/2 ……(4) となる。ここで、第(3)及び第(4)式から明らかな様
に、利得を定める抵抗の値がそれぞれ等しい為、
集積回路化などに際して、抵抗値がばらついたと
しても全て相殺されることになり、正確に2倍又
は1/2倍の利得設定を行なうことが出来る。
Next, the voltage gain can be set arbitrarily by the emitter resistance value R E and the collector resistance value R C , but in particular, the four emitter resistance values R 10 , R 11 , R 12 , R 13
If the values of the two collector resistors R 8 and R 9 are set equal, the gain ratio is V 02 /V 01 = 2...(3) V 01 /V 02 = 1/2... (4) becomes. Here, as is clear from equations (3) and (4), since the values of the resistances that determine the gain are equal,
Even if the resistance value varies during integration into an integrated circuit, it will all be canceled out, making it possible to accurately set the gain to 2x or 1/2.

次に第6図は制御信号と反転した出力信号を得
る例で、第1図のスイツチング回路7,8に加わ
る信号をその入力側にて反転した構成で、第6図
における各信号の波形は第7図イ〜ハに示す通り
制御信号vcに対して出力信号電圧voは反転した
状態となる。
Next, FIG. 6 shows an example of obtaining an output signal that is inverted from the control signal.The signal applied to the switching circuits 7 and 8 in FIG. 1 is inverted on the input side, and the waveforms of each signal in FIG. As shown in FIGS. 7A to 7C, the output signal voltage vo is in an inverted state with respect to the control signal VC.

第8図は利得を可変させる機能に加えて、端子
28を設け、入力信号vi(第9図イ、制御信号vc
(第9図ロ)、機能停止信号vST(第9図ハ)を各端
子11,12,28に印加したとき、出力端子1
3からは期間Toでは出力信号voとして停止した
状態の信号が得られる。これはスイツチングトラ
ンジスタ29,30,31が期間Toにオンにな
り、分圧回路25の抵抗32の両端が短絡され
て、トランジスタ22がオフになり、制御信号
vcには無関係に増幅作用が停止することになる。
In addition to the function of varying the gain, Fig. 8 shows a terminal 28 provided with an input signal vi (Fig. 9
(Figure 9B), when the function stop signal v ST (Figure 9C) is applied to each terminal 11, 12, 28, output terminal 1
3, a signal in a stopped state is obtained as the output signal vo during the period To. This is because the switching transistors 29, 30, and 31 are turned on during the period To, the ends of the resistor 32 of the voltage divider circuit 25 are shorted, and the transistor 22 is turned off, so that the control signal
The amplification effect will stop regardless of vc.

以上の様に本発明によれば、極めて簡単な構成
により、利得が可変できる効果が得られ、更に、
前述の構成の如く、差動対トランジスタにより、
そのベースバイアスを同一になし、負荷電流を
IO/2、エミツタ電流をIO/4として動作させて
いるので、従来の如く直流型の電子ボリユームと
して多用されている二重平衡型の差動増幅器で、
その差動対トランジスタの分流比が1対1からず
れた場合の動作点における温度特性の相違に伴う
出力電圧の温度・依存性を未然に防止し得るの
で、温度特性が極めて良い利点も得られる。
As described above, according to the present invention, the effect of variable gain can be obtained with an extremely simple configuration, and further,
As in the above configuration, the differential pair transistors
Make the base bias the same and the load current
Since it is operated with an emitter current of I O /2 and an emitter current of I O /4, it is a double-balanced differential amplifier that is often used as a conventional DC type electronic volume.
Since it is possible to prevent the temperature dependence of the output voltage due to the difference in temperature characteristics at the operating point when the current division ratio of the differential pair transistor deviates from 1:1, it also provides the advantage of extremely good temperature characteristics. .

又前述の実施例では増幅器として説明したが、
これはRC>REなる仮定のもとで動作し、逆にRE
>RCとすれば、電圧利得は1以下になり、減衰
器(圧縮器)としても使用できる。本発明は、カ
ラーテレビ受像機において、バーストゲートパル
スによつて色信号の中のパースト信号のみを増幅
又は圧縮させたい場合、音声増幅回路における電
子ボリウムに最適である。
In addition, although the above embodiment was explained as an amplifier,
This operates under the assumption that R C > R E , and conversely R E
> R C , the voltage gain will be less than 1, and it can also be used as an attenuator (compressor). The present invention is most suitable for an electronic volume in an audio amplifier circuit when it is desired to amplify or compress only a burst signal in a color signal using a burst gate pulse in a color television receiver.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の可変利得増幅回路のブロツク
図、第2図は同回路の一実施例、第3図イ,ロ,
ハは第2図の各部波形図、第4図及び第5図は第
2図の等価回路図、第6図及び第8図は同回路の
他の実施例、第7図イ,ロ,ハは第6図の各部波
形図、第9図イ,ロ,ハ,ニは第8図の各部波形
図を示す。 主な図番の説明、1…第1バイアス源、2…第
2バイアス源、3…第1差動対、4…第2差動
対、5,6…負荷、7…第1スイツチング回路、
8…第2スイツチング回路、9…波形整形回路、
10…定電流源、11…入力端子、12…制御端
子、13…出力端子。
Fig. 1 is a block diagram of the variable gain amplifier circuit of the present invention, Fig. 2 is an embodiment of the same circuit, and Fig. 3 A, B,
C is a waveform diagram of each part of Fig. 2, Figs. 4 and 5 are equivalent circuit diagrams of Fig. 2, Figs. 6 and 8 are other embodiments of the same circuit, and Figs. 7 A, B, and C are 6 shows waveform diagrams of various parts in FIG. 6, and FIGS. 9A, 9B, C, and 2 show waveform diagrams of various parts in FIG. Explanation of main figure numbers, 1...first bias source, 2...second bias source, 3...first differential pair, 4...second differential pair, 5, 6...load, 7...first switching circuit,
8... Second switching circuit, 9... Waveform shaping circuit,
10...constant current source, 11...input terminal, 12...control terminal, 13...output terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 ベースが入力端子に接続されると共にコレク
タが第1負荷抵抗に接続される第1トランジスタ
と、ベースがバイアス源に接続されると共にコレ
クタが第2負荷抵抗に接続される第2トランジス
タと、前記第1及び第2トランジスタのエミツタ
間に直列接続された第1及び第2抵抗と、ベース
が前記入力端子に接続されると共にコレクタが前
記第1トランジスタのコレクタに接続される第3
トランジスタと、ベースが前記バイアス源に接続
されると共にコレクタが前記第2負荷抵抗に接続
される第4トランジスタと、前記第3及び第4ト
ランジスタのエミツタ間に直列接続された第3及
び第4抵抗と、前記第1及び第2抵抗の接続点と
前記第3及び第4抵抗の接続点にそれぞれコレク
タが接続され、エミツタが共通接続された第1及
び第2スイツチングトランジスタと、該第1及び
第2スイツチングトランジスタの共通エミツタに
接続された定電流源と、第1レベルの制御信号に
応じて前記第1スイツチングトランジスタのみを
オンさせると共に、第2レベルの制御信号に応じ
て前記第1及び第2スイツチングトランジスタを
オンさせる波形整形回路とを備え、前記第1及び
第2負荷抵抗の値を等しく設定すると共に、前記
第1乃至第4抵抗の抵抗値を等しく設定し、前記
第2負荷抵抗の一端より出力信号を得るようにし
たことを特徴とする可変利得増幅回路。
1 a first transistor whose base is connected to the input terminal and whose collector is connected to the first load resistor; a second transistor whose base is connected to the bias source and whose collector is connected to the second load resistor; first and second resistors connected in series between the emitters of the first and second transistors; and a third resistor whose base is connected to the input terminal and whose collector is connected to the collector of the first transistor.
a fourth transistor whose base is connected to the bias source and whose collector is connected to the second load resistor; and third and fourth resistors connected in series between the emitters of the third and fourth transistors. and first and second switching transistors, each of which has a collector connected to a connection point between the first and second resistors and a connection point between the third and fourth resistors, and whose emitters are commonly connected. A constant current source connected to the common emitter of the second switching transistor turns on only the first switching transistor in response to a first level control signal, and turns on only the first switching transistor in response to a second level control signal. and a waveform shaping circuit that turns on a second switching transistor, and sets the values of the first and second load resistors to be equal, sets the resistance values of the first to fourth resistors to be equal, and sets the resistance values of the first to fourth resistors to be equal, and A variable gain amplifier circuit characterized in that an output signal is obtained from one end of a load resistor.
JP55162279A 1980-11-17 1980-11-17 Variable gain amplifying circuit Granted JPS5787219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55162279A JPS5787219A (en) 1980-11-17 1980-11-17 Variable gain amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55162279A JPS5787219A (en) 1980-11-17 1980-11-17 Variable gain amplifying circuit

Publications (2)

Publication Number Publication Date
JPS5787219A JPS5787219A (en) 1982-05-31
JPH0119289B2 true JPH0119289B2 (en) 1989-04-11

Family

ID=15751448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55162279A Granted JPS5787219A (en) 1980-11-17 1980-11-17 Variable gain amplifying circuit

Country Status (1)

Country Link
JP (1) JPS5787219A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60260217A (en) * 1984-06-06 1985-12-23 Pioneer Electronic Corp Amplifier
FR2642918B1 (en) * 1989-02-09 1995-04-14 Cit Alcatel BROADBAND AMPLIFIER CIRCUIT WITH AUTOMATIC GAIN CONTROL
JP3058087B2 (en) * 1996-06-07 2000-07-04 日本電気株式会社 Variable gain amplifier

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5162753U (en) * 1974-11-09 1976-05-18
JPS55138910A (en) * 1979-04-18 1980-10-30 Hitachi Ltd Amplifying circuit

Also Published As

Publication number Publication date
JPS5787219A (en) 1982-05-31

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