JPH0241929Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field The present invention relates to background art related to signal level control circuits.In audio equipment, etc., a signal level control circuit is provided to control the signal level of an audio signal, etc. in order to adjust the volume. is normal. A conventional example of such a signal level control circuit is shown in FIG. In Fig. 1, an input signal υ _i such as an audio signal is connected to the input terminal IN of an electronic volume circuit ₁ as a voltage dividing means via a capacitor C1.
is supplied to. In the electronic volume circuit 1, N resistors _R11 , _R12 , _R13 ... _R1N are connected in series between the input terminal IN and the ground terminal A-GND.
Analog switches _{S 1 ,} S _{2 ,}
S ₃ ...S _N and one end of S _N+1 are connected to each other.
An analog switch is activated by a control signal generation circuit (not shown) so that one of these analog switches S ₁ to S _N+1 is selectively turned on in response to operation of a volume adjustment operation button (not shown). A control signal is supplied to each control input terminal S ₁ +S _N+1 . The other ends of the analog switches S ₁ to _{S N+1} are connected to the output terminal OUT of the electronic volume circuit 1. A capacitor _C2 is connected between the connection terminal A-GND of the electronic volume circuit 1 and the ground. The ground terminal A-GND is
It is biased to a level obtained by dividing the power supply +B by resistors _R21 and _R22 . The signal led out to the output terminal OUT of the electronic volume circuit 1 is supplied to the base of the transistor _Q1 . Transistor Q ₁
A resistor _R23 is connected between the emitter and ground. Also, a resistor is connected to the collector of transistor _Q1 .
Power +B is supplied via _R24 . A buffer amplifier 2 is formed by the transistor Q ₁ and the resistors R ₂₃ and R ₂₄ , and a signal obtained by amplifying the output of the electronic volume circuit 1 with a gain determined by the resistance ratio of the resistors R ₂₃ and R ₂₄ is sent to the collector of the transistor Q ₁ . is derived. The collector output of this transistor _Q1 is outputted as an output signal _υp via a coupling capacitor _C3 .

In the above configuration, the ground terminal A-GND is
It is biased to a level obtained by dividing the power supply +B by resistors R ₂₁ and R ₂₂ , but this ground terminal A-
GND is AC grounded by capacitor _C2 . Therefore, one of the analog switches S ₁ to _{S N+1}
When the analog switch is turned on, one end of the analog switch that was turned on is connected to the series connection point and the input terminal.
Resistance between IN and the relevant series connection point and ground terminal A-
The input signal υ _i divided by the voltage division ratio determined by the resistance between GND is delivered to the output terminal OUT. At this time, there is an error due to the impedance of capacitor _C2 , but this capacitor
There is no problem in practice by making the C ₂ impedance sufficiently smaller than the resistance value of any of the resistors R ₁₁ to _{R 1N} .

However, when the volume is at its minimum, that is, when analog switch S _N+1 is selectively turned on and the voltage division ratio of electronic volume circuit 1 is maximized, the capacitance of capacitor C ₂ must be increased to obtain sufficient attenuation even in the bass range. It has to be large enough. Therefore, conventional signal level control circuits require this capacitor.
If there are constraints on the capacitance of C ₂ due to cost, shape, etc., a sufficient amount of attenuation cannot be obtained and the input signal υ _i leaks to the output terminal OUT.

Summary of the invention Therefore, an object of the invention is to provide a signal level control circuit that can increase the amount of signal attenuation when the volume is at its minimum without using a large capacity capacitor.

The signal level control circuit according to the present invention is
The amplifying means for amplifying the output of the voltage dividing means for voltage dividing an input signal has at least two loads connected in series between the controlled output terminal of the active element and a predetermined potential point, and the series connection point of these at least two loads. The configuration includes means for connecting the reference potential point of the voltage dividing means in an alternating current manner.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 8.

In FIG. 2, an electronic volume circuit 1, capacitors C ₁ to C ₃ , transistor Q ₁ , and resistors R ₂₁ to _{R 24}
are connected in the same way as the circuit in FIG. However, in this example, a resistor _R23 and a resistor _R25 are connected in series between the emitter of the transistor _Q1 and ground. A capacitor C ₄ whose impedance is sufficiently low compared to the resistance value of the resistor R ₂₅ is connected between the series connection point of these resistors R ₂₃ and R ₂₅ and the ground terminal A-GND.
is connected.

In this configuration, when the impedance of capacitor C ₂ is sufficiently small compared to the resistance value of resistor R ₂₅ , the signal current of input signal υ _i passes through resistors R ₁₁ to R _1N , and most of it flows through capacitor C ₂ . It then flows to the grounding point. Therefore, the current flowing through the capacitor C ₄ and the resistor R ₂₅ to the ground point is small. Similarly, the input signal υ _i component in the emitter current of transistor Q ₁ passes through resistor R ₂₃ and most of it passes through capacitor C ₄
and flows through C ₂ to the ground point. Therefore, by focusing only on the input signal υ _i , the circuit of FIG. 2 can be replaced with an equivalent circuit as shown in FIG. 3. Furthermore, in the frequency band where the frequency characteristics of the buffer amplifier 2 consisting of the transistor Q ₁ and the resistors R ₂₃ and R ₂₄ are flat, that is, in the frequency band where the impedance of the capacitor C ₄ is sufficiently small compared to the resistance value of the resistor R ₂₃ , The circuit shown in FIG. 2 can be replaced with an equivalent circuit as shown in FIG.

As is clear from Fig. 4, electronic volume circuit 1
Since the reference potential point of the ground terminal A-GND of the electronic volume circuit 1 and the reference potential point of the input of the buffer amplifier 2 match, the capacitor
The voltage generated across _C2 is no longer added to the audio signal and amplified, and the amount of attenuation becomes extremely large when the volume is at its minimum.

Note that the current flowing through capacitor C ₂ is larger than in the circuit shown in Figure 1 by the emitter current of transistor Q ₁ , but the resistance value of resistor R ₂₃ must be kept sufficiently high compared to the impedance of capacitor C ₂ . For example, the voltage generated across the capacitor C ₂ can be made negligibly small compared to the signal voltage of the input signal υ _i of the electronic volume circuit 1.

Furthermore, when the resistance value of resistor R ₂₅ becomes no longer large enough compared to the impedance of capacitor C ₂ , the input signal current begins to flow through capacitor C ₄ , and the voltage across capacitor C ₄ increases. arise. Then, the voltage across the capacitor _C4 is added to the audio signal by the buffer amplifier 2 and amplified, so the amount of attenuation at the minimum volume decreases. If capacitor C ₂
When the impedance of R ₂₅ becomes extremely large compared to resistor R 25 and becomes equal when capacitor C ₂ is removed, the amount of attenuation when _the volume is at minimum is
It is almost the same as when the capacity is set equal to the capacity of C ₄ .
At the same time, the impedance between the ground terminal A-GND and the ground becomes the first due to the presence of the resistor _R25 .
The voltage is higher than that in the circuit shown in the figure, and the alternating current voltage generated between the ground terminal A-GND and the ground also becomes large, and the error in the voltage division ratio in the electronic volume circuit 1 becomes large.

Therefore, it is desirable that the resistance value of resistor R ₂₅ be sufficiently large compared to the impedance of capacitor C ₂ . However, in order to prevent the DC operating point from changing significantly, the resistance value of the resistor _R25 must be made sufficiently smaller than the resistance value of the resistor _R23 . However, in order to increase the input impedance of buffer amplifier 2, it is necessary to increase the resistance value of resistor _R23 , so even if the capacitance of capacitor _C4 is small, the resistance value of resistor _R25 is smaller than the impedance of capacitor _C2 . can satisfy the condition that it is sufficiently large. Therefore, the impedance of the capacitor _C4 can be made sufficiently smaller than the resistance value of the resistor _R23 , and the frequency characteristics of the buffer amplifier 2 can be made flat. Furthermore, since the impedance of the capacitor C ₂ is sufficiently small compared to the resistance value of the resistor R ₂₃ at this time, the error in the voltage division ratio of the electronic volume circuit 1 due to the voltage across the capacitor C ₂ can be ignored. Become.

In addition, the attenuation amount when the volume is minimum is the capacitor
Even if the capacitance of C ₂ is doubled, the improvement is only 6 dB, but if the impedance of the capacitor C ₄ is set to 1/10 of the resistance value of the resistor R ₂₅ , an improvement of about 20 dB is possible.

FIG. 5 is a circuit block diagram showing another embodiment of the present invention, in which an electronic volume circuit 1, capacitors C ₁ , C ₂ , C ₄ , resistors R ₂₁ , R ₂₂ , R ₂₃ , and R ₂₅ are connected to a second circuit.
Connected in the same way as the circuit shown. However, in this example, the output of the electronic volume circuit 1 is supplied to the gate of a FET (field effect transistor) _Q2 via a capacitor _C5 . A resistor R ₂₆ is connected between the gate of FETQ ₂ and the series connection point of resistors R ₂₃ and R ₅₅ . Resistor between FETQ ₂ source and ground
R ₂₃ and R ₂₅ are connected in series. Power supply +B is supplied to the drain of FETQ ₂ via a resistor _R24 . Then, the drain output of FETQ ₂ is output as an output signal υ _p via a capacitor C ₃ .

In the above configuration, FETQ ₂ and resistors R ₂₃ to _{R 26}
The buffer amplifier 2 is formed by the circuit shown in FIG. 2, and operates in the same manner as the circuit shown in FIG.

FIG. 6 is a circuit block diagram showing still another embodiment of the present invention, and except for the use of transistors Q ₃ and Q ₄ connected to Darlington in the buffer amplifier 2, other parts are as shown in FIG. 2. The circuit is constructed in the same way as the circuit. It is clear that the same effect as in the circuit of FIG. 2 works in this example as well.

FIG. 7 is a circuit block diagram showing still another embodiment of the present invention, in which the electronic volume circuit 1, capacitors C ₁ and C ₂ , and resistors R ₂₁ and R ₂₂ are connected in the same way as in the circuit of FIG. 2. ing. However, in this example, the output of electronic volume circuit 1 is a capacitor.
It is supplied to the base of the PNP type transistor _Q5 via _C6 . The base of transistor _Q5 is a resistor
It is biased to a level obtained by dividing the power supply +B by R ₂₇ and R ₂₈ . Power supply +B is supplied to the emitter of the transistor _Q5 via resistors ₂₉ , _R30 , and _R31 . A capacitor C ₄ is connected between the series connection point of the resistors R ₂₉ and R ₃₀ and the ground terminal A-GND of the electronic volume circuit 1. A capacitor C ₇ is connected in parallel to the resistor R ₃₀ . Transistor Q ₅
A resistor R ₃₂ is connected between the collector and ground. Then, the collector output of transistor _Q5 is outputted as output signal _υp via capacitor _C3 .

In the above configuration, if the impedance of capacitor C ₄ is made sufficiently smaller than that of resistor R ₂₉ , the same effect as in the circuit of FIG. 2 will work.

FIG. 8 is a circuit block diagram showing still another embodiment of the present invention, which includes an electronic volume circuit 1, a transistor Q ₁ , capacitors C ₁ , C ₂ , C ₄ , and resistors R ₂₁ to
R ₂₅ is connected in the same way as in the circuit of FIG. However, in this example, the electronic volume circuit 1
The ground terminal A-GND of the electronic volume circuit 3,
It is commonly connected to the ground terminals A-GND of 4 and 5. Electronic volume circuits 3, 4, and 5 have the same configuration as electronic volume circuit 1. At the input terminals of electronic volume circuits 1 and 3, capacitors C ₈ ,
Audio signal υ _i of both left and right channels via C ₁
(L), υ _i (R) are supplied. The signals derived to the output terminals OUT of the electronic volume circuits 3 and 1 are sent to buffer amplifiers 6 and 7 for impedance conversion.
Input terminals of electronic volume circuits 4 and 5 via
Supplied to IN. These electronic volume circuits 4,
The signal led out to the output terminal OUT of 5 is supplied to the bases of transistors Q ₆ and Q ₁ . A resistor _R33 is connected between the emitter of the transistor _Q6 and the series connection point of the resistors _{R23 and R25} . transistor Q ₆
A power supply +B is supplied to the collector of the resistor _R34 . The collector outputs of these transistors Q ₆ and Q ₁ are supplied to the bases of transistors Q ₇ and Q ₈ . Transistors Q ₇ and Q ₈ are emitter resistors
Together with _R35 and _R36 , it forms a common collector amplifier. The emitter outputs of these transistors Q ₇ and Q ₈ are output as audio outputs υ _p (L) and υ _p (R) for both left and right channels via capacitors C ₉ and C ₁₀ . Note that a bypass capacitor _C11 for noise prevention is connected between the power supply +B and the ground.

In the above configuration, the separation between the left and right channels in the ultra-low frequency range is degraded, but the single capacitor C ₄ and resistor R ₂₅ are used for the audio signals of both the left and right channels, similar to the circuit shown in Figure 2. This effect works.

Effects of the Invention As detailed above, the signal level control circuit according to the present invention has a reference potential point connected to a predetermined potential point in an alternating current manner, and an active element is connected to the amplifying means for amplifying the output of the voltage dividing means for dividing the input signal. A configuration including at least two loads connected in series between a control output terminal and a predetermined potential point, and means for connecting the series connection point of these at least two loads and a reference potential point of the voltage dividing means in an alternating current manner. Therefore, even if an AC voltage is generated between the reference potential point of the voltage dividing means and the predetermined potential point, this AC voltage can be prevented from being added to the input of the amplifying means, and the attenuation amount when the volume is minimum is can be increased without using a large capacity capacitor. Therefore, according to the present invention, when an attenuator type electronic volume circuit is used as a voltage dividing means with a single power supply, it is possible to prevent input signals from leaking when the volume is at a minimum.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional signal level control circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 and 4 are equivalent circuits of the circuit in Fig. 2. The figures shown in FIGS. 5 to 8 are circuit block diagrams showing other embodiments of the present invention, respectively. Explanation of the symbols of the main parts, 1, 3, 4, 5...Electronic volume circuit, C ₂ , C ₄ ... Capacitor, Q ₁ ,
_Q8 ...Transistor, _R21 to _R36 ...Resistor.

Claims (1)

[Scope of utility model registration request] a voltage dividing means that divides the input signal at a voltage division ratio according to a command; a first connection means that connects a reference potential point of the voltage dividing means and a predetermined potential point in an alternating current manner; and amplifying the output of the voltage dividing means. a signal level control circuit comprising: an active element whose control input terminal is supplied with the output of the voltage dividing means; and a controlled output terminal of the active element and the predetermined potential point. a signal level control comprising at least two loads connected in series therebetween, and second connection means for connecting the series connection point of the at least two loads and the reference potential point in an alternating current manner. circuit.