JPS61168966A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61168966A
JPS61168966A JP942585A JP942585A JPS61168966A JP S61168966 A JPS61168966 A JP S61168966A JP 942585 A JP942585 A JP 942585A JP 942585 A JP942585 A JP 942585A JP S61168966 A JPS61168966 A JP S61168966A
Authority
JP
Japan
Prior art keywords
substrate
layer
semiconductor
gaas
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP942585A
Other languages
Japanese (ja)
Inventor
Yasunobu Nashimoto
梨本 泰信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP942585A priority Critical patent/JPS61168966A/en
Publication of JPS61168966A publication Critical patent/JPS61168966A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736Metallic materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor device having a PHS (plated heat sink) structure with reduced variation of heat resistance in a desirable yield, by forming a second semiconductor layer on a semiconductor substrate and etching the substrate from the bottom face thereof up to the second semiconductor layer. CONSTITUTION:An AlGaAs layer 2, a GaAs buffer layer 3 for forming a GaAs MESFET, and a GaAs active layer 4 are epitaxially deposited on a semi- insulating GaAs substrate 1. The substrate is further provided with an Al Schottky electrode 7, AuGe-Ni source electrode 5 and an AuGe-Ni drain electrode 6. The GaAs substrate 1 is etched from the bottom face thereof with a liquid mixture of ammonia and hydrogen peroxide. Since Al0.4Ga0.6As is hardly etched, the etching effect can be stopped at the layer 2. Therefore, the thickness (t) of the substrate can be controlled as required, by means of appropriately selecting the thicknesses of the Al0.4Ga0.6 layer 2 and the GaAs buffer layer 3. Ti and Au films 8 and 9 are further deposited and an Au plated layer 10 is provided. Thus, a PHS structure can be obtained.

Description

【発明の詳細な説明】 C成業上の利用分野〕 本殆明は半導体装置の製造方法に関し、待に、熱伝導率
の低い化合物半導体を用いた素子において、素子から発
生する熱を効率工く放牧させる部(Plated He
at 8ink)構造の製造方法に関するものである。
Detailed Description of the Invention C. Field of Commercial Application] The present invention relates to a method for manufacturing a semiconductor device. Plated He
The present invention relates to a method of manufacturing a 8ink) structure.

〔従来の技術〕[Conventional technology]

M抵抗の大きな化合物中4本でに素子から発生する熱を
効率しく放牧させることが装置の特性上必要である。符
に果償回路装置の様に素子の集積度が^く熱源が集中し
ている一合で、ディスクリ−)ii置でも高尚カドラン
シスターの様に発熱量の多い場合には、放熱の問題&、
Z瓜要でめ3゜CのためPH8購造と呼ばれる構造、丁
なわら、1iPI抵抗の大きなGaAs 基板をできる
だけ薄くし、そviarmにAu、 Ag、 Cu 等
の金属を数10μm〜100μm程度の厚さに厚メッキ
して、この金属2莫を通して放熱する構造が試みられて
hる。
Due to the characteristics of the device, it is necessary to efficiently dissipate the heat generated from the element in four of the compounds with high M resistance. In cases where the elements are highly integrated and the heat source is concentrated, such as in a cost-compensating circuit device, and when the amount of heat generated is large, such as in the case of a discreet quadrant sister, there is a problem of heat dissipation. &,
The structure is called PH8 fabrication because the temperature is 3°C at Z-shaped.The GaAs substrate with large 1iPI resistance is made as thin as possible, and metal such as Au, Ag, Cu, etc. is made on the substrate with a thickness of several 10 μm to 100 μm. Attempts have been made to construct a structure in which heat is dissipated through this metal by thickly plating it.

従来のPH8構造の形成方法は一般的に下記のとおりで
あった。
The conventional method for forming the PH8 structure was generally as follows.

よす、表面[素子を形成した半導体基板の一面全研磨し
、厚さを100μm i度にする。次いで基或の表面を
エツチングすることtic xって厚さを10〜30μ
m に仕上げる。その俊基板の41k面に金属、例え9
工Agt−30〜100μmの厚さに厚メッキする。
Okay, the surface [The entire surface of the semiconductor substrate on which the element is formed is polished to a thickness of 100 μm. Next, the surface of the base is etched to a thickness of 10 to 30 μm.
Finish to m. Metal on the 41k side of the board, e.g. 9
Agt - Thick plating to a thickness of 30 to 100 μm.

〔発明が屏決し=9とする問題点〕 上述した従来りP HS樽這の形成方法では、基&を薄
くするはに生ずる基板厚さの曲内バラツキが大@−こと
、また、厚さの再現性が恐いことが犬さな問題となって
いる。具体例で示すと、400μmのGaAs基板を裏
面から100μmの厚さまで研磨すると2“φ 径の基
板面内で±10μm程度の厚さのバラツキを生ずる。次
いで硫酸と過酸化水素の混合漱を用いて基板の裏面をエ
ツチングした場合、仕上りの厚さを20μm になる様
にエツチングを行なうとエツチングの除に生ずる厚さの
バラツキに±4μmm度である。したがって研磨とエツ
チング工程での基板面内に卦ける厚さのバラツキに±1
4μmとなり、基板の仕上O厚さと同橿度でのる。上列
で示さルる様に従来、PH84s造り製造工程での乗置
りほきわりて恐く、同−基板面でさえも均一な隔抵抗を
持っlt素子を得ることが^離であった。
[Problems determined by the invention = 9] In the above-mentioned conventional method of forming PHS barrels, there is a large variation in the thickness of the substrate that occurs when the substrate is made thinner. The fear of reproducibility has become a serious problem. To give a specific example, when a 400 μm GaAs substrate is polished from the back side to a thickness of 100 μm, a thickness variation of approximately ±10 μm occurs within the surface of the 2"φ diameter substrate. Next, a mixed slag of sulfuric acid and hydrogen peroxide is used to polish the substrate. When the back side of the substrate is etched to a finished thickness of 20 μm, the variation in thickness due to etching is ±4 μm. ±1 for thickness variation
It has a thickness of 4 μm and has the same roughness as the finished O thickness of the substrate. As shown in the upper row, in the past, it was difficult to obtain an LT element with uniform resistance even on the same substrate surface due to the fear of mounting during the PH84S manufacturing process.

本発明に、以上の問題点を解犬し、均一な薄い半導体基
板が一6aに得られ、P)is構造ζ有する午尋体装瀘
を歩留り良く一通する方法を提供することを目的として
いる。
It is an object of the present invention to solve the above-mentioned problems and provide a method for producing a uniform thin semiconductor substrate having a P)is structure ζ with a high yield. .

〔問題点tS失するための+段〕[+ steps to eliminate problem points tS]

本発明の424体装置の衷造万礪は、半導体素子t−板
表面有する半導体基板を表面から薄膜化して前6d半尋
体累子から発生する熱を前記半導体基板の一面に設けら
れ友金属厚膜へ効率工〈放出する構造の牛導体g装置の
裏造万汰において、半導体基板上に少なくともINIt
(1)前記半導体基板と異なる第2の半導体/#を含む
2/1以上の半導体エピタキシャル層を形成すゐ工程と
、前d己第2の半導体層と前記半導体基板との間のエツ
チング比が大きいエッチング方法1cエリ前記半24本
基板を一面から前記第2の半導体層に達するまでエツチ
ング商去する工程とを會んで構成さf’Lる。
The structure of the 424-body device of the present invention is such that a semiconductor substrate having a semiconductor element T-plate surface is made into a thin film from the surface, and heat generated from the front 6D semicircular body is transferred to a friend metal provided on one surface of the semiconductor substrate. In the back manufacturing of a conductor g device with a structure that emits an efficient process to a thick film, at least INIT is applied to a semiconductor substrate.
(1) A step of forming a 2/1 or more semiconductor epitaxial layer containing a second semiconductor different from the semiconductor substrate, and an etching ratio between the second semiconductor layer and the semiconductor substrate. A large etching method 1c is comprised of a step of etching the 24 halves of the substrate from one side until the second semiconductor layer is reached.

〔作用〕[Effect]

本発明では半導体基板上に所定のエツチング方法に対し
て基板の生得体材料と、エツチング比を大きくとれる第
2の牛導体材料層tエピタキシャル氏長し、その上に素
子を形成するための第3半導体材料@tエピタキシャル
成長する。この基板r用いて、PH8構造を形成すると
上記の第2半等木材料層で基板半導体のエツチングを停
止させることが可能で、基板の裏面研磨及び裏面エツチ
ングで生ずる厚さのバラツキを無くすることができる。
In the present invention, a second conductor material layer is epitaxially formed on a semiconductor substrate by a predetermined etching method to form a second conductive material layer that can have a large etching ratio, and a third layer is formed on the second conductive material layer to form a device. Semiconductor material @t is grown epitaxially. When a PH8 structure is formed using this substrate r, it is possible to stop the etching of the substrate semiconductor at the second half-wood material layer described above, and eliminate the variation in thickness that occurs during back side polishing and back side etching of the substrate. I can do it.

また、第二0名三半導体材料のエピタキシャル層の厚さ
を変えることによって、目出に仕上り基板の、・9さを
決めること゛が可能であり、しかもエピタキシャル層の
厚さの制御性は非常に良く、基板面内で士5チ以下のバ
ラツキに制御可能である。
Furthermore, by changing the thickness of the epitaxial layer of the second semiconductor material, it is possible to precisely determine the thickness of the finished substrate, and the thickness of the epitaxial layer is extremely controllable. It is possible to control the variation within the plane of the substrate to less than 5 cm.

〔実施列〕[Implementation row]

以下、本発明の実施例について、図面を参照して、祝明
する。
Hereinafter, embodiments of the present invention will be congratulated with reference to the drawings.

第1図ta)〜(e)に本発明の一実施例を説明するた
めに工種ノ倶にボした断面図でりる。本実施例でに、午
艶縁性GaAs、4板上にA J xG a □−x 
A s fエピタキシャル成長し、連続してGaAaバ
ッファ一層及びG a A s活性層をエピタキシャル
成長させ、この基板を用いてPkiB構造を有する高出
力GaAsMES F’ET(GaAs 1vleta
l  Sem1conductorfield eff
ect  transistor)t−一通する場合に
りbて脱明する。
FIGS. 1(a) to 1(e) are cross-sectional views of different types of work to explain one embodiment of the present invention. In this example, A J x G a □-x
A s f epitaxial growth is performed, followed by epitaxial growth of a single GaAa buffer layer and a Ga As active layer, and using this substrate, a high power GaAs MES F'ET (GaAs 1vlet
l Sem1 conductor field eff
ect transistor) t-If it is sent once, it will be removed.

まず、第1図ta)に示す様に半絶縁性のG a A 
S基板1上へ周gcaMUcVD(Metal  (J
rgamicChemical  Vapor Dep
osition) 伝2用いてAI。、4Gao、6A
s #i2’f:1μm  極度エピタキシャル成長さ
せる。AlとGa  の組成比μ後工程でのGaAsと
AlxGa1−xAsとのエツチング選択比を大きくす
るためVCAICD組成比O13以上であることが望し
いりで、本実施例でにAlの組成比を0.4とする。次
いで連続してs GaAs 胤bFET  を形成する
ためのGaAsバッフy−M3及びGaAs活圧層4t
−エピタキシャル成長する。
First, as shown in Figure 1 (ta), semi-insulating G a A
GcaMUcVD (Metal (J
rgamicChemical Vapor Dep
position) AI using Den 2. , 4Gao, 6A
s #i2'f: 1 μm Extreme epitaxial growth. In order to increase the etching selectivity between GaAs and AlxGa1-xAs in the subsequent process, it is desirable that the VCAICD composition ratio be O13 or more, and in this example, the Al composition ratio was set to 0. .4. Next, a GaAs buffer y-M3 and a GaAs active pressure layer 4t are successively formed to form a GaAs seed bFET.
-Grow epitaxially.

UaAs(B5Lll:m4iX(i’J高出高尚 a
 A s ME S F E Tt)し或する場合、s
ik不純切として、不純、崖fj7(nがn二lXl0
  Cm  4度で厚さが0.3μm@度でめる。Ga
Asバッファー!曽3ζ高抵M、I曽でMk而面ッチ7
グ諌り厳科仕上り膜厚tがt二10μm程度になる休に
この場合は9μm成量させる。
UaAs(B5Lll:m4iX(i'J Takashi Takashi a
A s ME S F E Tt) and in some cases, s
ik impurity cut, impurity, cliff fj7 (n is n2lXl0
Cm 4 degrees and thickness 0.3 μm @ degrees. Ga
As buffer! So 3ζ high resistance M, I So and Mk facetch 7
In this case, the film is deposited to a thickness of 9 .mu.m when the finished film thickness t is approximately 10 .mu.m.

入に、41図(b)に示す工うに、上記した基板表面に
Alショットキー1極7.AuGe5N1;/−x1甑
5及びA u c) e #N BドL/ (ンt+M
6 k−’fニレツレ周知の真空蒸着とリフトオフ法で
形成する。
First, in the device shown in Figure 41(b), one Al Schottky pole 7. is placed on the surface of the above substrate. AuGe5N1;/-x1 5 and A u c) e #N Bdo L/ (nt+M
6 k-'f Niretsure is formed by the well-known vacuum evaporation and lift-off method.

入VC1基板を薄くするわけであるが、まず0区3基截
1(1)−面を粒度が1200番のアルミナ研磨剤音用
いて型層し、100μm程度の厚さにする。
To make the input VC1 substrate thinner, first, the 0 section 3 bases 1 (1) - surface was molded using an alumina abrasive with a grain size of 1200 to a thickness of about 100 μm.

研磨終f後、4板の磯礪的補Aと基板狭面のデバイスの
沫腫を目的として、ガラス基板を半導体基板のべ面にエ
レクトロンワックスで貼りつけ、アン七ニアと過酸化水
素の混合液でGaAs基板lt兼面からエツチングする
After polishing was completed, a glass substrate was attached to the bottom surface of the semiconductor substrate using electron wax, and a mixture of annealing and hydrogen peroxide was applied to remove the swelling of the four substrates and the device on the narrow side of the substrate. Etch the GaAs substrate from both sides using a liquid.

こりエツチング[−用いるとAIo、4086.6AB
aはとんどエツチングされな贋ため第1図(C)に示す
様にA 1! 0.4 G a o、6A S  層2
でエツチングを1苧止させることかでざる。このとき、
基或の厚さtぼAJo、4Ga、)、6A8512及び
GaAsバッファ一層3の厚さで自由に変えることがで
きる。
Hard etching [- AIo, 4086.6AB
Since a is a fake that has not been etched, as shown in Figure 1 (C), A 1! 0.4 Gao, 6A S layer 2
The only thing that can be done is to stop the etching. At this time,
The basic thickness can be varied freely with the thickness of the 6A8512 and GaAs buffer layer 3.

エツチング後、基板の襄1川にヒートミンクとなるAu
メッキ/ii 10 ”c 501tm橿度形成する。
After etching, Au becomes a heat mink on the substrate.
Plating/II 10"C 501tm radiance formed.

通イAuメッキの前に500A程度の薄いT、j戻8及
び1000A程匿の薄いAu膜9’t一連続してスバッ
タテボジッションする。この11ids及びAu膜9a
Auのt屏メッキを容易に行なうためのものである。
Before the continuous Au plating, a thin T film of about 500 A, a thin Au film 9't of about 1000 A, and a thin Au film 9't of about 1000 A are continuously sputtered. These 11ids and Au film 9a
This is to facilitate the T-screen plating of Au.

最後に基板表−[貼りつけ之ガラス板をカー熱したトリ
クロルチレン中で剥離させると、第1図(d)に示した
PH8構造となる。
Finally, the glass plate attached to the surface of the substrate is peeled off in a heated trichlortyrene, resulting in the PH8 structure shown in FIG. 1(d).

第2図は本発明の徊の実施列にエフ完厄した半導体装置
の断面図である。+:実施飼でに、エツチングの停止層
として団用したA If o、4 G a o、 s 
A a  層2 ’i GaAs  基板1tエツチン
グ除去した後でフッ化水素嵌を用いてエツチングして除
去したもので、不美施例の工#iを行なうと、基板面内
での半$ 9$ 11 ro Jlさtのバラツキの少
ない、丁なわち熱抵抗のバラツキの少ないPH8構造を
有する高出力GaAs MESFET  f歩留り艮く
女定に製造することがでさる。
FIG. 2 is a cross-sectional view of a semiconductor device which has been fully implemented in accordance with the present invention. +: A If o, 4 Ga o, s used as a stop layer for etching during the actual feeding.
A a layer 2'i GaAs substrate 1t etched and removed using hydrogen fluoride filling. 11 A high-output GaAs MESFET having a PH8 structure with little variation in heat resistance, that is, with little variation in thermal resistance, can be manufactured with high yield.

季芙施例でぼディスクリート素子を例にしたが、−41
:発明は果槓回路にも適用できることに明らかである。
I used a discrete element as an example, but -41
: It is clear that the invention can be applied to a fruit circuit as well.

〔発明の効果〕〔Effect of the invention〕

以上説明し之とpす、4+:発明に工れば、均一な博い
半導体基板が容易に1#られ、PH8構造を有する半導
体装置tり函り艮く製造することができる。
As explained above, 4+: If the invention is applied, a uniform wide semiconductor substrate can be easily produced, and a semiconductor device having a PH8 structure can be manufactured in a neat manner.

【図面の簡単な説明】[Brief explanation of drawings]

第1図+a+〜(dlに本発明の一実施例を説明するた
めに工程順にボしfc断m1図、4IJ2図は本発明の
他の実施列にエリ形成された半導体装itの断面図であ
る。 ■・・・・・・GaAS基板、2−− AI! □、4
Ga 0.6AS層、3・・・・・GaAsバッファ一
層、4・・・・・・GaAs活性層、5・・・ ソース
電極、6・・・・・・ドレイン電極、7・・・・・・シ
ョットキー電極、8・・川・Ill 、膜、9・川・・
Au膜、10・・・・・・Auメッキ層。 −2−9,− 代理人 弁理士  内 原   f1゛\鴫−曽□− 第 l 図 第 /I!t $ 2 回
Figures 1+a+ to (dl) are shown in order of process for explaining an embodiment of the present invention. Figures fc sectional m1 and 4IJ2 are cross-sectional views of a semiconductor device IT formed with an edge in another embodiment of the present invention. Yes. ■...GaAS substrate, 2-- AI! □, 4
Ga 0.6AS layer, 3...GaAs buffer layer, 4...GaAs active layer, 5...source electrode, 6...drain electrode, 7...・Schottky electrode, 8・river・Ill, membrane, 9・river・・
Au film, 10... Au plating layer. -2-9, - Agent Patent Attorney Uchihara f1゛\雫-曽□- Part I /I! t $ 2 times

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を表面に有する半導体基板を裏面から薄膜化
して前記半導体素子から発生する熱を前記半導体基板の
裏面に設けられた金属厚膜へ効率よく放出する構造の半
導体装置の製造方法において、半導体基板上に少なくと
も1層の前記半導体基板と異なる第2の半導体層を含む
2層以上の半導体エピタキシャル層を形成する工程と、
前記第2の半導体層と前記半導体基板との間のエッチン
グ比が大きいエッチング方法により前記半導体基板を裏
面から前記第2の半導体層に達するまでエッチング除去
する工程とを含むことを特徴とする半導体装置の製造方
法。
In a method for manufacturing a semiconductor device having a structure in which a semiconductor substrate having a semiconductor element on the front surface is thinned from the back surface and heat generated from the semiconductor element is efficiently released to a thick metal film provided on the back surface of the semiconductor substrate, the semiconductor substrate forming two or more semiconductor epitaxial layers including at least one second semiconductor layer different from the semiconductor substrate thereon;
a step of etching away the semiconductor substrate from the back surface until reaching the second semiconductor layer using an etching method with a high etching ratio between the second semiconductor layer and the semiconductor substrate. manufacturing method.
JP942585A 1985-01-22 1985-01-22 Manufacture of semiconductor device Pending JPS61168966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP942585A JPS61168966A (en) 1985-01-22 1985-01-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP942585A JPS61168966A (en) 1985-01-22 1985-01-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61168966A true JPS61168966A (en) 1986-07-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP942585A Pending JPS61168966A (en) 1985-01-22 1985-01-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61168966A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203924A (en) * 1995-01-27 1996-08-09 Nec Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5370760A (en) * 1976-12-07 1978-06-23 Nec Corp Gas discharge display panel

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5370760A (en) * 1976-12-07 1978-06-23 Nec Corp Gas discharge display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203924A (en) * 1995-01-27 1996-08-09 Nec Corp Semiconductor device

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