JPS61168264A - Manufacture of metal gate mos field effect transistor - Google Patents
Manufacture of metal gate mos field effect transistorInfo
- Publication number
- JPS61168264A JPS61168264A JP860185A JP860185A JPS61168264A JP S61168264 A JPS61168264 A JP S61168264A JP 860185 A JP860185 A JP 860185A JP 860185 A JP860185 A JP 860185A JP S61168264 A JPS61168264 A JP S61168264A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- metal
- silicide
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 23
- 239000002184 metal Substances 0.000 title claims abstract description 23
- 230000005669 field effect Effects 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 29
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は金属ゲー）ＭＯＳ型電界効果トランジスタの製
造方法に関し、特に耐圧の優れた金属ゲ−）ＭＯＳ型電
界効果トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a metal-gauge MOS field effect transistor, and particularly to a method for manufacturing a metal-gauge MOS field effect transistor with excellent breakdown voltage.
従来、半導体集積回路（以下ＩＣと記す）におけるＭＯ
Ｓ型電界効果トランジスタ（以下ＭＯＳＦＥ中と記す）
のゲート電極は不純物を添加した多結晶シリコンで形成
されていた。しかし、近年のＩＣ高密度化に伴う素子微
細化のため、ゲート電極の寸法が減少し、ゲート電極を
従来法で形成していたのでは、ゲート電極の電気抵抗が
増大し電気回路動作速度が減少するという問題が生じ、
これを解決する方法の一つとしてはゲート電極を金属で
形成することが考えられている。Conventionally, MO in semiconductor integrated circuits (hereinafter referred to as IC)
S-type field effect transistor (hereinafter referred to as MOSFE)
The gate electrode was made of polycrystalline silicon doped with impurities. However, due to the miniaturization of elements accompanying the recent increase in IC density, the dimensions of gate electrodes have decreased, and if gate electrodes were formed using conventional methods, the electrical resistance of the gate electrodes would increase and the operating speed of electrical circuits would slow down. The problem arises that the decrease in
One way to solve this problem is to form the gate electrode with metal.
しかし、ゲート電極を金属で形成した場合、ＭＯＳＦＥ
Ｔのゲートと基板間の電気的耐圧が減少するという問題
が生じる。However, if the gate electrode is made of metal, the MOSFE
A problem arises in that the electrical breakdown voltage between the gate of T and the substrate is reduced.
即ち、第４図（ａ）に示すように、ゲート電極１０１を
反応性スパッタ（以下ＲＩＥと記す）により形成した場
合、ゲート電極領域を除いてゲート絶縁ｖ−１０２もエ
ツチングされる。そしてその際ゲート電極下の絶縁膜１
０２の側面１ｏ３はＲＩＥによシ損傷を受ける。そのた
め、このゲート電極側面付近でゲートと基板間の電気的
耐圧が減少する。That is, as shown in FIG. 4(a), when the gate electrode 101 is formed by reactive sputtering (hereinafter referred to as RIE), the gate insulation v-102 is also etched except for the gate electrode region. At that time, the insulating film 1 under the gate electrode
The side surface 1o3 of 02 is damaged by RIE. Therefore, the electrical withstand voltage between the gate and the substrate decreases near the side surface of the gate electrode.
従来法では、ゲート電極を多結晶シリコン、ゲート絶縁
膜をシリコン酸化膜で形成していたので、この耐圧劣化
を回復させるために、ＲＩＥ後熱酸化してゲート電極側
面およびソース・ドレイン領域の基板表面に酸化膜を形
成し、その際酸化が横方向にも進むことを利用してゲー
ト側面付近のゲート酸化膜をわずかに増加させていた。In the conventional method, the gate electrode was formed of polycrystalline silicon and the gate insulating film was formed of silicon oxide film, so in order to recover from this breakdown voltage deterioration, thermal oxidation was performed after RIE to remove the side surfaces of the gate electrode and the substrate in the source and drain regions. An oxide film was formed on the surface, and by taking advantage of the fact that oxidation progressed laterally, the gate oxide film was slightly increased near the sides of the gate.
この状態を示したのが第４図（ｂ）である。しかしゲー
ト電極を金属で形成した場合、このような熱酸化を行う
ことができず、従ってゲートと基板間の耐圧劣化を回復
することができなかった。FIG. 4(b) shows this state. However, when the gate electrode is made of metal, such thermal oxidation cannot be performed, and therefore it has not been possible to recover from the breakdown voltage deterioration between the gate and the substrate.
本発明はかかる欠点を除去し、金属ゲート電極と基板間
の電気的耐圧の高い金属ゲートＭＯＳＦＥＴを提供する
ことを目的とする。An object of the present invention is to eliminate such drawbacks and provide a metal gate MOSFET with high electrical withstand voltage between the metal gate electrode and the substrate.
本発明の金属ゲー）％１’Ｏ８型電界効果トランジスタ
の製造方法は、半導体基板の一主面にゲート絶縁膜を形
成する工程と、該ゲート絶縁膜を形成する工程と、該ゲ
ート絶縁膜上にシリサイド膜を形成する工程と、該シリ
サイド膜上に金属膜を形成する工程と、該金属膜上に第
１のシリコン璧化膜を形成する工程と、前記第１のシリ
コン窒化膜および前記金属膜を選択的に異方性エツチン
グしてＭＯＳ型電界効果トランジスタ構造におけるゲー
ト電極を形成する工程と、全面に第２のシリコン窒化膜
を形成する工程と、該第２のシリコン窒化膜および前記
シリサイド膜を異方性エツチングし、少なくとも前記Ｍ
ＯＳ型電界効果トランジスタ構造におけるソースおよび
ドレイン領域上のゲート絶縁膜を露出させる工程と、前
記ゲート電極側面下方に無比した前記シリサイド膜を酸
化する工程とを含んで構成される。The method for manufacturing a metal oxide (G)%1'O8 type field effect transistor of the present invention includes a step of forming a gate insulating film on one main surface of a semiconductor substrate, a step of forming the gate insulating film, and a step of forming the gate insulating film on the gate insulating film. forming a silicide film on the silicide film; forming a metal film on the silicide film; forming a first silicon oxide film on the metal film; a step of selectively anisotropically etching the film to form a gate electrode in a MOS field effect transistor structure; a step of forming a second silicon nitride film on the entire surface; and a step of forming the second silicon nitride film and the silicide. The film is anisotropically etched, and at least the M
The method includes a step of exposing a gate insulating film on the source and drain regions in an OS type field effect transistor structure, and a step of oxidizing the silicide film below the side surfaces of the gate electrode.
なお、上記シリサイド膜の替わシに多結晶シリコン膜を
使用しても本発明により電気的耐圧の優れた金属ゲー）
ＭＯＳ型電界効果トランジスタを得ることができる。Note that even if a polycrystalline silicon film is used instead of the silicide film described above, the present invention provides a metal game with excellent electrical breakdown voltage.
A MOS field effect transistor can be obtained.
以下、本発明の実施例について、図面を参照して説明す
る。第１図（ａ）〜（ｄ）は、本発明の第１の実施例を
説明するために工程順に示した断面図である。本実施例
は次の工程によ多構成される。Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1(a) to 1(d) are cross-sectional views shown in the order of steps for explaining the first embodiment of the present invention. This embodiment consists of the following steps.
まず、第１図（ａ）に示すよりに１半導体基板２０１上
にゲート絶縁膜２０２を形成し、引続きゲート絶縁膜２
０２に遂次重ねてシリサイド膜２０３、金属膜２０４．
シリコン穿化膜２０５を成長させる。First, as shown in FIG. 1(a), a gate insulating film 202 is formed on one semiconductor substrate 201, and then the gate insulating film 202 is
02, a silicide film 203, a metal film 204 .
A silicon perforation film 205 is grown.
次に、第１図（ｂ）に示すように、シリコン窒化＠２０
５．金属膜２０４を選択的に異方性エツチングし、ゲー
ト電極２０４ａを形成する。次いで、半導体基板の導電
型と反対の導電型の不純物を半導体基板内にイオン注入
しソース・ドレイン領域２０７を形成する。次いで、全
面に第２のシリコン窒化膜２０６を成長させる。Next, as shown in FIG. 1(b), silicon nitride @20
5. The metal film 204 is selectively anisotropically etched to form a gate electrode 204a. Next, impurity ions of a conductivity type opposite to that of the semiconductor substrate are ion-implanted into the semiconductor substrate to form source/drain regions 207. Next, a second silicon nitride film 206 is grown over the entire surface.
次に、第１図（Ｃ）に示すように、シリコン忰化膜２０
６．シリサイド膜２０３を全面異方性エツチングしてソ
ース・ドレイン領域を露出させる。Next, as shown in FIG. 1(C), the silicon film 20 is
6. The entire surface of the silicide film 203 is anisotropically etched to expose the source/drain regions.
なお、このときゲート絶縁膜２０２を全部除去する必要
はなく少なくともソース・ドレイン領域上のゲート絶縁
膜が少なくとも露出していればよい。Note that at this time, it is not necessary to completely remove the gate insulating film 202, and it is sufficient that at least the gate insulating film over the source/drain regions is exposed.
しかるときは、ゲート電極側面には下からゲート絶縁膜
２０２．シリサイド膜２０３．シリコン窒化膜２０６の
順に重なったサイドウオールが形成される。なおこの時
、ゲート電極上面は第１図（ａ）の工程で形成された第
１のシリコン窒化膜２０５で被覆されている。In such a case, a gate insulating film 202 is formed on the side surface of the gate electrode from below. Silicide film 203. A sidewall is formed in which the silicon nitride films 206 are stacked in this order. At this time, the upper surface of the gate electrode is covered with the first silicon nitride film 205 formed in the step of FIG. 1(a).
次に、この状態で熱酸化を行ない、シリサイド膜２０３
および基板表面に第１図（ｄ）に示すような酸化膜２０
８を形成する。Next, thermal oxidation is performed in this state to form the silicide film 203.
and an oxide film 20 as shown in FIG. 1(d) on the surface of the substrate.
form 8.
以上のとお如シリサイド唆の側面及びソース・ドレイン
領域の表面は散化１摸に覆われるので耐圧は向上する。As described above, the side surfaces of the silicide layer and the surfaces of the source/drain regions are covered with a silicide layer, so that the withstand voltage is improved.
また金属膜の側面および上−面はシリコン忰化膜２０６
及びシリコン酸化膜２０５に覆われているので酸化され
ることはない。Also, the side and top surfaces of the metal film are covered with a silicon film 206.
Since it is covered with a silicon oxide film 205, it will not be oxidized.
第２図（ａ）〜（ｅ）は本発明の第２の実施例を説明す
るために工程順に示した断面図である。FIGS. 2(a) to 2(e) are cross-sectional views shown in the order of steps for explaining the second embodiment of the present invention.
まず、第２図（ａ）に示すように、不純物濃度ＩＸ １
０ ｌＳＣｍ−３程度のＰ型シリコン基板３０１に、素
子分離用の厚いシリコン酸化膜３０２を選択酸化法で形
成し、ゲート絶続膜として熱酸化シリコン酸化膜３０３
を数百人形成する。引続きタングステンシリサイド膜３
０４を数百に、タングステンＰ３０５を数千に、シリコ
ン窒化膜３０６を数千人を例えば気相成長法により成長
させる。First, as shown in FIG. 2(a), the impurity concentration IX 1
A thick silicon oxide film 302 for element isolation is formed by selective oxidation on a P-type silicon substrate 301 of about 0 lSCm-3, and a thermally oxidized silicon oxide film 303 is used as a gate continuity film.
Form hundreds of people. Continue with tungsten silicide film 3
04 to several hundreds, tungsten P305 to several thousand, and silicon nitride film 306 to several thousand by, for example, vapor phase growth.
次に、第２図（ｂ）に示すように、フォトリソグラフィ
ーによりゲートをパターニングして、反応性スパッタエ
ツチング（以下ＲＩＥと記す）によシシリコン窒化膜３
０６．タングステン膜３０５をこの順に異方性エツチン
グし、ゲート電極３０５ａを形成する。次いで全面にヒ
素を例えば７０ＫｅＶで５Ｘ１０Ｃｍ 程度イオン注
入し、ソース・ドレイン領域に不純物を注入しソース・
ドレイン不純物注入領域３０７を形成する。Next, as shown in FIG. 2(b), the gate is patterned by photolithography, and the silicon nitride film 3 is etched by reactive sputter etching (hereinafter referred to as RIE).
06. The tungsten film 305 is anisotropically etched in this order to form a gate electrode 305a. Next, arsenic is ion-implanted to about 5×10 cm at 70 KeV over the entire surface, and impurities are implanted into the source and drain regions.
A drain impurity implantation region 307 is formed.
次に、第２図（Ｃ）に示すように、全面にシリコン窒化
膜３０８を例えば気相成長法によシ数千人成長する。Next, as shown in FIG. 2C, several thousand silicon nitride films 308 are grown over the entire surface by, for example, vapor phase growth.
次に、第２図（ｄ）に示すように、ＲＩＥでシリコン彎
化膜３０８．シリサイド膜３０４．ゲート絶縁膜３０３
を異方性エツチングすると、ゲート電極側面に基板３０
１の表面からゲート絶縁膜３０３、シリサイドｌｐ％３
０４． シリコン窒化膜３０８の順に重なったサイド
ウオールが形成される。Next, as shown in FIG. 2(d), the silicon curvature film 308. Silicide film 304. Gate insulating film 303
When etched anisotropically, the substrate 30 is etched on the side of the gate electrode.
From the surface of 1, gate insulating film 303, silicide lp%3
04. A sidewall is formed in which silicon nitride films 308 are stacked in this order.
次に、例えばウエツ）０２雰囲気中１０００℃１０分程
度のアニールを行うと、第２図（ｅ）に示すようなサイ
ドウオール下のシリサイド膜３０４およびソース・ドレ
イン領域３０７の基体表面に熱酸化膜３０９が成長する
。またこの時、イオン注入されたヒ素も活性化するので
ＭＯＳＦＥＴが出来あがる。ただし、その際ゲート電極
３０５のタングステン膜はシリコン♀化膜３０６および
サイドウオールによシ被橿されているので酸化されるこ
とはない。Next, when annealing is performed for about 10 minutes at 1000° C. in a 02 atmosphere, for example, a thermal oxide film is formed on the silicide film 304 under the sidewall and the substrate surface of the source/drain region 307 as shown in FIG. 2(e). 309 grows. At this time, the implanted arsenic is also activated, completing the MOSFET. However, at this time, the tungsten film of the gate electrode 305 is not oxidized because it is covered by the silicon oxide film 306 and the sidewalls.
なお、第１の実施例でものべたとお多シリコン窒化膜３
０８及びシリサイド膜３０４のエツチングにあたっては
ゲート酸化膜３０３は全部エツチング除去される必要は
なく少なくともソース・ドレイン領域上のゲート酸化膜
の表面が露出していればよい。Note that the silicon nitride film 3 described above in the first embodiment is
In etching the gate oxide film 304 and the silicide film 304, the gate oxide film 303 does not need to be completely etched away; it is sufficient that at least the surface of the gate oxide film over the source/drain regions is exposed.
第３図は本発明の第３の実施例により形成され 。FIG. 3 is formed according to a third embodiment of the invention.
た金属ゲートＭＯＳ型電界効果トランジスタの断面図で
ある。FIG. 2 is a cross-sectional view of a metal gate MOS field effect transistor.
第３図においては、シリサイド膜３０４の替わシに多結
晶シリコン膜を用いた場合で、第２図（ｅ）−９二
に示した熱酸化処理工程で多結晶シリコンとタングステ
ンがシリサイド反応を起し、タングステン膜３１０の下
の多結晶シリコンのみが選択的にタングステンシリサイ
ド化されてタングステンシリサイド膜３１１が形成され
たことを示している。In FIG. 3, a polycrystalline silicon film is used instead of the silicide film 304, and a silicide reaction occurs between polycrystalline silicon and tungsten in the thermal oxidation process shown in FIG. 2(e)-92. However, it is shown that only the polycrystalline silicon under the tungsten film 310 was selectively converted into tungsten silicide to form a tungsten silicide film 311.
そしてタングステンシリサイド膜の側面及びソース・ド
レイン領域の表面は酸化膜２０９となシ、第２の実施例
と同様の効果が得られる。Since the side surfaces of the tungsten silicide film and the surfaces of the source/drain regions are not oxide films 209, the same effect as in the second embodiment can be obtained.
以上説明したとおり、本発明においては、金属製ゲート
電極側面に基板表面からゲート絶縁膜、シリサイド膜ま
たは多結晶シリコン膜、絶縁膜の順に重ったサイドウオ
ールを形成し、絶縁膜にはさまれたシリサイド又は多結
晶シリコンのみを選択的に酸化することにより、金属製
グー）！極を電気絶縁性に優れた絶縁膜で被覆すること
により、ゲート・ソースおよびゲート・ドレイン間の耐
圧を大幅に高めることができる。As explained above, in the present invention, a sidewall is formed on the side surface of a metal gate electrode, in which a gate insulating film, a silicide film or a polycrystalline silicon film, and an insulating film are stacked in this order from the substrate surface, and the sidewall is sandwiched between the insulating films. By selectively oxidizing only the silicide or polycrystalline silicon, metallic goo is produced! By covering the poles with an insulating film with excellent electrical insulation, the breakdown voltage between the gate and source and between the gate and drain can be significantly increased.
第１図＜ａ＞〜（ｄ）は本発明の第１の実施例を説明す
るために工程順に示した断面図、第２図（ａ）〜（ｅ）
は本発明の第２の実施例を説明するために工程順に示し
た断面図、第３図は本発明の第３の実施例を説明するた
めの一部工程における断面図、第４図（ａ）、（ｂ）
は従来のＭＯＳ型電界効果トランジスタの製造方法を
説明するために工程順に示した断面図である。
１０１・・・・・・ゲート電極、１０２・・・・・・ゲ
ート絶縁膜、１０３・・・・・・ゲート絶縁膜側面、２
０１・・・・・・牛導体基板、２０２・・・・・・ゲー
ト絶縁膜、２０３・・・・・・シリサイド膜、２０４・
・・・・・金属膜％ ２０４ａ・・・・・・ゲート電
極、２０５・・・・・・シリコン窒化１％、２０６・・
・・・・シＩ）コンミｔ化換、２０７・・・・・・ソー
ス・ドレイン領域、２０８・・・・・・酸化膜、３０１
・・・・・・シリコン基板、３０２・・・・・・シリコ
ン酸化Ｌ３０３・・・・・・シリコン酸化膜、３０４・
・・・・・シリサイド膜、３０５・・・・・・タングス
テン瞑ｓ ３０５ａ・・・・・・ゲート電極、３０６
・・・・・・シリコン窒化膜、３０７・・・・・・ソー
ス・ドレイン領域、３０８・・・・・・シリコン穿化瞑
、３０９・旧・・シリコン酸化膜、３１ｏ・・・・・・
タングステン膜、３１１・・・・・・シリサイド膜。Fig. 1 <a> to (d) are sectional views shown in the order of steps to explain the first embodiment of the present invention, and Fig. 2 (a) to (e)
3 is a sectional view showing the steps in order to explain the second embodiment of the present invention, FIG. 3 is a sectional view showing some steps in order to explain the third embodiment of the invention, ), (b)
1A and 1B are cross-sectional views shown in the order of steps to explain a conventional method of manufacturing a MOS type field effect transistor. 101...Gate electrode, 102...Gate insulating film, 103...Gate insulating film side surface, 2
01... Ox conductor substrate, 202... Gate insulating film, 203... Silicide film, 204...
...Metal film% 204a...Gate electrode, 205...Silicon nitride 1%, 206...
. . . I) Commit conversion, 207 . . . Source/drain region, 208 . . . Oxide film, 301
...Silicon substrate, 302...Silicon oxide L303...Silicon oxide film, 304.
...Silicide film, 305...Tungsten membrane 305a...Gate electrode, 306
...Silicon nitride film, 307...Source/drain region, 308...Silicon perforation, 309 Old...Silicon oxide film, 31o...
Tungsten film, 311...silicide film.
Claims (2)
程と、該ゲート絶縁膜上にシリサイド膜を形成する工程
と、該シリサイド膜上に金属膜を形成する工程と、該金
属膜上に第１のシリコン窒化膜を形成する工程と、前記
第１のシリコン窒化膜および前記金属膜を選択的に異方
性エッチングしてＭＯＳ型電界効果トランジスタ構造に
おけるゲート電極を形成する工程と、全面に第２のシリ
コン窒化膜を形成する工程と、該第２のシリコン窒化膜
および前記シリサイド膜を異方性エッチングし、少なく
とも前記ＭＯＳ型電界効果トランジスタ構造におけるソ
ースおよびドレイン領域上のゲート絶縁膜を露出させる
工程と、前記ゲート電極側面下方に露出した前記シリサ
イド膜を酸化する工程とを含むことを特徴とする金属ゲ
ートＭＯＳ型電界効果トランジスタの製造方法。(1) A step of forming a gate insulating film on one main surface of a semiconductor substrate, a step of forming a silicide film on the gate insulating film, a step of forming a metal film on the silicide film, and a step of forming a metal film on the metal film. forming a first silicon nitride film on the entire surface; selectively anisotropically etching the first silicon nitride film and the metal film to form a gate electrode in a MOS field effect transistor structure; forming a second silicon nitride film, and anisotropically etching the second silicon nitride film and the silicide film to remove at least the gate insulating film on the source and drain regions of the MOS field effect transistor structure. A method for manufacturing a metal gate MOS type field effect transistor, comprising the steps of exposing the silicide film exposed below the side surface of the gate electrode.
した特許請求の範囲第（１）項記載の金属ゲートＭＯＳ
型電界効果トランジスタの製造方法。(2) Metal gate MOS according to claim (1) using a polycrystalline silicon film instead of a silicide film
Method of manufacturing type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP860185A JPS61168264A (en) | 1985-01-21 | 1985-01-21 | Manufacture of metal gate mos field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP860185A JPS61168264A (en) | 1985-01-21 | 1985-01-21 | Manufacture of metal gate mos field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168264A true JPS61168264A (en) | 1986-07-29 |
Family
ID=11697484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP860185A Pending JPS61168264A (en) | 1985-01-21 | 1985-01-21 | Manufacture of metal gate mos field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168264A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0417646A2 (en) * | 1989-09-06 | 1991-03-20 | Kabushiki Kaisha Toshiba | MOS type semiconductor device with a multilayer gate electrode and method for manufacturing the same |
-
1985
- 1985-01-21 JP JP860185A patent/JPS61168264A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0417646A2 (en) * | 1989-09-06 | 1991-03-20 | Kabushiki Kaisha Toshiba | MOS type semiconductor device with a multilayer gate electrode and method for manufacturing the same |
| US5115290A (en) * | 1989-09-06 | 1992-05-19 | Kabushiki Kaisha Toshiba | Mos type semiconductor device and method for manufacturing the same |
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