JPS61168261A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to microminiaturize an element by forming the shape of the element without irregular surface due to polycrystalline silicon crystal particles, thereby enabling to form an element having uniform and good reproducibility. CONSTITUTION:A semiconductor layer is formed on a substrate having an irregular surface, a collector electrode lead 33 is formed, and an insulating film 70 like an oxide film SiO2 or a nitride film SiN is formed by thermal oxidizing on the entire surfaces of vapor phase grown semiconductor layers 30, 31, 31'. Then, the film 70 is entirely etched by anisotropically etching, an insulating film 71 is allowed to remain only on the side wall of the recess, and the other is removed. A nitride layer is formed on the semiconductor layer, a substance layer is further formed thereon, and the surface is flattened. Subsequently, the substance layer and the nitride layer are etched to allow the nitride layer to remain in the recess. With the nitride layer as a mask an oxide layer is formed on the surface of the semiconductor layer. Then, with the oxide as a mask an impurity is implanted to the semiconductor layer.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, which is suitable for application to obtaining a semiconductor device, particularly a semiconductor circuit (RC) using a bipolar transistor. .

[Background technology and its problems]

Conventionally, as a method for isolating circuit elements in an IC, for example, selective oxidation (LOGOS) method has been used. Fifth
The figure shows a sectional view of essential parts of a bipolar transistor IC using this selective oxidation separation method. In the figure, +11 is, for example, a P-type silicon semiconductor substrate, (2) is, for example, an N-type collector buried layer with a high impurity concentration, (3) is a collector region made of an N-type epitaxial growth layer, and (4) is a P-type collector region. A base region, (5) an n-type emitter region, (6) a 5i02 oxide layer formed by selective oxidation, and (7) a collector electrode extraction portion. Although not shown, each area (71, (
4) and (5) each have a metal electrode, for example A7! The electrode is ohmically deposited to form a lead-out electrode. C,B
and E indicate the collector, base, and emitter terminals led out by these electrodes, respectively.

However, this IC has several problems associated with its selective oxidation. One of these is the so-called bird's beak, which occurs during selective oxidation when the oxidation progresses to get under the edge of the mask for selective oxidation.
beak), and the so-called bird's head (
bird's head) occurs, making it impossible to sufficiently increase pattern accuracy and integration density, opening a window in a mask for selective oxidation, and diffusion for selectively forming an emitter region, for example. Mutual alignment with the window opening is required, and in this case, mask alignment accuracy and tolerance including the above-mentioned bird's beak are required. The need for a margin that takes into account the alignment accuracy of the collector impedes the improvement of integration density, and the parasitic capacitance of the collector is greatly affected by the so-called extrinsic region other than its active region (the so-called intrinsic region). Moreover, there are limits to miniaturization of the circuit element area due to these factors.

On the other hand, in order to solve these problems, the present applicant has developed a bipolar transistor IC as shown in FIG.
proposed a manufacturing method for obtaining (see Japanese Patent Application No. 58-92697).

In view of the above points, this manufacturing method solves the problem of isolation between elements caused by the selective oxidation method, and further miniaturizes the elements by forming the collector, base, emitter regions and emitter electrode extraction part with self-alignment lines. enable high performance,
Regarding the manufacturing method of a semiconductor device that can manufacture a highly integrated RC device device, first, as shown in FIG. 6A,
An oxide film (5t (h)
) (22), the channel, this oxide film (2
2), a window is opened and an N-type impurity is diffused into the substrate (21) to form an N-type collector buried layer (23).

Next, as shown in FIG. 6B, after removing the oxide film (22) by etching, a thin oxide film (5iO2) (24) is formed, and the photoresist film deposited on this oxide film (24) is Using (25) as a mask, P-type impurities are implanted to form a buried layer (26) for channel buckwheat.

Next, as shown in FIG. 6C, 5i02
After depositing 1if (27) by CVD (chemical vapor deposition), reactive ion etching (RIE) was performed.
Openings (28) and (29) are formed at required positions of this 5t(h N (27)), that is, at portions corresponding to the active region and the collector electrode lead-out portion, using a method such as the following.

Next, as shown in the sixth diagram, vapor phase growth is performed using SiH4 to form an N-type polycrystalline silicon layer (30) on the 5i02 layer (27) in the openings (28) and (29). N-type single crystal silicon epitaxial N (31) and (3
1') respectively. Polycrystalline silicon jW (30) and epitaxial layer (31) formed by this vapor phase growth
, (31') are approximately equal in thickness, the opening (28
) and (29) are concave.

In this shape, the surface of the substrate is (100) and (
111) can be obtained.

Next, as shown in FIG. 6E, the epitaxial layer (3) is formed in the opening (29) using the photoresist layer (32) as a mask.
1'), and then drive-in diffusion is performed to form a low-resistance collector electrode lead-out part (33
) to form.

Next, as shown in FIG. 6F, photoresist (32)
After removing, a thin oxide film (5i02) (34) and a nitride film (SiN) (35) are deposited by CVD. Note that this thin oxide film (34) has a thickness of 200 mm.
~500 people is appropriate, but it is also possible to manufacture the device without forming it.

Next, as shown in FIG. 6G, photoresist (36)
After the surface of the substrate (21) is planarized by depositing the polycrystalline silicon layer (30), the polycrystalline silicon layer (30) is partially etched by ion milling or reactive ion etching.

Next, as shown in FIG. 6H, a polycrystalline silicon layer (30
) P-type impurities are ion-implanted. Thereafter, the unnecessary polycrystalline silicon layer (30) is removed by etching, leaving the photoresist (36) and the polycrystalline silicon layer (30) in a required area, to form a base electrode extraction portion (38).

Next, as shown in FIG. 6, the oxide film (5i02) (39) is selectively applied to the surface of the polycrystalline silicon layer (30) using the nitride film (35) as a mask. ), the nitride film (35) is removed.

By removing this nitride film (35), a window for forming a base region and an emitter region and a window for extracting the collector electrode (33) can be automatically opened.

Next, as shown in FIG. 6J, photoresist (40)
Using as a mask, a window for the base electrode extraction part (38) is opened in the 11% oxidation part (39), and at that time, the opening part of the oxide film (39) on the collector electrode extraction part (33) is slightly warped.

Next, as shown in FIG. 6K, photoresist (41)
A base region (48) is formed by masking the collector electrode extraction portion (33) and implanting P-type impurity ions into the active region. At this time, the base electrode extraction part (38)
Ions are also implanted. After this, an annealing treatment is performed.

Next, as shown in the sixth diagram, the oxide film (
34) is removed by etching, a polycrystalline silicon film (42) is formed by CVD to prevent penetration of Aβ, and if necessary, the surface of this polycrystalline silicon film (42) is thinly oxidized. Next, using the photoresist (43) as a mask, an N-type impurity such as arsenic As is ion-implanted into the base region (48), and then a 5i02 film (not shown) for preventing external diffusion is formed by CVD. Drive-in diffusion to form an emitter region (47). Then, this 5i02 film is removed by etching, and then annealing treatment is performed.

Next, as shown in FIG. 6M, after depositing /l, the base electrode (44) and emitter electrode (4
5) A collector electrode (46) is formed, and then sintering is performed.

In the case of this manufacturing method, if the invasion of the birth beak (60) is small as shown in FIG. 7 in the step shown in FIG. 6 I, then in the step of removing the oxide film (34) shown in FIG. The oxide film on the inner side of the lower part of the fourth part is also removed by etching, and as a result, short circuit between the emitter region and the base electrode lead-out part is likely to occur, which becomes a problem when applied to an actual semiconductor device. After the steps in Figure I, CV D T: S
After depositing an i3N4 layer or a SiO2 layer or thermally oxidizing a polycrystalline silicon layer with good coverage thinly deposited by CVD, the window is etched by ion milling or reactive ion etching, leaving an insulating layer on the sides of the recess. In this method, an opening was made, and then the opened part was directly nitrided, and selective oxidation was performed using this as a mask.

According to this manufacturing method, in addition to being an inter-element isolation method that replaces the conventional selective oxidation method that caused problems due to the occurrence of bird's beaks and bird's heads, By opening the window once, the collector region (49), base region (48), emitter region (47), and emitter electrode lead-out portion (50) can be formed using self-alignment, which reduces the device manufacturing cost compared to conventional manufacturing methods. It is possible to achieve further miniaturization, reduce the parasitic capacitance of the collector, and manufacture high-performance, highly integrated bipolar transistor ICs. The planar shape of the openings of the concave portions corresponding to the openings (28) and (29) of the polycrystalline silicon layer (30) is uneven due to the polycrystalline silicon crystal grains, as shown in FIG. If a film is formed thereon in a subsequent process, the quality of the film becomes uniform, making it impossible to obtain desired characteristics or making it difficult to form a device with good reproducibility.

Purpose of the Invention In view of the above points, the present invention makes it possible to form a device with uniformity and good reproducibility by creating an element shape without unevenness due to polycrystalline silicon grains, and also enables further miniaturization of the device. The present invention provides a method for manufacturing a semiconductor device that can manufacture a high-performance, highly integrated IC device.

Summary of the Invention The present invention comprises a process of forming a semiconductor layer on a substrate having unevenness, a process of forming an insulating layer on the semiconductor layer, and anisotropic etching of the insulating layer to form the sidewalls of the unevenness. selectively leaving the insulating layer; forming a nitride layer on the semiconductor layer; forming a material layer on the nitride layer and planarizing its surface; A step of etching the nitride layer so that the nitride layer remains on the recess, a step of introducing impurities into the semiconductor layer using the nitride layer as a mask, and a step of etching the nitride layer into the semiconductor layer using the nitride layer as a mask. This method of manufacturing a semiconductor device includes a step of forming an oxide layer on the surface, a step of removing the nitride layer, and a step of introducing impurities into the semiconductor layer using the oxide layer as a mask.

〔Example〕

Hereinafter, the first embodiment of the method for manufacturing a semiconductor device of the present invention will be described.
This will be explained with reference to the figures. Note that although this example is a case of an NPN transistor element, it goes without saying that it can also be applied to a PNP transistor element.

In this example, as shown in FIGS. 6A to 6E, a semiconductor layer is formed on a substrate having unevenness, and a collector electrode extraction portion (
After forming semiconductor layers (33), as shown in FIG. 1A, semiconductor layers (30) and (31) are grown in a vapor phase.

An insulating film (70) such as an oxide film (5t02) or a nitride film (SiN) is formed on the entire surface of (31') by CVD or thermal oxidation.

Next, as shown in FIG. 1B, the entire surface of the insulating film (70) is etched by anisotropic etching to leave (71) only on the side walls of the recess and remove the other parts.

In the subsequent steps, a semiconductor device is formed using the same steps as those shown in FIG. 6F and subsequent steps.

In the above embodiment, after the process shown in FIG. 6E, the insulation crotch (70)
However, the present invention is not limited to this, and after the step shown in Figure 6, an insulating IQ (70) is formed and anisotropic etching is performed, and then the insulating film (7) at the collector electrode extraction part is etched away. The process shown in FIG. 6E may also be performed.

According to this manufacturing method, the surface shape of the recess formed by the polycrystalline silicon crystal grains can be made flat as shown in FIG. Therefore, a uniform element with good reproducibility can be formed. Furthermore, as shown in FIG. 4, since the emitter formed in a later step and the low resistance region of the base can be reliably separated, the E/B breakdown voltage is also improved.

Furthermore, in the process shown in FIG. 1, when the insulating film (70) is formed by thermal oxidation, the surface of the polycrystalline silicon layer (30) is oxidized, so the graft base region can be made smaller, and as a result, further miniaturization is possible. can be achieved. Furthermore, since the capacitance can be reduced, a high-performance semiconductor device can be manufactured.

〔Effect of the invention〕

According to the manufacturing method of this semiconductor device, in addition to being an element isolation method that replaces the conventional selective oxidation method that has problems with the generation of bird's beaks and bird's heads, It can be formed using self-aligned lines, and a highly integrated semiconductor device can be manufactured.

Furthermore, since the emitter region and the base region can be reliably separated, the E/B breakdown voltage can be improved.

Furthermore, by reducing the graft base area,
A high-performance semiconductor device with a small capacity can be manufactured, and a highly integrated semiconductor device with further miniaturization can be manufactured.

[Brief explanation of the drawing]

Figures 1, 3, and 4 are sectional views of the process according to the embodiment of the present invention, a plan view of the main parts for explanation, and an enlarged sectional view thereof, and Figure 2 is a cross-sectional view of the process according to the embodiment of the present invention, and Figure 2 is a cross-sectional view of the process according to the embodiment of the present invention. 5 and 6A to 6M are cross-sectional views of a bipolar transistor manufactured by a conventional manufacturing method, and FIG. 7 is an enlarged cross-sectional view of important parts to explain the conventional example. It is a diagram. (21) is a semiconductor substrate, (23) is a collector buried layer, (
27) is a 5t02 layer, (30) is a polycrystalline silicon layer, (
33) is the collector electrode extraction part, (34) is the oxide film, (
35) is the nitride film, (38) is the base electrode extraction part, (4
4) is the base electrode, (45) is the emitter electrode, (46)
is a collector electrode, (47) is an emitter region, (48) is a base region, (49) is a collector region, (51) is a bipolar transistor, and (71) is an insulating film formed on the side wall of the recess. Shito phrase for ward ward N −q'tq− < − 0p

Claims (1)

[Claims] a step of forming a semiconductor layer on a substrate having unevenness; a step of forming an insulating layer on the semiconductor layer; and anisotropic etching of the insulating layer to selectively form the insulating layer on the sidewalls of the unevenness. forming a nitride layer on the semiconductor layer; forming a material layer on the nitride layer and planarizing its surface; etching the material layer and the nitride layer; A step of leaving the nitride layer on the recess, a step of introducing an impurity into the semiconductor layer using the nitride layer as a mask, and forming an oxide layer on the surface of the semiconductor layer using the nitride layer as a mask. A method for manufacturing a semiconductor device, comprising: a step of removing the nitride layer; and a step of introducing an impurity into the semiconductor layer using the oxide layer as a mask.