JPS61168252A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPS61168252A
JPS61168252A JP859685A JP859685A JPS61168252A JP S61168252 A JPS61168252 A JP S61168252A JP 859685 A JP859685 A JP 859685A JP 859685 A JP859685 A JP 859685A JP S61168252 A JPS61168252 A JP S61168252A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
film
insulating film
silicon film
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP859685A
Other languages
Japanese (ja)
Inventor
Yasutaka Ikushima
生嶋 康孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP859685A priority Critical patent/JPS61168252A/en
Publication of JPS61168252A publication Critical patent/JPS61168252A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form a resistor having a small occupying area by superposing the first and second polycrystalline silicon films through an insulating film, and connecting them by a side wall. CONSTITUTION:The first polycrystalline silicon film 12 of high resistivity having a slender pattern is formed on the first insulating film 22 formed on a semiconductor substrate, and the surface is coated with the second insulating film 13. One side wall 14 of the film 12 is exposed, and the second polycrystalline silicon film 15 of high resistivity having a slender pattern connected with the side wall region 15 is formed. The third insulating film 16 is formed on the surface of the film 15, and an electrode 17 is formed on the film 16. Thus, since the second resistor L2 can be superposed on a resistor L1, the occupying area of the resistor can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置及びその製造方法に関し、特に占有
面積が小さく且つ、高抵抗値の多結晶シリコン抵抗体を
備えた半導体装置及びその製造方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly a semiconductor device including a polycrystalline silicon resistor that occupies a small area and has a high resistance value, and a method for manufacturing the same. Regarding.

〔従来の技術〕[Conventional technology]

従来、高抵抗値の多結晶硅素抵抗体の形成は、第3図に
示すように、第1の多結晶シリコン肋°(1のみを用い
て形成されていた。半導体装1にの高密度化に伴い上記
多結晶シリコン股1の占有面積も減少させる必要が生じ
てきた。このためには、同一抵抗値を得るには抵抗体の
幅Wを狭くしこれに伴い長さLも短くするのが従来の方
法であった。
Conventionally, a polycrystalline silicon resistor with a high resistance value has been formed using only the first polycrystalline silicon rib (1) as shown in FIG. Along with this, it has become necessary to reduce the area occupied by the polycrystalline silicon crotch 1.For this purpose, in order to obtain the same resistance value, the width W of the resistor must be narrowed, and the length L must also be shortened accordingly. was the conventional method.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、占有面積を減少させるために、同一抵抗
値を得るには抵抗体の幅Wを狭くシ、これに伴い長さL
を短くすると云ってもリソグラフィー技術の現状から考
えると、Wを1.0μm 以下に精度良く形成すること
は困難であり、ひいては抵抗体の占有面積を小さくでき
ないと云う欠点を持っていた。
However, in order to reduce the occupied area, the width W of the resistor is narrowed to obtain the same resistance value, and the length L is accordingly reduced.
However, considering the current state of lithography technology, it is difficult to accurately form W to 1.0 μm or less, and this has the drawback that the area occupied by the resistor cannot be reduced.

本発明の目的は、上記欠点を除去し、占有面積の少ない
、多結晶シリコン抵抗体を備えた半導体装置及びその製
造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device equipped with a polycrystalline silicon resistor that eliminates the above drawbacks and occupies a small area, and a method for manufacturing the same.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の第1の発明の半導体装置は、半導体基板表面に
選択的に形成された第1の絶縁膜と、該第1の絶縁膜上
に伸びて形成された細長パターンを有する高抵抗率の第
1の多結晶シリコン膜と、該第1の多結晶シリコン膜を
徨う第2の絶縁膜と、前記第1の多結晶シリコン膜の一
方の端部において少なくとも露出する側壁領域に接続し
第2の絶縁膜を介して第1の多結晶シリコン股に重なっ
て形成された細長パターンを有する高抵抗率の第2の多
結晶シリコン眸と、該第2の多結晶シリコン膜を覆う第
3の絶縁膜とを含んで構成される。
A semiconductor device according to a first aspect of the present invention includes a first insulating film selectively formed on a surface of a semiconductor substrate, and a high resistivity film having an elongated pattern extending and formed on the first insulating film. A first polycrystalline silicon film, a second insulating film surrounding the first polycrystalline silicon film, and a second insulating film connected to at least an exposed sidewall region at one end of the first polycrystalline silicon film. a second polycrystalline silicon film with high resistivity having an elongated pattern formed overlapping the first polycrystalline silicon film through a second insulating film; and a third polycrystalline silicon film covering the second polycrystalline silicon film. and an insulating film.

また、本発明の第2の発明の半導体装置の製造方法は、
第1の絶縁膜が選択的に形成された半導体基板表面に高
抵抗率の第1の多結晶シリコン膜を形成する工程と、該
多結晶シリコン膜を選択的に除去する工程と、該多結晶
シリコン膜の表面に第2の絶縁膜を形成する工程と、該
第2の絶縁膜を選択的に除去し該第1の多結晶シリコン
膜の表面の一部を露出する工程と、該第2の絶縁膜の表
面と露出しだ第1の多結晶シリコン膜表面とに接して高
抵抗率の第2の多結晶シリコン膜を形成する工程と、該
第2の多結晶シリコン膜を覆う第3の絶縁膜を形成する
工程とを含んで構成される。
Further, the method for manufacturing a semiconductor device according to the second invention of the present invention includes:
A step of forming a first polycrystalline silicon film with high resistivity on the surface of the semiconductor substrate on which the first insulating film is selectively formed, a step of selectively removing the polycrystalline silicon film, and a step of selectively removing the polycrystalline silicon film. forming a second insulating film on the surface of the silicon film; selectively removing the second insulating film to expose a part of the surface of the first polycrystalline silicon film; forming a second polycrystalline silicon film with high resistivity in contact with the surface of the insulating film and the exposed surface of the first polycrystalline silicon film, and a third polycrystalline silicon film covering the second polycrystalline silicon film. The method includes a step of forming an insulating film.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
。第1図は本発明の一実施例の断面図である。第1図に
示すように、11は半導体基板上に形成された第1の絶
縁膜である酸化シリコン膜である。この酸化シリコン膜
11上には細長パターンを有する高抵抗率の第1の多結
晶シリコン膜12が形成されてお如、その第1の多結晶
シリコン膜の表面は第2の絶縁膜13で覆われてお如、
第1の多結晶シリコン膜の一方の端部は少なくとも側壁
領域14が露出され、その側壁領域14で接続された細
長パターンを有する高抵抗率の第2の多結晶シリコン膜
15が第2の絶縁膜上にのび第1の多結晶シリコン膜に
重なって形成されている。そして第2の多結晶シリコン
膜15の表面は第3の絶縁膜16で覆われ、第3の絶縁
膜16には開孔を通して電極17が設けられている構造
を有している。第1図における抵抗体としては従来の抵
抗体L1に重なった抵抗体L2が加わったものが本実施
例の抵抗体となる。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention. As shown in FIG. 1, 11 is a silicon oxide film which is a first insulating film formed on a semiconductor substrate. A first polycrystalline silicon film 12 having an elongated pattern and high resistivity is formed on this silicon oxide film 11, and the surface of the first polycrystalline silicon film is covered with a second insulating film 13. I'm sorry,
At least a sidewall region 14 is exposed at one end of the first polycrystalline silicon film, and a high-resistivity second polycrystalline silicon film 15 having an elongated pattern connected to the sidewall region 14 serves as a second insulating film. The first polycrystalline silicon film is formed so as to extend over the first polycrystalline silicon film. The surface of the second polycrystalline silicon film 15 is covered with a third insulating film 16, and the third insulating film 16 has a structure in which an electrode 17 is provided through an opening. As for the resistor in FIG. 1, the resistor of this embodiment is obtained by adding a resistor L2 overlapping the conventional resistor L1.

第2図(a)〜(C)は本発明の一実施例を説明するだ
めに工程順に示した断面図である。本実施例は次の工程
により実施できる。
FIGS. 2(a) to 2(C) are cross-sectional views showing an embodiment of the present invention in the order of steps to explain it. This example can be implemented through the following steps.

まず、第2図(a)に示すように、半導体基板21と、
この基板の一表面に選択的に設けられた第1の絶縁膜で
ある酸化膜22と、ソース・ドレイン領域23と、ゲー
ト電極としての多結晶シリコン膜24が既知の方法で形
成され、ひき続いてソース・ドレイン領域23上に予め
設けられている酸化膜25に開孔を形成する。続いて高
抵抗率の第1の多結晶シリコン膜26を和・積し、開孔
部でソース・ドレイン領域23と接触し且つ酸化膜22
の表面まで延在させる。
First, as shown in FIG. 2(a), a semiconductor substrate 21,
An oxide film 22 as a first insulating film selectively provided on one surface of this substrate, a source/drain region 23, and a polycrystalline silicon film 24 as a gate electrode are formed by a known method. An opening is formed in the oxide film 25 previously provided on the source/drain region 23. Then, as shown in FIG. Subsequently, a first polycrystalline silicon film 26 with high resistivity is deposited so that it contacts the source/drain region 23 at the opening and forms the oxide film 22.
extend to the surface of

次に、第2図(b)に示すように、第1の多結晶シリコ
ン膜26の表面に第2の絶縁膜27を形成する。第2の
絶縁膜27としては酸化シリコン膜或は窒化シリコン膜
が適している。次いで、第1の多結晶シリコン膜26の
側壁領域28が少なくとも露出するように第2の絶縁膜
27を選択的に除去する。続いて高抵抗率の第2の多結
晶シリコンIji29を第2の絶縁膜27の上部に堆積
し、側壁領域28で第1の多結晶シリコン膜26と接触
させる。
Next, as shown in FIG. 2(b), a second insulating film 27 is formed on the surface of the first polycrystalline silicon film 26. As the second insulating film 27, a silicon oxide film or a silicon nitride film is suitable. Next, the second insulating film 27 is selectively removed so that at least the sidewall region 28 of the first polycrystalline silicon film 26 is exposed. Subsequently, a second polycrystalline silicon film Iji 29 with high resistivity is deposited on top of the second insulating film 27 and brought into contact with the first polycrystalline silicon film 26 in the sidewall region 28 .

最後に、第2図(C)に示すように、第2の多結晶シリ
コン膜29の表面に第3の絶縁膜30を形成し、更にそ
の上面に流動性のあるリンケイ酸ガラス膜31ガどを形
成し、段差を低減した後で、少なくとも第2の多結晶シ
リコン膜30と接触する金属電極32を形成すると、本
実施例の占有面積の少ない多結晶シリコン抵抗体を備え
た半導体装置が形成できる。
Finally, as shown in FIG. 2C, a third insulating film 30 is formed on the surface of the second polycrystalline silicon film 29, and a fluid phosphosilicate glass film 31 is further formed on the upper surface of the third insulating film 30. By forming the metal electrode 32 in contact with at least the second polycrystalline silicon film 30 after reducing the level difference, a semiconductor device including a polycrystalline silicon resistor that occupies a small area according to this embodiment is formed. can.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、第1の多結晶シ
リコン膝と第2の多結晶シリコン膜を絶縁膜を介して重
ねて形成し、側壁領域で接続しているので重なり部だけ
抵抗長を長くすることができ、したがって素子寸法を縮
少しなくても抵抗体の占有面積を少なくすることができ
、半導体装置の高密度化に効果的である。また、この構
造は本発明方法によ如容易に製作することができる。
As explained above, according to the present invention, the first polycrystalline silicon layer and the second polycrystalline silicon film are formed in an overlapping manner with an insulating film interposed therebetween, and are connected at the side wall region, so that only the overlapping portion has resistance. Since the length can be increased, the area occupied by the resistor can be reduced without reducing the element size, which is effective for increasing the density of semiconductor devices. Moreover, this structure can be easily manufactured by the method of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断簡図、第2図(a)〜(
C)は本発明の一実施例の方法を説明するために工程順
に示した断面図、第3図は従来の半導体装置゛の抵抗体
部の断面図である。 1・・・・・・第1の多結晶シリコン脇、11・・・・
・・第1の絶縁膜、12・・・・・・第1の多結晶シリ
コン膜、13・・・・・・第2の絶縁膜、14・・・・
・・側壁領域、15・・・・・・第2の多結晶シリコン
膜、16・・・・・・第3の絶縁膜、17・・・・・・
電極、21・・・・・・半導体基板、22・・・・・・
第1の絶&tllP%、23・・・・・・ソース・ドレ
イン、24・・・・・・ゲート電極、25・・・・・・
酸化シリコン睦、26・・・・・・第1の多結晶シリコ
ン抄、27・・・・・・第2の絶縁膜、28・・・・・
・側壁領域、29・・・・・・第2の多結晶シリコン股
、30・・・・・・第3の絶1tiigllL31・・
・・・・リンケイ酸ガラスIt費、32・・・・・・電
極。 第2図
FIG. 1 is a simplified diagram of an embodiment of the present invention, and FIGS. 2(a) to (
C) is a cross-sectional view shown in order of steps for explaining the method of one embodiment of the present invention, and FIG. 3 is a cross-sectional view of a resistor portion of a conventional semiconductor device. 1... First polycrystalline silicon side, 11...
...First insulating film, 12... First polycrystalline silicon film, 13... Second insulating film, 14...
...Side wall region, 15...Second polycrystalline silicon film, 16...Third insulating film, 17...
Electrode, 21... Semiconductor substrate, 22...
1st &tllP%, 23...source/drain, 24...gate electrode, 25...
Silicon oxide wire, 26...First polycrystalline silicon material, 27...Second insulating film, 28...
- Side wall region, 29... second polycrystalline silicon crotch, 30... third edge 1tiigllL31...
...Phosphorsilicate glass It cost, 32... Electrode. Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板表面に選択的に形成された第1の絶縁
膜と、該第1の絶縁膜上に伸びて形成された細長パター
ンを有する高抵抗率の第1の多結晶シリコン膜と、該第
1の多結晶シリコン膜を覆う第2の絶縁膜と、前記第1
の多結晶シリコン膜の一方の端部において少なくとも露
出する側壁領域に接続し第2の絶縁膜を介して第1の多
結晶シリコン膜に重なって形成された細長パターンを有
する高抵抗率の第2の多結晶シリコン膜と、該第2の多
結晶シリコン膜を覆う第3の絶縁膜とを含むことを特徴
とする半導体装置。(2)第1の絶縁膜が選択的に形成
された半導体基板表面に高抵抗率の第1の多結晶シリコ
ン膜を形成する工程と、該多結晶シリコン膜を選択的に
除去する工程と、該多結晶シリコン膜の表面に第2の絶
縁膜を形成する工程と、該第2の絶縁膜を選択的に除去
し該第1の多結晶シリコン膜の表面の一部を露出する工
程と、該第2の絶縁膜の表面と露出した第1の多結晶シ
リコン膜表面とに接して高抵抗率の第2の多結晶シリコ
ン膜を形成する工程と、該第2の多結晶シリコン膜を覆
う第3の絶縁膜を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。
(1) a first insulating film selectively formed on the surface of a semiconductor substrate; a first polycrystalline silicon film with high resistivity having an elongated pattern extending over the first insulating film; a second insulating film covering the first polycrystalline silicon film;
A second polycrystalline silicon film having a high resistivity and having an elongated pattern connected to at least the exposed sidewall region at one end of the polycrystalline silicon film and overlapping the first polycrystalline silicon film via a second insulating film. A semiconductor device comprising: a polycrystalline silicon film; and a third insulating film covering the second polycrystalline silicon film. (2) forming a first polycrystalline silicon film with high resistivity on the surface of the semiconductor substrate on which the first insulating film is selectively formed; and selectively removing the polycrystalline silicon film; forming a second insulating film on the surface of the polycrystalline silicon film; selectively removing the second insulating film to expose a part of the surface of the first polycrystalline silicon film; forming a second polycrystalline silicon film with high resistivity in contact with the surface of the second insulating film and the exposed surface of the first polycrystalline silicon film; and covering the second polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising the step of forming a third insulating film.
JP859685A 1985-01-21 1985-01-21 Semiconductor device and manufacture thereof Pending JPS61168252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP859685A JPS61168252A (en) 1985-01-21 1985-01-21 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP859685A JPS61168252A (en) 1985-01-21 1985-01-21 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61168252A true JPS61168252A (en) 1986-07-29

Family

ID=11697353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP859685A Pending JPS61168252A (en) 1985-01-21 1985-01-21 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61168252A (en)

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