JPS61167218A - Generating circuit for variable period pulse train - Google Patents

Abstract

PURPOSE:To form a variable period pulse train generating circuit with the ease of circuit integration by combining a basic pulse train generating means, a unit circuit means group and a command circuit means. CONSTITUTION:The unit circuit means group 20 is formed by the cascade connection of unit circuit means 20i (i=1-m) including a frequency-division means 21i and a switching circuit means 22i. The frequency division means 20i applies frequency division while receiving the output of the unit circuit means of the pre-stage. The switching circuit means 22i switches selectively a basic pulse from the basic pulse train generating means 10 based on a switch command SWPj (j=1-m). On the other hand, the command circuit means 30 consists of a shift register formed by the cascade connection of a command circuits 30j and generates sequentially the switch command SWPj while receiving the output of the unit circuit means 20m at the final stage. Thus, a variable period pulse train OP is obtained. As a result, since the wiring between element is simplified, the circuit integration is attained easily.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

In the present invention, the inter-pulse period increases sequentially over time, for example, every predetermined number of pulses. Preferably, the present invention relates to a variable period pulse train generating circuit that generates a pulse train that increases by a predetermined ratio, and particularly to a circuit suitable for measuring the so-called EV value of an object to be imaged.

[Prior art and its problems]

The above-mentioned variable period pulse train generation circuit as a subject of the present invention is useful for measuring the so-called EV value, which is a measure of the brightness of an object to be photographed when photographing or imaging the object with a television camera, etc. Since it is used as part of a circuit for measuring the distance to the imaging target, the necessity of this will be explained first with reference to FIGS. 5 and 6. What is shown on the left side of FIG. 5 is an optical sensor 1 such as a photodiode or a phototransistor, which receives light from an object to be imaged (not shown) through a lens (not shown), and has an essential effect on the light intensity. A video signal 1 with an analog value directly proportional to is generated. 1 * Optical sensor] is sufficient for simple EV value measurement, but when image pattern processing is required, such as when measuring distance, an optical sensor array or a TV camera target as shown is required. etc., and a large number of sets of circuits numbered 2 or less are provided accordingly, but for the sake of simplicity, only one set is shown in the figure. As is well known, the light intensity of incident light is 1 to 1.
Since the electrical signal can fluctuate within a range of about 0" to 106, it is not possible to accurately evaluate an electrical signal with such a large variation range using a normal measuring circuit. Therefore, the video signal l is measured using an integrating circuit 2 such as a capacitor. After integrating,
It is reasonable to use the time required for the output e of the integrating circuit to reach the threshold eth of the threshold circuit 3 at the next stage as a measure of the intensity of light. Now, the integrating circuit 2 has a capacitance C
, and the brightness of the light is B
, if the corresponding video signal l is a photocurrent, then
Since the output e of the integrating circuit 2, that is, the capacitance voltage of the capacitor C, is charged or discharged by the photocurrent I, the following equation holds true. However, the amount is constant regardless of time t. Therefore, the following equation further holds. If the time taken for the output 0 of the integrating circuit 2 at e*B-1/ to reach the threshold eth is t, then eth=-B-t/C (k: constant of proportionality), and the threshold Since eth is constant, the brightness B is expressed as k t . This is a relationship expressed by an inverse proportion or a hyperbola as shown in FIG. 6(a). Now, as is well known, the EV value is expressed by a logarithmic relationship with the base 2 of the brightness B, and this is expressed by the formula: EV56kgtB
・−・−・−・−・−・・・・・−・−・−・・
・−・−・・・(2) If we take the logarithm of both sides of equation (1) and substitute equation (2), we get EV”leglt or EV −A −B lag,
t −−+31. However, A and B are constants. FIG. 6 (bl is a diagram showing this.) Measuring the EV value can ultimately result in measuring time t, but in order to measure time t, for example, a counter 4 is used as shown in FIG. After clearing the count value of the counter 4 with a reset pulse RP at the start of a specific specification, a count pulse CP as shown from the pulse train generation circuit 5 is counted, and the count is stopped by the output from the threshold circuit 3. The count value of the counter 4 at the time of stopping is read by the evaluation circuit 6 as the measured value of the time t.The value for the brightness B1 at the time measured in this way is set as tl as shown in FIG. If the value for the brightness B2 (-2XBI), which is twice the brightness B1, is t2, then it is tl-2Xt2.However, in a simple circuit like this, the brightness B is about 1 to 106, as you can see on the package. If the value of time t varies over a wide range, the value of time t will also change to 10.
It varies over a wide range of about 4 to 1, and the counter 4 needs to have a very large number of digits. To solve this problem, the pulse train generating circuit 5 is most simply caused to generate a variable period pulse train CPI in which the pulse time period is doubled for each pulse as shown in the figure. In this way, even if the brightness B doubles and therefore the EV value increases by 1, the count value of the counter 4 can be made to increase by only 1. However, in practice, it is necessary to find the value below the decimal point of Ev (1), so Fig. 6 (b)
As shown in FIG. 3, a variable period pulse train CPI is used in which the IEV value is divided into, for example, eight pulses and the inter-pulse period is doubled for every eight pulses. Of course in this case EV
Every time the value differs by 1, the count value of the counter 4 changes by 8. The change range of brightness B from 1 to 10' corresponds to approximately 17 EV value widths, and in this example, the required number of steps for binary counter 4 is IEV (PI per II), which is 3 steps, so the number of steps of the counter is approximately 50 steps. The circuit shown in Fig. 7 is known as a conventional example of a variable frequency °C 1 pulse train generation circuit suitable for the above purpose (
For example, see Japanese Patent Application Laid-Open No. 59-25414), which applies the basic clock pulse CP to the first binary counter 51 to
The positive clock pulse CP is counted, and each stage Q0,
01. Ω2. ... is taken out as the output pulse OP while sequentially selecting it every n pulses through the selection circuit 52. Therefore, the output pulse OP is 1/n.
A frequency divider, 178 in the previous example, is applied to the frequency divider 53, and the output pulse from the frequency divider 53 is fed to a second binary counter 5.
4 is given and counted. Of course, the first and second counters 51 and 54 are reset by the reset pulse RP at the start of pulse train generation, so the initial count value of the second binary counter 54 is 0, and at this time the selection circuit 52 is its selection human power S1. S2. S3. ... receive all 0s, and the first stage output QO of the first binary counter is received at its input 10 and output as is as an output pulse OP. Since the first stage output 00 at this time corresponds to the clock pulse CP divided by z, the inter-pulse period of the output pulse OP is twice that of the clock pulse CP. When n output pulses OP are output, for example 8, 1/n
Since one count pulse is given from the frequency divider 53 to the second binary counter 53, its first stage 01 becomes 1, and the selection circuit 52 receives this in the selection manual S1 and in turn outputs the first count pulse to the input ball 1. The second stage output 01 of the binary counter 51 is selected and outputted as the output pulse OP. Similarly, each time the output pulse OP is on the n side, the second binary counter 54 counts and amplifies the output by 1, and in response, the selection circuit 52 increases the output stage of the selected first binary counter by 1. Since the output pulse OP is increased step by step, the period of the output pulse OP doubles every n pulses. In this conventional circuit, as described above, the output pulse OP is output from any one of the stages of the first binary counter 51.
In addition to the inconvenience that the highest frequency of the output pulse OP is half of the basic tarok pulse CP, there are the following problems. When attempting to integrate the circuit shown in FIG. 7 on a semiconductor chip, a selection circuit 52, first and second binary counters 51,
54 must be connected with many signal lines,
Furthermore, within the selection circuit 52, selection input S1. Since it is necessary to connect S2 etc. and input i0.11.12 etc. with a fairly complicated logic circuit, the wiring for connections inside and outside the selection circuit becomes complicated and the chip area for wiring becomes large. Furthermore, restrictions on signal wiring make integration extremely difficult. Further, since the stepwise increase rate of the period of the output pulse OP is also determined to be 2 depending on the configuration of the first binary counter 51, the degree of freedom in designing the circuit performance is also low. Furthermore, this conventional circuit is
If you try to use it to measure the V value, there is a problem that accurate measurement values cannot be obtained. To explain this with reference to Figure 6 (al), as mentioned above, since the brightness is B2-2・Bl, the time that is inversely related to this must be tl-2・t2. However, in the conventional circuit, if the period of the first n pulses is 10, the time during which these n pulses are generated is n-tO, which is t2, so t2=
The period of n pulses of the 0th order which is n -tO is 2・t
o, so the time of occurrence is 2・n −to, and the addition of time t1 to this is t2, so tl−3
・N-to, which does not meet the above-mentioned tl-2/t2 condition. In order to satisfy this condition, it is only necessary to generate one pulse 21' instead of n pulses at first. In this case, t2-2・n・

0, zl”4・nt
Since it becomes O, the above condition is satisfied. In other words, the period is doubled every n pulses, but unless 20 pulses are generated in the first pulse train, accurate EV values cannot be measured. Although it is not impossible to make modifications or add circuits in this way, as is easily understood, conventional circuits are not necessarily convenient for such purposes. [Object of the Invention] The present invention provides a variable period pulse train generating circuit of the type described at the beginning, which has simple wiring and is therefore easy to integrate into an integrated circuit, that is, a pulse train whose period of generated pulses is variable over time. The main purpose is to obtain a circuit that generates A further object of the present invention is to construct this type of pulse train generating circuit by repeating unit concave path means as simple as possible, thereby further facilitating integration. Furthermore, a secondary but important object of the present invention is to provide an advantageous variable IIIX for use in a circuit for measuring the EV value of an imaging target, for example.
The object of the present invention is to obtain a JI pulse train generation circuit, that is, a circuit suitable for measuring an EV value by replacing it with a time amount that is inversely proportional to the EV value. Summary of the Invention According to the present invention, the above-mentioned main object is to provide a basic pulse train generating means for generating a pulse train of a constant period in a variable period pulse train generating circuit, a pulse train frequency dividing means, an output pulse of the cough frequency dividing means, and the output pulses of the pulse train frequency dividing means and the cough dividing means. Switching circuit means that receives a basic pulse and selectively outputs one of the basic pulses based on a switching command is connected in multiple stages in series so that the frequency dividing means receives the output pulse from the switching circuit means in the previous stage. a group of unit circuit means, and a command circuit means which includes at least a number of stages of command circuits corresponding to each unit circuit means in the group and connects the command circuits in cascade, and the command circuit means is a unit circuit means. Upon receiving the output pulse from the final stage unit circuit means in the group, each command circuit issues a command to the corresponding switching circuit means to switch the output from the basic pulse side to the output pulse side of the frequency dividing means. Each time an output pulse is received from the switching circuit means of a stage, it is applied sequentially in the direction from the last stage to the first stage in the unit circuit means, and the pulse interval is given from the last stage unit circuit means in the unit circuit means group. This is achieved by extracting a train of output pulses that increases over time. According to the above-mentioned basic structure of the present invention, the group of unit circuit means serving as the backbone of the circuit only needs to be connected sequentially in series in multiple stages in a nest, so wiring for connection between the unit circuit means is extremely difficult. It gets easier. In addition, since the command circuit means can be similarly connected in cascade, the wiring between the command circuits can be minimized, and the wiring between the corresponding stages between the unit circuit means group and the command circuit means can also be minimized at each stage. Since only one command line is required per unit, wiring is simple and does not take up much space. It is also possible to incorporate each command circuit within the command circuit means into a corresponding unit circuit means, as will be described later. The frequency division means in each unit circuit means are all set at the same frequency division ratio, for example, A
Therefore, in this case, all the positioning circuit means may have the same construction, and the above-mentioned secondary object of the present invention is thereby achieved. Of course, all the command circuits in the command circuit means can be constructed in the same manner. The pulse train generation circuit according to the present invention generates a pulse train whose period changes over time, but in actual applications such as for EV value measurement, it is necessary to generate a predetermined number of pulses at the same period as described above. , it is often necessary to generate a pulse train with a period different from this for the first time.The generation of a pulse train in such a manner is possible within the basic configuration of the present invention described above. In particular, by frequency-dividing the output of the final-stage unit circuit means by a predetermined frequency division ratio of 1, for example, a 10-frequency division ratio divided by a power of 2, and then giving it as a sidewalk pulse to the first-stage command circuit in the command circuit means, It can be easily done. As a result, a number of pulses corresponding to the frequency division ratio are generated at a constant period. The frequency dividing means in each unit circuit means may most simply be a counter, especially a binary counter, and the EV
In the value measurement example, the division ratios of each frequency division means may all be A, so a single-stage binary counter is sufficient.Of course, the division ratios of each frequency division means are generally different. On the other hand, the switching circuit means in each unit circuit means can be easily constructed by combining several logic circuit elements such as NAND circuit elements. One of the preferable types of command circuit means is a multi-stage shift register, in which each stage plays the role of a command circuit, and the first stage of this shift register has a unit circuit as described above. The output of the final stage unit circuit means in the means group is given as a shift pulse,
For example, two methods can be implemented to provide the data to be shifted. One is a mode in which a predetermined logical value, for example "1", is always applied as data to the write input terminal of the first stage of the shift register, and in this case, the output pulse train from the circuit of the present invention is stored in each unit circuit means. For example, if all the frequency dividing factors are 2, the period of the pulse train is 2 seconds, 2+, 2s, etc. The ratio changes over time. Another aspect is to first set a predetermined logic value of 1 to the first stage of the shift register.
For example, by simply giving "1", this logical value is advanced from the first stage to the final stage by a shift pulse, and in this case, the switching circuit corresponding to the command circuit in which the logical value exists Since only the means selects the frequency dividing means side as an output, the period of the generated pulse train from the circuit of the present invention is determined only by the frequency division ratio of the frequency dividing means of the relevant stage. Therefore, in this case, by appropriately selecting the frequency division ratio of each stage, the period can be made not only to simply increase as before but also to decrease depending on the case. Another preferable LiPA for the command circuit means is to configure each command means with a D-type or engine trigger type flip-flop, and the advantage of this embodiment is that the flip-flop is incorporated into each unit circuit means. An advantage of the present invention is that the overall configuration of the circuit according to the present invention can be further simplified.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4. FIG. 1 shows an embodiment in which one shift register is used in the command circuit means 30 shown at the bottom of the figure.
Above it, a unit circuit means group consisting of m unit circuit means 2 (H(1-1 to m)) each surrounded by a dashed line is shown. Each unit circuit means, for example, the first unit circuit. The means includes a frequency dividing means 211 and a switching circuit means 221. The frequency dividing means 211 may be a binary counter as described above, and the dividing ratio thereof is 2 in the case of EV value measurement. Since this is necessary, it is a simple one-stage binary counter.The frequency dividing means 21 receives the output pulse train of the switching circuit means of the unit circuit means 20 and 1 in the preceding stage, and divides the pulse train at a predetermined frequency division ratio. The output is applied to one switching input of the switching circuit means 221. Each switching circuit means 2
21 is constructed by combining a plurality of logic circuit elements as shown in FIG. 2, and receives a constant period pulse train cp from the basic pulse train generating means 10 (not shown) at the other switching input. This basic pulse train generating means 10 may be an ordinary clock pulse generator, as will be understood by 5.
As can be seen from FIG. 1, each unit circuit means 201 in this embodiment is connected in series with its preceding and succeeding stages by a single wiring. In the example shown in FIG. 2(al), the switching circuit means 22i includes one inverter 23 and two AND gates
The AND gate 24 receives the basic pulse train CP from the basic pulse train input terminal TC at one input, and receives the switching command 5WPJ from the switching command input terminal TS at the other input. 23
received in reversed form. The other AND gate 25 receives the output of the previous stage unit circuit means from the frequency dividing input terminal TI at one input, and receives the aforementioned switching command 5hpj at the other input. The OR gate 26 receives the outputs of the AND gates 24 and 25 at its two inputs, and outputs the logical sum thereof to the output terminal TO. Figure 2 (1))
In this example, the switching circuit means 221 consists of one inverter 23 and three Nant gates 27, 28, 29, which are connected by M1 as shown in FIG. Figure 2(a). (1)) The operation is the same, and the switching command is 5W.
When Pj has the logical value "0", the output from the output terminal TO selects the basic pulse train cp from the basic pulse train input terminal,
When the switching command 5itpj has a logical value of "1", the output of the previous stage unit circuit means from the frequency dividing input terminal TI is output from the pulse output terminal TO. The command circuit means 30 that issues the switching command 5WPJ to each switching circuit 221 is one shift register as described above, but in this embodiment, the number of stages is one more than the number m of stages of the unit circuit means group 20. 0 configured in m+l
In the figure, these stages are designated 30j (J-0 to J-m). Also, as can be seen from the figure, the order of the stages is numbered in the opposite order to that of the unit circuit means group 2o.
In the figure, the first stage 300 on the right side has a unit circuit, and the output of the final stage unit circuit means 20m of the circuit means group 20 is divided into 1 by the frequency divider 31.
The pulse train frequency-divided by /n is received by the shift pulse human power C as a shift pulse train SP. As mentioned above, this frequency division ratio determines the number n of pulses to be repeatedly generated in the same period.
It is desirable to select a frequency division ratio of 1 divided by a power of , and in practice it is set to n-32, for example. In this embodiment, a logic value rlJ is always applied to the data input IN, which is another input of the first stage 300, as data to be written to the first stage 300. The operation of the embodiment circuit shown in FIG. 1 will be explained below with reference to FIG. 3. The waveforms of the signals shown in the figure are:
This corresponds to the case where the frequency dividing ratios of the frequency dividing means 211 (1-1 to m) in FIG. 1 are all A. FIG. 3 (11) shows the reset pulse RP, whose signal value is kept at the "1" value until time ta, and the shift register 30
The shift register 30 and therefore the circuit of FIG. 1 are put into a reset state through the reset state R of , but this is released at time ts and the circuit starts operating. The lower part thereof (the clock pulse cp indicated by bl is a basic clock pulse train given to each one input of the switching circuit means 22i (1=1 to m) and has a basic frequency) l]Tb. Now, the "1" value of the write data signal DS is always given to the data input IN of the shift register 30, but immediately after the operation start time ts, the shift pulse SP corresponding to the shift pulse C is not yet given. Therefore, each stage 30J (j-0 to m) serves as a command circuit.
The output from, that is, the switching command signal 5WPJ (j-1 to m
) are all "0" values, and each switching circuit means 221 (I-1 to I-m) that receives this command all outputs the clock pulse CP as it is. Therefore, the output pulse OP from the circuit in this state is the output from the final stage switching circuit means 22m+, that is, the clock pulse CP.
This state is illustrated in the range of period TO in FIG. 3, icl. As will be seen, in the circuit of the present invention, unlike the conventional circuit, the highest frequency of the output pulse OP can be made equal to the frequency of the clock pulse CP. In this embodiment, as shown in the figure, the output pulse OP has already been generated before the start of operation t3, but if necessary, the clock pulse CP can be generated in synchronization with the reset pulse RP.
Of course, it is possible to start generating the output pulse OP from the time ts by providing a gate in the output pulse OP circuit that is enabled by the "0" value of the reset pulse RP. It is. When n clock pulses CP and therefore n output pulses OP are issued after time ts, the first shift pulse SP that rises at this time 10 from the frequency divider 31 is sent to the shift register 30 as shown in FIG. 3 (dl). Shodan 30
A shift pulse of 0 is given to the human power C. by this,
The output 5typo of the first stage is "1" as shown in (8) in the same figure.
However, in this embodiment, the swpo is not applied to any switching circuit means 221 (1-1 to m), so that the period of the output pulse OP remains unchanged and is still equal to the basic period Tb. , Incidentally, the period TO from the time ts to this time to is equal to n-Tb, but at the time t1 when n output pulses OP are further emitted from the time to, the shift pulse SP rising at the time tl becomes Shift pulse manual power C of shift register 30
is given again to the output 5 of the next stage 301.
The WPI takes the rlJ value as shown in +f) in the same figure, and this is sent as the switching command 5WPI to the switching circuit means 22- in the final stage.
Therefore, the means 22m is switched to output the signal from the final stage frequency dividing means 21 as the output pulse OP. Now, since the frequency dividing means 21m receives the output of the unit circuit means 20m-1 at the previous stage, that is, the clock pulse CP at this point, the unit circuit means 20II at the final stage receives the clock pulse CP from the frequency dividing means 20m-1.
The pulse whose frequency has been divided into A by 1 is outputted as the output pulse OP. Note that the first period T1 shown in FIG. 3 (C1) from the operation start time t3 to this first switching time t1 is equal to 2·To. After the time t1, n output cover 9 less OPs are issued. Therefore, each time the shift pulse SP is emitted from the frequency divider 31,
The shift register 30 begins to output "1" as a switching command while moving step by step toward the left in FIG. The period of the pulse OP increases twice as much as the previous one, as shown in Figure 3 (gl, (hl and IcI). Period T2 is T2-2・T
It is expressed as 1-4・To. More generally, the period Tj from the operation start time ts to the j-th switching time tj
can be represented by Tj-2'-TO. from now,
It can be seen that according to the circuit of the present invention, precise measurement of the EV value as described above is possible, and an accurate measurement circuit in which the period of the output pulse is successively doubled can be constructed. That is, only the output of the first stage 300 of the shift register 30 is used as the switching command SWP and the unit circuit means 201 (1-1 to
m) by simply avoiding giving it to E.
Accurate measurement of V values and the like can be guaranteed. Next, an embodiment of the circuit of the present invention shown in FIG. 4 will be described. In this embodiment, instead of the multi-stage shift register 30 in the first embodiment shown in FIG.
m) is used, and the flip-flops 40j of j-1 to m are connected to the corresponding unit circuit means 201(1-
1 to m), respectively. Figure 4 fat
Each position circuit means 20+(1−) in the circuit of the present invention shown in FIG.
1 to m) respectively include such flip-flops 40j (j=1 to m) as shown in detail in the same figure to), and are connected in series to each other as shown in the figure, and from the final stage 20m. An output pulse OP is taken out. Also,
This output pulse OP is given to the 1/n frequency divider 31 as in the previous embodiment, and the output of the frequency divider 31 is given to the clock terminal C of the first stage flip-flop 400, and the unit circuit means 20+( It is also given in common to the clock power C of the flip-flops 40j (j-1 to m) in 1=l to m). A data signal DS, that is, a logical value "1" is always applied to the D input of the first stage flip-flop 400. Each unit circuit means 20i (1-1 to m) receives a signal from the output terminal To of the preceding stage at its input terminal TI, and receives a signal from the Q output terminal TQ of the succeeding stage at its D input terminal TD. Connected in cascade as shown. Also,
These unit circuit means 201 (i is 1 to m) commonly receive a clock pulse CP, a reset signal RP, and a shift pulse SP at their clock input terminals TC, reset input terminals TR, and shift pulse input terminals TS, respectively. Note that this shift pulse SP is the output signal of the frequency divider 31 described above. The specific circuit of each unit circuit means 201 shown in FIG. One part B, whose input is connected to the input terminal TI, is a switching circuit section, consisting of three Nant gates 271, 281, and 291 shown previously in Fig. The gate 271 receives the clock pulse CP from the clock terminal TC at one input thereof, and the gate 271 receives the clock pulse CP from the clock terminal TC.
8i is a zero NAND circuit 271 which receives the output signal of frequency dividing means 211 at one input, and the other input of 281 is the output of flip-flop 40j. Each Q output is a receiving stone, another Nantes gate 29
1 receives the outputs of both Nant gates 271 and 281 at its two inputs, and its output signal is guided to the output terminal TO. The configuration of this part B is equivalent to the previous figure 2), and the other input of the Nant gate 27I is connected to the flip-flop 40J.
By making it possible to receive the output of R
are connected to the D input terminal TD, the shift pulse input terminal ↑S, the Q output terminal TO, and the reset input terminal TH, respectively. As can be easily seen, in the circuit of the embodiment shown in FIG. 4, the switching commands 5WPj (J-1 to m) in FIG. 1 are all exchanged within the unit circuit means 20i (i is 1 to m). Other than that, the operation is exactly the same as the previous embodiment, and the waveforms of the signals RP, CP, OP and SP are as shown in FIG.
As shown in a) to fdl. However, the circuit configuration of this embodiment is simpler than the previous embodiment, as can be seen by comparing FIG. 4 with FIG. 1, and is therefore more suitable for integrated circuits. That is, in this embodiment, the circuit of the present invention can be easily constructed by simply combining one frequency divider 2x31 and one flip-flop 400 to m unit circuit means 201 (l is 1-m), all of which are configured identically. It can be constructed mechanically, so to speak. Furthermore, the number of wiring lines for connection between these circuit elements can also be kept to the necessary minimum as shown in the figure. In addition to the two representative embodiments described above, the circuit of the present invention can be implemented in various different ways as described in the Summary of the Invention and the Claims.

【Effect of the invention】

As explained above, according to the circuit of the present invention, a variable period pulse train generation circuit in which the period between pulses changes over time includes a basic pulse train generation means for generating a pulse train of a constant period, a pulse train frequency dividing means, and a pulse train frequency dividing means for generating a pulse train of a constant period. unit circuit means including an output pulse and a switching circuit means for receiving the basic pulse and selectively outputting one of the basic pulses based on a switching command; Basically, there are three groups of unit circuit means connected in series in a plurality of stages, and a command circuit means in which the command circuits are connected in series and includes at least the number of stages of command circuits corresponding to each unit circuit means in the group. Since it can be constructed only with the following circuit components,
The circuit configuration is simplified in principle, and the number of wires between circuit components is also simpler than in the prior art, making it easier to integrate into an integrated circuit. In addition, in many applications to which the circuit of the present invention is applied, all the frequency division ratios of the frequency division means in each unit circuit means may be the same, so the main circuit components including the command circuit means can be simply replaced with elements of the same configuration. It can be configured by simply repeating the process, making it easier to integrate the circuit. E
~? Even in applications where the value to be measured is replaced with an amount of time that is inversely proportional to it, such as when measuring a value, the prior art uses a variable period pulse train to accurately measure the time. However, as can be seen from the above explanation, according to the circuit of the present invention, by changing the part of the entire circuit according to the purpose, a precise measurement circuit can be constructed extremely easily. be able to. In addition, although the circuit of the present invention has a simple configuration, it has a large degree of freedom in selecting the parameters of each circuit element, and can be implemented in various ways within the gist to suit a wide range of applications. It is particularly valuable as a basic pulse generation circuit for integrated circuits.

[Brief explanation of drawings]

1 to 4 illustrate a variable period pulse train generation circuit according to the present invention, of which FIG. 1 is a block circuit diagram showing the circuit configuration of a first embodiment of the circuit of the present invention, and FIG. 3 is a circuit diagram showing two specific configuration examples of the switching circuit means in the circuit of the first embodiment; FIG. 3 is a waveform diagram showing waveforms of main signals in the circuit of the first and second embodiments of the present invention; FIG. 4 is a circuit diagram showing the configuration of a second embodiment circuit of the present invention. FIG. 5 is a block circuit diagram of a measurement circuit showing the principle of measuring the EV value of an object to be imaged by an imaging means as an example to which the circuit of the present invention is applied, and FIG. FIG. 2 is a graph diagram illustrating the principle of measuring the brightness of an imaging target by converting an EV value into a time amount. FIG. 7 is a block circuit diagram illustrating a variable period pulse train generation circuit according to the prior art. In the figure, 10: Basic pulse train generation means or clock pulse generation circuit, 20: Unit circuit means group, 201 (i-1 to m)
: Unit circuit means, 211(i-1~m): Frequency dividing means, 22t(i-1~m): Switching circuit means, 23: Inverter, 24, 25: AND gate, 26: OR gate, 27.27i( i −0= m), 28.28
j (j −0” m), 29°29j (j = 0 to m):
NAND gate, 3o: command circuit means or shift register, 30j (j=0-m): each stage of the command circuit or shift register, 31: frequency divider or 1/n frequency divider, 40j (j-0-m) : D type flip-flop constituting the command circuit means, CP: 5 pulses or clock pulse, Ds=data signal, OP: output pulse as a variable periodic pulse emitted by the circuit of the present invention, RP
: Reset pulse, SP: Shift pulse, 5WPj(j
-1 to m): switching command, input terminal of unit circuit means, ↑0: output terminal of unit circuit means, TD: D input terminal of unit circuit means, Ω: Q output terminal of unit circuit means,
TR: reset input terminal of the unit circuit means, TS+shift pulse input terminal of the unit circuit means, t3: start point of operation of the circuit of the present invention, tj U -1, 2,...): point of switching of pulse period. .

Claims (1)

[Scope of Claims] 1) A basic pulse train generating means for generating a pulse train of a constant period, a frequency dividing means for the pulse train, and an output pulse of the frequency dividing means and the basic pulse, and one of them is selected based on a switching command. a group of unit circuit means in which a plurality of unit circuit means including a switching circuit means for outputting a signal are connected in series so that the frequency dividing means thereof receives output pulses from the switching circuit means in the preceding stage; a command circuit means comprising at least a number of stages of command circuits corresponding to the number of stages corresponding to the unit circuit means and the command circuits connected in cascade; Upon receiving the pulse, each command circuit sends a command to the corresponding switching circuit means to switch the output from the basic pulse side to the output pulse side of the frequency dividing means. The output pulse train is applied sequentially in the direction from the last stage to the first stage in the unit circuit means, and the output pulse train whose inter-pulse period increases over time is taken out from the last stage unit circuit means in the unit circuit means group. A variable period pulse train generation circuit characterized by: 2) A variable period pulse train generating circuit according to claim 1, wherein the frequency dividing ratios of the frequency dividing means of each stage included in the unit circuit means group are all selected to be equal to each other. 3) A variable period pulse train generation circuit according to claim 2, wherein the frequency division ratio is 1/2. 4) In the circuit according to claim 1, the command circuit means supplies the first stage command circuit with an output pulse obtained by dividing the output from the final stage unit circuit means in the unit circuit means group at a predetermined frequency division ratio. A variable period pulse train generation circuit characterized in that it receives a pulse train in the form of a pulse train. 5) A variable period pulse train generating circuit according to claim 4, wherein the predetermined frequency division ratio is 1/2. 6) In the circuit according to claim 1, the variable period pulse train is characterized in that the command circuit means receives an output pulse from the last unit circuit means in the group of unit circuit means in its first stage command circuit. generation circuit. 7) In the circuit according to claim 1, the frequency division ratios of the frequency division means of each stage included in the unit circuit means group are all 2, and each of the frequency division means from the first stage to the second stage and thereafter in the command circuit means A variable period pulse train generation circuit characterized in that a switching command is given from a stage command circuit to each unit circuit from the final stage to the first stage in the group of unit circuit means. 8) In the circuit according to claim 1, the switching command from the command circuit of each stage in the command circuit means is stepped one stage at a time by an output pulse from the final stage unit circuit means in the unit circuit means group. A variable period pulse train generation circuit characterized in that: 9) A variable period pulse train generating circuit according to claim 1, wherein the frequency dividing means in the unit circuit means is a frequency dividing circuit. 10) The circuit according to claim 1, wherein the frequency dividing means in the unit circuit means is a counter circuit in which an input pulse is received at the first stage and an output pulse is taken out from the last stage. circuit. 11) A variable period pulse train generating circuit according to claim 1, wherein the switching circuit means is constructed by combining logic circuit elements. 12) In the circuit according to claim 1, the command circuit means is a shift register circuit, and the output pulse from the final stage unit circuit means in the unit circuit means group is sent to the clock terminal of the first stage as a step pulse. A variable period pulse train generation circuit, characterized in that the output of each stage is sent as a switching command to each unit circuit means in a group of unit circuit means. 13) The variable period pulse train generating circuit according to claim 12, wherein a signal of a predetermined logic value is always applied to the logic value write input terminal of the first stage of the shift register. 14) In the circuit according to claim 1, each command circuit in the command circuit means is a D-type flip-flop circuit, and the D input of each flip-flop circuit receives the output of the preceding flip-flop circuit. Flip-flop circuits are connected in series as shown in FIG. A variable period pulse train generation circuit characterized in that the pulse train is applied to each unit circuit means in a group. 15) The circuit according to claim 14, wherein a flip-flop circuit corresponding to each unit circuit means in the group of unit circuit means is incorporated in each unit circuit means. . 16) A variable period pulse train generation circuit according to claim 1 or 15, characterized in that the circuit is integrated within one semiconductor chip. 17) A variable period pulse train generation circuit according to claim 1, wherein the circuit is used as a circuit for measuring an EV value of an object to be imaged.