SU570884A2 - Device for checking and measuring parameters of digital semi-conductor elements - Google Patents

Description

the outputs are with a digital unit for measuring time intervals and a power generation unit for automatically shifting clock pulses.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagrams of his work.

The device comprises a block 1 consisting of a holder of digital semiconductor elements, switching elements and sources of supply voltages and loads; block 2 strobe conversion of the input signal; a strobe 3 output conversion unit; unit 4 of the pulse generator; block 5 automatic shift clock; strobe pulse forming unit 6; block 7 of the discriminator of the origin of the measured time interval; block 8 of the discriminator of the end of reference of the measured time interval; a digital time interval measurement unit 9; voltage generation unit 10 for automatically shifting clock pulses; blocks 11-13 controlled voltage-to-current converters, to the combined inputs 14-16 of which voltage is applied to automatically shift the clock pulses, and from outputs 17-19, a current proportional to the voltage at inputs 14-16, respectively, is output, with its own for each converter by conversion factor. This happens when the control inputs 20–22 have the enable signals generated by the decoder unit 23, which, in turn, is controlled by signals from the output of the read step fixation circuit of the unit 9 for digital measurement of time intervals. The control unit 24 is connected to the units 1, 4, 10.

The sequence of measurement of parameters and the conditions for the transition to the measurement of the next parameter are determined by block 25 of the programmatic measurement of parameters by the principle of "fit-marriage. The device contains a read discretionary control unit, the inputs of which are connected to blocks 7 and 8 of the discriminators of the beginning and end of the measurement of the measured time interval, and the outputs are connected to the digital measuring unit 9 of the time intervals and the voltage generating unit 10 for automatic synchronization of the clock pulses.

An embodiment of a controlled voltage-to-current converter (block 11) comprises a diode 26, a pnp-transistor 27 and a resistance 28. One of the embodiments of the read discreteness control unit 29 is shown in FIG. 1, it contains a memory trigger 30, logic circuits AND 31 and 32, a pulse counter 33, an OR circuit 34, a decoder 35. In this case, an embodiment of the device in which the measurement result is represented by a three-digit number (floating point) is considered. In addition, in block 9 of digital measurement of time intervals and in block 10 of voltage generation, three-decade decimal counters with a read decoupling ratio of the highest decade to a younger one equal to ten are used for the auto-shift of clock pulses, and the counter 33, which is part of the read discreteness control unit , has three states. The features of the operation, which are caused by the introduction of the read discretion control unit 29 into the main device, are as follows. Before the arrival of the first clock pulse (| Fig. 2, a), corresponding to the beginning of the measurement, the average decade of the pulse counter included in the voltage generation unit 10 for the automatic shift of the clock pulses is set to

full state, which corresponds to the discrete value of the highest decade of the counter (Fig. 2.6, level f / i). The decoder signal 35, corresponding to the initial state of the counter 33 pulses

of the reading discretion control unit, opens the high-order decade of the pulse counter, which is part of the voltage generation unit for automatic shift of the clock pulses. Finding the established

The level is maintained in the largest steps with a resolution of the highest decade equal to 100 / g (h is the read resolution, set) for this range). At the same time, the remaining two decades of the counter are closed with signals from

decoder 35.

When the set level is exceeded (see Fig. 2.6) at time i, block 7 of the discriminator of origin of the measured time interval is triggered (see

FIG. 2, e), the signal from which through the logic circuit OR 34 enters the counting input of the pulse counter 33 and transfers it to state I. The signal from the pulse counter acts on the decoder 35, in accordance with

with which the latter at time 4 generates a signal that resets the average decade of the pulse counter of block 10, and sets its younger decade to the full state, which corresponds to the discreteness of the average decade 10 h.

Thus, at time / 2, the mid-decade of the counter is open for synchronization pulses, and the low and high are closed. The reference discriminator unit 7 returns to the initial state. With the arrival of sync pulses, the determination of the established level is performed in steps with a discreteness of 10 / g of the average decade. With an increase in the observatory level at time ts, the originating discriminator is triggered again and the described processes are repeated with the only difference that the pulse counter 33 is set to the state P. Pulse from the decoder 35 at the time moment

4 resets the lower decade of the pulse counter of block 10, the lower decade is open for sync pulses, and the high and low are closed. With the advent of clock pulses finding

the set level is produced in steps

with discreteness h of the lowest decade. When the set level is exceeded at time 4, the originating discriminator is triggered again, and through logic OR 31 translates into state III a pulse counter 33, which acts on the decoder 35. As a result, the latter generates a signal that transmits through logic AND 31 trigger 30 memory ti in reverse state. An impulse from the output of the memory trigger opens the inputs of the decades of the counter, the input to block 10, the digital time meter. -Process-BS measurement of the time interval from the found start of the measurement to the end of the measurement is carried out in the same way. By finding the set level corresponding to the end of the measured time interval, by means of the signal from the decoder 35, corresponding to the pulse from the counter 33, which is in state III, the memory trigger 30 through the logic circuit 32 is transferred to the measurement start state, and the pulse c its second output opens the inputs of the decades of the pulse counter of the unit 10, corresponding to the search for the start of the measurement. The same pulse stops the meter. Thus, the introduction of an additional read discretionary control unit makes it possible to roughly find the required level with discrete

100 L, and then more accurately read with a resolution of 10 / g and h. This greatly improves the speed of the device, i.e., the measurement time of the parameter is reduced without degrading the measurement accuracy. For example, when building a device using three-decade counters, the measurement time is reduced by an average of 60 times.

Claims (2)

1. Self-tuning systems. Handbook ed. Chinaev P. I. Kiev, “Iaukova Dumka, 1969, p. 331. 2. USSR author's certificate L 359639, cl. G 05В 23/02, 14.03.72. 300h200h ypoSeM TH i r-h0 8bi.duci -f. 0 f-y T Jl FIG. 2