JPS61165164A - 同期化割込み制御回路 - Google Patents

同期化割込み制御回路

Info

Publication number
JPS61165164A
JPS61165164A JP59276368A JP27636884A JPS61165164A JP S61165164 A JPS61165164 A JP S61165164A JP 59276368 A JP59276368 A JP 59276368A JP 27636884 A JP27636884 A JP 27636884A JP S61165164 A JPS61165164 A JP S61165164A
Authority
JP
Japan
Prior art keywords
interrupt
mcu
control unit
counter
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59276368A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0370266B2 (enrdf_load_stackoverflow
Inventor
Shigeru Nagasawa
長沢　茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59276368A priority Critical patent/JPS61165164A/ja
Publication of JPS61165164A publication Critical patent/JPS61165164A/ja
Publication of JPH0370266B2 publication Critical patent/JPH0370266B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP59276368A 1984-12-28 1984-12-28 同期化割込み制御回路 Granted JPS61165164A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59276368A JPS61165164A (ja) 1984-12-28 1984-12-28 同期化割込み制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59276368A JPS61165164A (ja) 1984-12-28 1984-12-28 同期化割込み制御回路

Publications (2)

Publication Number Publication Date
JPS61165164A true JPS61165164A (ja) 1986-07-25
JPH0370266B2 JPH0370266B2 (enrdf_load_stackoverflow) 1991-11-07

Family

ID=17568454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59276368A Granted JPS61165164A (ja) 1984-12-28 1984-12-28 同期化割込み制御回路

Country Status (1)

Country Link
JP (1) JPS61165164A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0370266B2 (enrdf_load_stackoverflow) 1991-11-07

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