JPS61161548A - Data processor - Google Patents

Abstract

PURPOSE:To facilitate supervision of a logical space by giving logical addresses of another process to read or write data from or in memory cells on a main memory corresponding to them since one process inputs the discrimination name of another process. CONSTITUTION:The logical address indicated by an address register 2 is converted to a storage position on a main memory 1 by an address converting unit 3. An another process address converting unit 6 reads out the value in a process control block indicated by a process name converting unit 5 and stores this value and converts a logical address of another process to a storage position on the main memory 1. The logical address on the logical space in another process is stored in an another process address register 7. The output of the address converting unit 3 and that of the another process address converting unit 6 are selected by a selector 8 and are inputted to the main memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing apparatus equipped with means for monitoring and changing the states of processes other than itself in a multi-process computer system.

(Prior art and its problems) Programs that run on computers often cause errors even if they are carefully designed and developed. There are debugger programs and trace programs that track errors while actually running programs that cause errors in order to eliminate program bugs. We will call these programs the visual subsystem.

The general way to create a monitoring subsystem in a multi-process computer system is to have the target program and the program to be monitored run in separate processes, and then control the status of the process that executes the target program on the side of the monitoring process. The idea is to do so.

A multi-process computer system that has a separate segment table for each process as architectural support for a memory management unit that supports the realization of a multi-process mechanism, and has a mechanism that stores the segment table of the running process in a segment memory managed by hardware. has traditionally existed. This computer system is effective in improving computer performance because it can quickly calculate addresses from logical addresses that appear in a program to real addresses in main memory (from 'M System/370 Pr1n
ciplesof 0operation” 8th E
dition (Mar, 1981)).

In such a computer system, there is no means to input a logical address in the logical space of another process and read out a corresponding memory cell in the main memory. Therefore, a situation in which one process stealthly views the logical space of another process cannot occur, which is effective in protecting user privacy.

However, if you try to build a visual subsystem on such a computer system, there is no way to read the corresponding memory cell in the main memory by inputting a logical address in the logical space of another process, so the visual subsystem In the design of the system, there was a drawback that it was not possible to use a two-process construction method using a multi-process mechanism.

In addition, a method using the multi-process mechanism described above can be used in a trace program if a reading means is provided, but it would be very convenient for a debugger program to have a function that can also rewrite the state information of other processes. Therefore, in order to design a visual subsystem, it is necessary to have the ability to read and write memory cells in the corresponding main memory by inputting logical addresses of other processes.

Therefore, an object of the present invention is to designate a specific process by inputting the identifier of another process in the program of a certain process, and pass the logical address of the other process. To provide a data processing device equipped with a read/write operation means for another process space, capable of performing address conversion as an address of a real address, and reading and writing the value of a converted real address in a memory cell on a main memory. It is in.

(Means for Solving the Problems) Means provided by the present invention for solving the above-mentioned problems is a data processing device for a multi-process computer system in which each process has a different logical space. means for decoding a first instruction declaring that the second process will access a logical space of a second process; and means for having a logical address of the second process as an operand and reading a value of a memory cell pointed to by the logical address. means for decoding a requested second instruction, an other process data register, and a logical address of the second process as an operand, and a request to write the value of the other process data register into a memory cell pointed to by the logical address. a main memory; an address register indicating a logical address in the logical space of the first process; and converting the logical address indicated by the address register into a physical address on the main memory. an address translation unit for translation, an instruction register for instructing execution of a program, and an address translation unit for receiving the identification name of the second process, which is passed as an input together with the instruction when the first instruction is completely decoded, and relating to the second process. A process name conversion unit outputs the location of the process control block that holds information, and the value in the process control block specified by this process name conversion unit is read from the main memory and stored. an other process address conversion unit that converts a logical address in the logical space in the second process to a storage location in the main memory when the second or third instruction is completely decoded; The other process address register stores a logical address passed as an operand of the other process address register, and the selector selects the output from the address translation unit and the output from the other process address translation unit according to an instruction.

(Function) The present invention solves the problems of the prior art by the above-mentioned means.The present invention will now be described in detail.

There are two processes; the process that monitors the logical space of another process is called the monitoring process (the first process described above), and the process that is monitored is called the target process (the second process described above). I'll decide. It is also assumed that the viewing process has an identifier of the target process.

FIG. 3 is a conceptual diagram of the present invention.

First, the monitoring process passes the target process identifier to the process name conversion unit 101 as an input. The process control block 102 stores the identifiers of all processes and their status information for each process.The process name conversion unit 101 stores the correspondence between the position of the process control block 102 in the logical space and the identifier. is held. All process control blocks exist in a logical space common to all processes. The process name conversion unit 101 is
A process control block 102 corresponding to the passed identifier is found, and information on the base address of one or more segments constituting the logical space of the process is stored in the other process address conversion unit 103 from among the process control blocks 102. . Then, when the monitoring process wants to read the value of a certain address in the logical space of the target process, the monitoring process passes the logical address as an input to the other process address conversion unit 1034. The process address conversion unit 103 converts the main memory 1 into the logical address of the target process rather than that of the monitoring process.
The value of the memory cell at the real address on the main memory 104 is read out, and the value of that memory cell is output.

Therefore, it is possible to read the value of a memory cell pointed to by a logical address of another process from within the program of one process, and this can be used to create a subsystem in which one process acts as a monitoring/measuring process for another process. It can be made.

Further, when the monitoring process wants to write a value to a certain address in the logical space of the target process, the monitoring process passes the logical address as an input to the other process address conversion unit 103, and the other process data register 1
When data to be written is stored in 05, the same address conversion process as when reading is performed, and other process data register 1 is stored in the corresponding memory cell on main memory 104.
A value of 05 is written.

Therefore, by using this function, it is possible to construct a debugger program that requires monitoring and manipulating state information in the logical space of other processes from within the program of a process.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The data processing device shown in this figure has a main memory 1 for storing instructions, data, etc., and an address indicating a logical address in a logical space of a certain process. a register 2, an address conversion unit 3 that converts the logical address indicated by the address register 2 to a storage location on the main memory 1, an instruction register 4 that instructs program execution, and a certain logic in the logical space of another process. When the instruction to read (the above-mentioned second instruction) or write to the memory cell pointed to by the address (the above-mentioned third instruction) is decoded, the identification name of the above-mentioned other process can be passed as an input. A process name conversion unit 5 receives and outputs the location of the process control block of the above-mentioned different process, and reads out the value in the process control block specified by the process name conversion unit 5 from the main memory 1 and stores it. , when there is a request to read or write a specific logical address in the other process using another instruction (that is, when the instruction to read or write can be decoded), By inputting the logical address on the logical space, the logical address of the above-mentioned separate process is stored in the main memory 1.
The other process address conversion unit 6 converts to the above storage location, the other process address register 7 stores the logical address on the logical space in the above separate process, and the output from the address conversion unit 3 and the other process address conversion unit 6. a selector 8 that selects the output of the output according to a command; and a process data register 10 that stores the value to be written when the above request is a write request.
and a control circuit 9 for controlling instruction retrieval, instruction code determination, and processing specified by the above instructions.

Program operations are carried out via the data bus 21 in the main memory 1.
The instructions are sequentially sent to the instruction register 4 and executed.

When the control circuit 9 determines that the instruction food stored in the instruction register 4 is an instruction (the above-mentioned first instruction) that uniquely specifies the other process for observing the state of the other process, first, I! The process name conversion unit 5 takes in the identification name input via 22. The process name conversion unit 5 is composed of a register file containing a number of registers sufficiently larger than the total number of processes existing in the system, and the identification name input via 1122 specifies one of the register files. The contents of the register designated by line 22 can be output to line 23.

The output of the line 23 indicates the start address of the process control block of the other process, and is taken into the address register 2, converted to a real address by the address conversion unit 3, and the line 24 is selected by the selector 8 and stored in the main memory. 1, and information of one or more segments located a fixed length away from that address is taken into the other process address conversion unit 6 via the data bus 21. The steps up to this point are the processing of the command (the first command described above) that uniquely specifies the other process.

When the control circuit 9 determines that the instruction food stored in the instruction register 4 is an instruction (the above-mentioned second instruction) to read the value of the logical address in the logical space of the other process, the other process address register 7 is first set. The address in the logical space of the other process that has been set is input to the other process address conversion unit 6 via the gland 26, and the address constituting the logical space of the other process that has already been set in the other process address conversion unit 6 is input. Adding the information eliminates address translation for other processes. The real address obtained therefrom is output to the line 25, and the selector 8 selects the side of the line 25 to be input to the main memory 1. The main memory 1 stores the value of the real address indicated by the gland 25 on the data bus 2.
Output to 1.

FIG. 2 is a block diagram showing a specific example of the other-process address conversion unit 6. In the logical space of each process, there are registers 33, which exist in the number of different segment types for each process, such as work area segments. 3
4, 35, an arithmetic unit 32 that performs binary addition, a register 33 that stores line 27, a selector 36 that selects 34, 35, a selector 37 that selects the output of these registers, and a logical address of line 26. and a segment register 30 that stores the segment designation section of the segment register 30. In this specific example, there are three different segment types for each process, which correspond to registers 33, 34, and 35.

In processing an instruction that uniquely specifies another process, each base value of a different segment for each process is sequentially sent to the register 33 from the process control block of the other process.
, 34 and 35.

Furthermore, in processing the instruction (the second instruction described above) that measures the value of the logical address on the logical space of another process, when the logical address on the logical space of the other process is input via line 26, the value of the logical address The segment specification part of is stored in the segment register 30, the value of the segment register 30 is decoded by the control circuit 9, and the register holding the value of the corresponding segment among the registers 33, 34, and 35 is selected by the selector 37. The value of the line 31, from which the selected value is output, and the address within the segment among the logical addresses of the input 26 are added together by the arithmetic unit 32, and the result becomes the output 25.

The steps up to this point are processing for an instruction to read a memory cell pointed to by a certain logical address in the logical space of another process.

When the control circuit 9 determines that the instruction food stored in the instruction register 4 is an instruction to write a value to the memory cell pointed to by the logical address in the logical space of the other process (the third instruction mentioned above), a read instruction is executed. Similarly to the processing for , first, the address in the logical space of the other process that has been set in the other process address register 7 is input to the other process address conversion unit 6 via the II 26,
The address information of the other process, which has already been set in the other process address translation unit 6, and which constitutes the logical space of the other process is added up to perform the address translation of the other process. The real address obtained therefrom is output to the line 25, and the selector 8 selects the side of the line 25 to be input to the main memory 1. On the other hand, the data to be written has already been stored in the other process data register 10, and when the write command is decoded, the contents of the other process data register 10 can be output to the data bus 21, and the data determined by the other process address conversion unit 6 can be stored. The data is taken into the memory cell in the main memory 1 corresponding to the address.

The present invention has been described in detail using Examples above.

(Effects of the Invention) The data processing device of the present invention can be used in a computer system in which each process has a different logical space. When one process inputs the identification name of another process, it can read from or write to the memory cell in the main memory corresponding to that logical address by giving the logical address of the other process. It is extremely effective as a means of monitoring and operating. Therefore, using the present invention,
Monitoring subsystems such as tracer programs and debugger programs that effectively utilize the multi-process mechanism can be efficiently constructed.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the process address conversion unit 6 other than the one shown in FIG. FIG. 3 is a conceptual diagram for explaining a method of reading other process logical addresses in the invention. 1...Main memory, 2...Address register, 3...
・Address translation unit, 4...Instruction register, 5.
...Process name conversion unit, 6...Other process address conversion unit, 7...Also process address register, 8...Selector, 9...Control circuit, 10...
・Other process data registers, 21...data bus,
22 , 23 , 24 , 25 . 26, 27, 28, 31...data line, 30.
... Segment register, 32 ... Addition operator, 33
, 34.35...Register, 36, 37...Selector. Figure 1 Figure 2

Claims (1)

[Claims] In a data processing device for a multi-process computer system in which each process has a different logical space, means for decoding a first instruction that declares that a first process accesses a logical space of a second process; means for decoding a second instruction that has a logical address of a process as an operand and requests to read a value of a memory cell pointed to by the logical address, another process data register, and a logical address of the second process as an operand; means for decoding a third instruction requesting to write a value of the other process data register into a memory cell pointed to by the logical address, a main memory, and a logical address in the logical space of the first process; an address register, an address translation unit that converts a logical address indicated by the address register into a physical address on the main memory, an instruction register that instructs execution of a program, and an instruction that is used when the first instruction is decoded. a process name conversion unit that receives an identification name of the second process passed as an input and outputs the location of a process control block that holds information regarding the second process; and a process control instructed by the process name conversion unit. The value in the block is read from the main memory and stored, and when the second or third instruction is decoded, the logical address in the logical space during the second process is read out from the main memory. an other process address translation unit that converts into a storage location, another process address register that stores a logical address passed as an operand of the second or third instruction, and an output from the address translation unit and the other process address. A data processing device comprising a selector that selects an output from a conversion unit according to a command.