JPS61103259A - Data processing device - Google Patents

Abstract

PURPOSE:To obtain the value of a main memory for the logical address by designating a special process with an identifier of another process as an input in the program of a certain process and delivering a logical address of another process. CONSTITUTION:A monitoring process delivers the identifier of the object process as an input for a process name converting name converting unit 101. The unit 101 stores base address information of one segment or above composing a logical space of the process out of the process control block 102 corresponding to the identifier, to other process address converting unit 103. When the monitoring process desires to read an address value on the logical space of the object process and the logical address is delivered as an input to the unit 103, the address is converted to an actual address on a main memory 104 as the logical address of the object process. Thus, the value on the main memory to the logical address can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device equipped with means for monitoring the status of processes other than itself in a multi-process computer system.

(Prior art and its problems) Programs that run on computers often cause errors even if they are carefully designed and developed. There are debugger φ programs and trace programs that track errors while actually running programs that cause errors in order to eliminate program bugs. These programs will be referred to as the monitoring subsystem.

The general way to create a monitoring system in a multi-process computer system is to run the target program and the program to be monitored in separate processes, and then create a process that monitors the status of the process that executes the target program. It is controlled by the side.

A computer system has a separate segment table for each process as architectural support for the memory management unit that supports the realization of a multi-process mechanism, and also has a mechanism to store the segment table of the running process in the segment memory managed by hardware. This method is effective in improving computer performance because address calculation from a logical address that appears in a program to a real address in main memory can be performed at high speed. (For example, 'IBM System/37
0Principles of Qperatio
n” 8th Editi-on (Mar,
(1981) ) In such a computer system, there is no means for reading out the corresponding memory cell in the main memory by inputting a logical address in the logical space of another process. Therefore, it is possible for one process to secretly view the logical space of another process, so this is effective in terms of protecting user privacy. (However, if you try to build a monitoring subsystem on such a computer system, there is no way to input the logical address in the logical space of another process and read the corresponding memory cell in the main memory, so the monitoring subsystem's When designing, a multi-process mechanism was used to construct the system in two processes, which resulted in the disadvantage that the construction method could not be adopted.

(Object of the invention) The present invention eliminates such conventional drawbacks and
When a specific process is specified by inputting the identifier of another process in the program of the process, and the logical address ti of the other process is specified, address translation is performed using the logical address as an address in the logical space of the other process, An object of the present invention is to provide an entire data processing device equipped with a monitoring means capable of obtaining a value on a main memory pointed to by a converted real address.

(Structure of the Invention) The present invention provides a multi-process computer system in which each process has a different logical space, including a first instruction that declares that a certain process refers to the logical space of one other process, and A second instruction to read all the values of the physical address using the logical address of the process as input + all the preparations, the main memory, the address register indicating the logical address on the logical space of one process, and the above address register are used. an address translation unit that converts the indicated logical address to a storage location in main memory, an instruction register that directs program execution, and the value of a certain logical address between the logical space of one process and the logical 1 of another process. When the first instruction to read the above is decoded, the process name conversion receives the identification name of the other process passed as an input together with that instruction, and outputs the position a of the process control block that holds information regarding the other process. The value in the process control block specified by the 07" process name conversion unit is read from the raw memory and stored, and the second instruction specifies the specific logical address of the other process. When there is a request to read out the other process, an other process address conversion unit converts the logical address of the other process to a storage location on the main memory by inputting the logical address above the logical 9 in the other process, and another process an other process address register that stores a logical address on a logical space within the internal process, a selector that selects the output from the address conversion unit and the output from the other process address conversion unit according to an instruction, and an instruction fetching, instruction code determination, and the above-mentioned instruction. This is a data processing device consisting of a control circuit that controls processing defined by .

(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-described configuration. Next, the present invention will be explained in detail.

There are two processes, and the process that monitors the logical space of other processes is called the monitoring process, and the process that is monitored is called the target process.

Oh, look at me. Yaniyu, target o. Yani. □Assume that you have 11 children.

FIG. 3 is a conceptual diagram of the present invention.

First, the monitoring process passes the target process's identifier to the process name conversion unit as an input.

The process name conversion unit 101 maintains the correspondence between the identifiers of all processes and the locations in the logical space of process control blocks that store status information for each process. All process control blocks exist in a logical space common to all processes. The process name conversion unit 101 converts the process control block 1 corresponding to the passed identifier.
02'f: Find and configure the logical space of the process from among the process control blocks 102.
Information on the base addresses of three or more segments is stored in the other process address conversion unit 103, and when the monitoring process wants to read the value of a certain address in the logical space of the target process, the monitoring process converts the other process address. When a logical address is passed as an input to the unit 103, the logical address is converted by the other process address conversion unit 103 into a real address on the main memory 104 as a logical address of the target process, not of the monitoring process. The value of the memory cell at the real address on the main memory 104 is read out, and the value of that memory cell is output.

It is possible to read out the value of a memory cell pointed to by a logical address of another process from within the program of one process, and by using this, one process becomes a monitoring/measurement process for another process. Create and vine.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The data processing device of the present invention shown in FIG. An address conversion unit 3 that converts a real address to a storage location in main memory, an instruction register 4 that instructs program execution, and an instruction that reads the value of a certain logical address in the logical space of another process are decoded. a process name conversion unit 5 which receives the identification name of the other process passed as its input and outputs the location of the process control block of the other process, and a process control block designated by the process name conversion unit 5; If there is a request to read a value from main memory and store it, and then read a specific logical address of the other process using another instruction,
Another process at-L/space conversion unit 6 converts the logical address of the other process into a storage location on the main memory l by inputting the logical address on the logical space of the other process; an other process address register 7 that stores the logical address of the other process address register 7, a selector 8 that selects the output from the address translation unit 3 and the output from the other process address translation unit 6 according to an instruction, and a It is composed of a control circuit 9 that controls prescribed processing.

Program operations are carried out via the data bus 21 to the main memory I7.
1 to instruction register 4 and executed.

When the control circuit 9 determines that the instruction code stored in the instruction register is an instruction that uniquely specifies the other process for observing the state of the other process, first the %lR22
The identification name input via the process name conversion unit 5
Import it with. The process name conversion unit 5 is composed of a register file containing a number of registers sufficiently larger than the total number of processes existing in the system, and the identification name input via the line 22 refers to one of the register files. It is treated as a specified cell address and is specified by line 22;
, 6 v) 21゜content power, it will be output to you.

The output on line 23 indicates the start space of the process control block of the other process, and is taken into the address register 2, converted to a real address by the address conversion unit 3, and the line 24 is selected by the selector 8, and the main address is output. Memory 10 inputs the information of one or more segments at a fixed distance from that address via data bus 21 and line 27 to other process address translators 22 and 22.

The steps up to this point are the processing of the command that uniquely specifies the other process.

When the control circuit 9 determines that the instruction code stored in the instruction register 4 is an instruction to read the value of the logical address in the logical space of the other process, first the logical space of the other process set in the other process address register 7 is read. The address inside is input to the other process address conversion unit 6 via the line 26, and the address information constituting the logical space of the other process that has already been set in the other process address conversion unit 6 is added up and the address is input to the other process address conversion unit 6.
1 address translation is not possible. The real address obtained therefrom is output to the line part, and the selector 8 selects the line part side and becomes input to the main memory IJ1. The main memory 1 outputs the value of the real address indicated by #iI4 to the data bus 21.

FIG. 2 is a block diagram showing an example of the detailed configuration of the other-process address translation unit 6. In the logical space of each process, there are as many different types of segments for each process, such as work area segments. registers 33, 34, and 35, and an operation lR that performs a binary 7JO operation.
register 33 for storing information from line 27.
34, 35, a selector 37 that selects the register output eN, and a segment register 30 that stores the segment designation part of the logical address of the line 26. In this embodiment, there are three different segment types for each process, which correspond to registers 34 and 35.

In processing an instruction that uniquely specifies another process, each pace value of a different segment for each process is sequentially stored in the register 33 in the process control block of the other process.
．． 34.35.

Furthermore, in processing an instruction to measure the value of a logical address on the logical space of another process, the logical address on the logical space of the other process is input by #26, and the segment specification part in the logical address is stored in segment register J. The value of the segment register 30 is decoded by the control circuit 9, the register holding the value of the corresponding segment is selected from among the registers 33, 34, and 35 by the selector 37, and the selected value is output # J31
The value of and the intra-segment address among the input logical addresses are added by the arithmetic unit 32, and the result becomes output 5.

The present invention has been described in detail using Examples above.

(Effects of the Invention) When a data processing device according to the present invention is used, in a multi-process computer system where each process has a different logical space, when one process inputs the identification name of another process, the logic of the allocation process is It is effective as a monitoring means in that when an address is given, the value on the main memory corresponding to that logical address can be read out.

The present invention has an applied effect in that a monitoring subsystem such as a tracer program that effectively utilizes a multi-process mechanism can be efficiently constructed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing an embodiment of the other-process address translation unit 6. FIG. 3 is a conceptual diagram for explaining a method of reading out another process logical address according to the present invention. In the figure, l is the main memory, 2#i address register, 3 is an address translation unit, 4 is an instruction register, 5 is a Grosse x name z translation unit, 6 is an other process address translation unit, and 7 is another process address register. 1. To 1 °“ゞ”′・ ゛1 Can control circuit・
21 +1 f −fi ′“′・22−23.24−
25-26, 27, and 31 are data lines, 30 is a segment register, 32i1 addition arithmetic unit, 33.34° spacing register, and 36.37 is a selector.

Claims (1)

[Claims] In a multi-process computer system where each process has a different logical space, the value of the physical address is read using the first instruction that declares that a process refers to the logical space of another process and the logical address of another process as input. A main memory, an address register indicating a logical address in the logical space of one process, and an address for converting the logical address indicated by the address register into a storage location on the main memory as a real address. a conversion unit, an instruction register for instructing program execution, and input together with the instruction when the first instruction for reading the value of a certain logical address on the logical space of one process from the logical space of another process is decoded; a process name conversion unit that receives an identification name of the other process passed as a process name and outputs the location of a process control block that holds information regarding the other process; It is read out from the main memory through the address register and the address translation unit and stored, and when there is a request to read out a specific logical address of the other process in the second instruction, the other process is read out and stored. converts the logical address of the other process into a storage location on the main memory as a real address by inputting the logical address in the logical space from the other process address register that stores the logical address in the logical space of the other process address register. a selector that selects an output from the address translation unit and an output from the other process address translation unit according to an instruction, and controls fetching of an instruction, determination of an instruction code, and processing specified by the instruction. A data processing device configured to include a control circuit that performs a control circuit.