JPS6177936A - Information processor - Google Patents

Abstract

PURPOSE:To increase the processing speed of an information processor by using all general-purpose registers with a single program or using some of these registers to switch tasks at a high speed. CONSTITUTION:The 32 pieces of general-purpose registers 1 (R0, R1...R31) are designated as operands, and five pieces of address registers 2 are used to holds said operands. Then registers R0...R15 are designated when the highest bit of the register 2 is equal to '0'; while registers R16...R31 are designated when said highest bit is equal to '1' respectively. This highest bit is applied to an exclusive OR circuit 4 together with the output of a mode FF3. The output of the circuit 4 is applied together with lower 4 bits of the register 2 for designation of the address of the register 1. Thus the circuit 4 functions as a subset address conversion mechanism. When the FF3 is equal to '0', the registers R0...R15 designated by a machine word instruction are set directly opposite to the general-purpose registers r0...r31 on a processor and receive accesses. When the FF3 is equal to '1', the highest bit of the register address is inverted. Then registers r16...r31 and r0...r15 are allocated to registers R0...R15 and R16...R31 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an information processing device, and relates to an information processing fc system that enables effective use of general-purpose registers in 9%.

(Prior Art) Generally, in an information processing device, a register called a general-purpose register is provided in a processor, and this register is used as a data storage location by a machine language instruction.

Using all general-purpose registers = 9, it can be accessed faster than storing all data in main memory, so assigning frequently used data to general-purpose registers has the advantage of increasing em processing speed. .

Ignoring the effects of erroneous task switching shown later, -
When considering only individual tasks, there are applications in which processing speed can be significantly improved if a large number of general-purpose registers can be used, but there are also applications in which the degree of performance improvement is low.

-1. In an information processing device equipped with general-purpose registers,
When switching tasks, it is necessary to save the contents of the general-purpose register in use to main memory or store it from main memory, and the processing time for this data transfer reduces the effectiveness of the general-purpose register. This is a contributing factor.

Regarding the frequency of task switching, there are environments in which a single task uses the processor for a long time and task switching hardly occurs. - There also exist environments in which the time it takes for each task to run continuously on the processor is extremely short.

Therefore, in the former case, the effect of using a large number of general-purpose registers 7 becomes noticeable when the fill of general-purpose register contents save/restore is low t, whereas in the latter case, the effect of Vc becomes noticeable. In order to improve performance, reducing the overhead of saving/restoring the contents of general-purpose registers is an important issue.

This method is especially useful in processors designed specifically for applications where high-speed task switching is important. There are some methods that allow tasks to be immediately switched without having to save/restore data to the main memory.

However, in conventional information processing devices such as this, if the entire processor is used for applications that do not require high-speed task switching, hardware such as multiple sets of internal registers is wasted. There are flaws.

In order to save on saving/restoring the contents of general-purpose registers, define the general-purpose registers that can be used in each mode in advance and do not use the others.VC
Technique 9: There are also methods to prevent general-purpose registers from being used in multiple modes. However, in this conventional information processing device, it is necessary to determine the general-purpose registers that can be used by the program from the time the program is created. There is a drawback that the degree of freedom of the program is limited because it is necessary to complete seven tasks, and once released, the friend program can only be used for that task. Particularly in systems where stack pointers, argument pointers, etc. are assigned to fixed general-purpose registers, all programs are forced to specify the same general-purpose registers. There is a drawback that restoration is required and the effect of allocating to each task is reduced.

(Objective of the Invention) The first object of the present invention is that by providing a processor with a subset address translation mechanism, all general-purpose registers can be used from one program, and only a part of the general-purpose registers can be fully used. An object of the present invention is to provide an information processing device that can perform task switching at high speed and improve processing speed without saving/restoring the contents of general-purpose registers in a plurality of tasks.

A second object of the present invention is to use a subset address conversion mechanism (ICL) provided in a processor to convert general-purpose registers specified by machine language instructions of a program into hardware according to the subset selection mode at the time the program is being executed. to be assigned to a general-purpose register on the processor = 9
, at the time of program installation, each program does not need to be aware of the subset that is actually allocated during execution, increasing the flexibility of the program, and special registers that are fixedly allocated as part of general-purpose registers. To provide an information processing device that can improve the effective use of general-purpose registers by eliminating the need for converting and saving/restoring the general-purpose register addresses on an actual processor in subset units even if all addresses of the same general-purpose register are specified in a program. To do [6ru.

A third object of the present invention is to enable the mixed use of programs that use only a subset belonging to the basic mode of general-purpose registers and programs that also use subsets other than the basic mode, and to save and restore the contents of a minimum number of registers. We will provide all information processing equipment that allows switching between these tasks.

(Bottom of the Invention) The device of the present invention includes a general-purpose register provided in a processor consisting of a plurality of subsets, a subset designation holding means for holding all subset designations of a ratio register designated by one machine language instruction, and a mode data writing/holding means for holding data specified by the mode meeting, and all addresses of subsets of the general-purpose registers provided in the processor, corresponding to the held mode data; Subset address conversion means for converting into a specified address; basic mode data storage means for saving all contents of registers belonging to the subset in basic mode when the subset is used in a mode other than basic mode; and a task for identifying all tasks being executed. and task identifier holding means for holding an identifier for each subset selection mode.

Whether said subset was used in other than basic mode?
a subset usage status information holding unit that holds information for each all-subset selection mode; a task control block that holds sag set specification information specified by the task identifier holding unit VC and specified for the subset to be used in addition to the basic mode; When switching the selection mode, the information held in the subset usage information holding means indicates that the subset of the basic mode of the subset selection mode to be switched to the new one is being used in another subset selection mode in a mode other than the basic mode. When it indicates that the subset selection mode to be newly switched to is the same as the subset selection mode switching means which reads out all the contents of the registers belonging to the basic mode subset of the basic mode to be switched from the basic mode data storage means and restores the corresponding register vc. When switching tasks in subset selection mode! If the sag set specification information of the task control block corresponding to the task to be executed specifies a subset to be used in addition to the basic mode, and the information held in the subset usage information holding means is The number of subsets used in modes other than the basic mode is 1.The sub-sets used in modes other than the basic mode belong to the corresponding subset of the basic mode data collection means in the Togi VC that shows the basic mode. A task switching means for updating the contents of the register NI and updating the information t in the subset usage information holding means to switch tasks;
It consists of:

(Example) Next, an example of the present invention will be described in detail with reference to the first page.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, the processor is divided into K 32 general-purpose registers (r6, rl, . . . r31Vt, each consisting of two subsets of 16 registers).

In this embodiment, at least a part of the machine language instruction can specify 32 general-purpose registers (Ro, R+, . . . R31) as the operand. A 5-bit address register 2 is provided to hold the addresses of 32 general-purpose registers designated by machine language instructions. The most significant bit is specified by a machine language instruction and specifies a subset of the ratio register. HRo-Rtst
", -1" Throat IcUR16~Rstt- Specify. This most significant bit is applied to the exclusive OR circuit 4 together with the output of the mode 7 lip flop flag 3, which is provided to maintain the subset selection mode 7, and the output is applied to the general register 1 along with the lower 4 bits of the address register 2.
applied for addressing. That is, the exclusive OR circuit 4 serves as a subset address conversion mechanism that converts a sub-ceratome specified sound processor specified by a machine language instruction into a subset address of a general-purpose register of the sound processor.

Nine, two machine language instructions are provided to set the subset selection mode, all standard mode, and back-of-the-box mode. By this machine language instruction, the mode 7 lip 70 lip 3
mode setting is performed.

Here, R15 is used as a light stack register, and R15 is a frame pointer to indicate the local variable area of the called procedure. It is assumed that R13 is fixedly allocated as a register for holding an archument pointer for indicating money.

Also, the specified range of general-purpose registers in machine language instructions is RO""
When the specified range is within R15, it is called using a basic mode subset, and when the specified range extends beyond R16, it is called using an extended mode subset.

A mode control table 5 is prepared to hold control information in the standard mode and the secret mode. This mode control table 5 has two entries corresponding to the general mode and the secret mode. Each entry has a ninth field PTR which holds the identifier of the task currently executing in the corresponding mode, and a subset of the basic mode in the corresponding mode, i.e. RIo to R15, is an extended mode of the other modes. It has a defined flag field Fi indicating whether it has been used.

Furthermore, when each subcent is used in the extended mode, a tth save area 6 is prepared for saving the contents of the general-purpose registers used for the subset in the original basic mode.

In addition to conventional task status information such as the task control block 'I'CBhij provided corresponding to each task (Th) and the current instruction counter, whether this task uses registers other than the basic mode, that is, RI6 to FLsxk. Extended mode bit E2 is used as subset designation information indicating whether
Motsu. A value of ``0'' in the extended mode bit E indicates that the task uses only a subset of the basic mode;
1# indicates money to be spent after 16.

Next, the operation in this embodiment will be explained.

When the subset selection mode is the standard mode, that is, the mode setting machine language command is set to the value '
The register address specified by the machine language instruction b is applied to general-purpose register 1 as is. Therefore, 7tR◇, R1,...R31T'S specified by machine language instructions are directly transferred to general-purpose registers ro, rr+ on the processor.
... rl1 VC is associated and access is performed.

When the subset selection mode is the hidden mode, that is, the machine language instruction for mode setting is 1p mode 7 rig 7 otsu 7" 3
When the 7bL value is '''11, the most significant bit of the register address specified by the machine language instruction specifying the register is inverted and applied to general register 1 as an address.In other words, for the specification of Ro to RIS, The registers from r16 to rss t of the processor are from R16 to R3.
For a specification of 1, registers from 0 to r15 of the processor are allocated VC7. Therefore, if the task executed in each subset selection mode is the basic mode, that is, the program selects registers from Ro to RIS. In the standard mode, the general-purpose registers rQ to rtst of the processor are used, and in the hidden mode, t'X
Registers from r1@ to rst will be used.

Next, switching of subsets in this embodiment.

Task switching will be explained in Section 2.

In this embodiment, it is assumed that a normal user's program is executed in the standard mode, and only special input/output interrupt processing is executed in the secret mode. Some tasks executed in standard mode use only a subset of basic mode, while others also use extended mode.

- It is assumed that a program executed in secret mode uses only a subset of the basic mode.◇ If the special input/output interrupt occurs while the program is running in standard mode, the special input/output interrupt When the processing for the output interrupt is completed, the subset selection mode switching mechanism is activated and the next operation is performed.

First, the task switching mechanism is activated and the next rollout operation is performed.

That is, whether the currently executing task is using extended mode sub-selection mode or not.
Bit vcLr) is checked. If this is "1", that is, if it is being used, the contents of the corresponding register are stored in the register save area of the task control block. If the E bit is O, VC2 and C are not processed.

Next, the 10-gram state word on the processor (which includes:
Occurrence of overflow, carry, etc. after instruction execution? The contents of the modified program counter (including flags 1, etc. shown) are also stored in the corresponding save area of the task control block.

After the above roll 7 act processing is completed, the next processing is all performed at 7t6.

Check the flag field F=2 of the mode control table 5 corresponding to the mode to be switched to the new 7t+. When this is 11#, that is, when the subset of the basic mode in the subset selection mode is used in the subset of another mode, , contents t of the corresponding subset of evacuation area 6
-a is output, stored in general-purpose register I, restores the entire contents of the basic mode subset in this subset selection mode, and resets the flag field F'kO.

If F is O, the contents of the basic mode subset are retained and remain t, so the above process is not performed immediately.

Next, a machine language instruction for switching the subset selection mode to another mode is executed, and after that, the task switching mechanism is activated. The task switching mechanism performs the following task roll-in processing upon startup from the subset switching mechanism. That is, the current sub1'-PTR of the mode control table 5 for each set selection mode.
Check the extended mode pit E of the task control block indicated by field and if it is 1, set the 7 lag F'kl of mode control table 5 corresponding to the previous subset selection mode that is different from the current subset selection mode.
In that case, the basic mode subset of the previous subset selection mode (corresponding to the extended mode subset 1m of the current subset selection mode) has not been saved yet, so save it to the subset corresponding to save area 60 and save it. Then, the contents of the subset corresponding to the extended mode subset of the current subset selection mode saved on the task control block are restored to the subset t-general register 1, and the 7-lag pic-i of the previous subset selection mode is restored. Make seven sets.

If the flag F is '1', the VC has already been saved, so the above process is not necessary.

When the extended mode bit E is '0', there is no need to restore the subset corresponding to the extended mode.

Task switching within the same subset selection mode is performed as follows.

That is, first, all tasks to be executed next are determined.

If this is different from the currently executing task, the VC saves the state of the currently executing task to the save area of the corresponding task control block. This process is similar to the rollout process when switching the subset described above, except that general-purpose registers of the basic mode subset are also saved. That is, in this case, along with the program status word and program counter, the basic mode subcellar 1ci
The contents of the general-purpose registers specified in ii are also saved. Furthermore, at this time, the extension bit Et of the task control block is checked and if this is 1#, the contents of the subset corresponding to the extension mode are also saved in the task control block.

After the above rollout process is completed, all pointers to the task control blocks of the tasks to be executed in the new batch are set in the PTR field of the entry in the mode control table 5 corresponding to the current subset selection mode, and then, Perform on the next roll-in process.

That is, first, the contents of the general-purpose registers belonging to the subset of the basic mode are stored, and then the same process as the roll-in process when switching the subset described above is performed in line 5. This is shown in FIG. 2(b). .

In this embodiment, a set of 32 general-purpose registers t
- 616 registers, but the present invention can reduce the number of registers in one set, ? It is not limited to the number of pushets.

Matrix 5 In this embodiment, it is assumed that a specific register such as a specific stack register is allocated to a general-purpose register, but it is not necessarily necessary to use this L5 equation. However, in that case, it is necessary to save/restore the contents of these specific registers every time the register selection mode is switched.

In the explanation of this embodiment, for the sake of simplicity, the details of the task switching mechanism, the detailed implementation method of the subset switching mechanism, the detailed structure of the task control block, etc. are omitted. This can be realized in the same way as equation 1.

(Effect of the invention) By providing a subset address translation mechanism in the processor of the T/C of the present invention, it is possible to use all the general-purpose registers from 91 Vc engineering programs, and it is possible to use only a part of the registers for comparison. It is possible to perform task switching at high speed without having to save/restore the contents of general-purpose registers among multiple tasks, thereby improving the effective use of general-purpose registers and increasing processing speed.

Furthermore, it is possible to mix programs that use only the basic mode subset of general-purpose registers with programs that also use non-basic mode subsets, and to switch between these tasks by saving and restoring the contents of the registers to a minimum, increasing processing speed. The effect is that it can improve

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
), (b) is a flowchart for the operation of 1a. 1...General-purpose register, 2...Address register, 3
. . . Mode 7 log frog, 4 . . . Exclusive OR circuit, 5 . . . Mode control table, 6 . . . Save area. TCBi, TCBj...Task control block. No1 dent

Claims (1)

[Scope of Claims] General-purpose registers provided in a processor and consisting of a plurality of subsets; subset designation holding means for holding subset designations of the general-purpose registers designated by machine language instructions; and writing data designating a subset selection mode. mode data writing and holding means for holding; and subset address conversion means for converting the held subset designation into address data of a subset of general-purpose registers provided in the processor in accordance with the held mode data; basic mode data storage means for storing the contents of registers belonging to the subset in basic mode when the subset is used in a mode other than basic mode; and a task for holding a task identifier for identifying the task being executed for each subset selection mode. an identifier holding means; a subset usage information holding means for holding information indicating whether or not the subset is used in a mode other than the basic mode for each subset selection mode; a task control block that holds subset specifying information that specifies a subset to be changed; and a task control block that holds subset specifying information that specifies a subset to be changed, and information held in the subset usage information holding means when switching the subset selection mode to another basic mode subset of the subset selection mode to be newly switched to. When the subset selection mode indicates that the mode is being used in a mode other than the basic mode, the content of the register belonging to the basic mode subset of the subset selection mode to be newly switched is read out from the basic mode data storage means and correspondingly executed. Subset selection mode switching means for restoring to the register, and subset specification information of the task control block corresponding to a newly executed task when switching tasks within the same subset selection mode specifying a subset to be used in addition to the basic mode. and when the information held in the subset usage information holding means indicates that the subset to be used in modes other than the basic mode has not yet been used in a mode other than the basic mode, the corresponding subset in the basic mode data storage means is and task switching means for storing the contents of registers belonging to subsets used in addition to the basic mode, updating information in the subset usage information holding means, and switching tasks. .