JPH02150923A - Program dividing controller - Google Patents

Abstract

PURPOSE:To assure the real time property of the processing and at the same time to design a program regardless of the limitation of the memory capacity by dividing a program into the independent tasks to hold them in a ROM and switching these tasks via an execution register. CONSTITUTION:A program is divided into the independent tasks TSK and stored in a program ROM 2 together with the task numbers. A high speed signal processor MPU 1 processes the task of the number designated for switch based on a sequence table ST held by an execution register EXCR 4. Then a job is started by a host to an EXCR controller 5, and the controller 5 increases the sequence numbers of the EXCR 4. Thus the MPU 1 outputs an end report to the host when the execution is through with the task of the final sequence number of the table ST. Thus it is possible to assure the real time property of the processing and also to design the program with no limitation of the memory capacity.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a device that uses a high-speed signal processing processor and divides and controls a variety of large-capacity programs that exceed the memory space of the processor in order to process these programs in real time. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

Conventionally, high-speed signal processing processors (hereinafter referred to as MPUs)
One way to have this MPU process multiple programs, each of which has its own program capacity, so that it falls within the accessible address range is to hold the aforementioned multiple programs on the host side, and then process them every time a processing request is made. To,
A method is used in which a program corresponding to a processing request is loaded from the host side into the program memory of the MPU and executed.

[Problem to be solved by the invention]

However, in such a conventional method, the MPU is stopped every time a program is loaded, which poses a problem when real-time processing is required. Therefore, the present invention provides a program division control device that divides a program into independent tasks, stores the entire program in a program ROM, and switches programs for executing tasks in order of sequence numbers in an execute register (EXCR). The object of the present invention is to enable the MPU to process a variety of large-capacity programs in real time by providing the following.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the device of the present invention provides addresses for predetermined lower digits (AO −
A first memory (such as program ROM 2) that stores individual programs (such as TSK, hereinafter referred to as tasks) for each area (such as All, hereinafter referred to as lower addresses), and tasks that should be executed continuously and sequentially among the tasks. (in the form of a sequence table ST, etc.) in the second memory (execute register 4, etc.) stored in this execution order (sequence number order, etc.) and in the processing start command (from a host computer, etc.) reading the task numbers in the second memory based on the order of storage;
Each time this reading is performed, the upper digit address corresponding to the lower digit (A1
an upper address output means (EXCR controller 5, multiplexer 3, etc.) that outputs an upper address such as 2 to A15 (hereinafter referred to as upper address); The CPU resets the program counter of the CPU (via the MPU reset signal R3T, etc.), causes the CPU to sequentially access the lower addresses of the first memory to execute the task, and ends the execution (via the MPUI processing request). and a task execution control means (such as the EXCR controller 5) which causes the upper address output means to read the next task number as described above.

[For use]

The address area of the program memory is divided into lower address areas that can be accessed by the MPU, and individual programs (tasks) are stored in these divided areas, and task numbers to be executed consecutively are executed in the order of their execution. Store in register (EXCR). Then, while the EXCR controller sequentially reads the task number in EXCR, it accesses the program memory at the upper address where this task is stored during this reading, and also causes the MPU to sequentially access the lower address area of the program memory from the first address. and execute the task. In this way, various large-capacity programs exceeding the address space of the MPU are continuously executed.

【Example】

The present invention will be described in detail below with reference to FIGS. 1 to 3. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a detailed configuration diagram of the main part of FIG. 1, and FIG. 3 is a diagram showing the flow of the operation of FIG. 1. In FIG. 1, 1 is a high-speed signal processing processor (MPU).
), 2 is a program ROM, 4 is an execute register (EXCR) that holds a sequence table ST for managing tasks in program ROM 2, 5 is a controller for this EXCR4, 3 is a program ROM
2 is a multiplexer that specifies a task, 8 is an internal bus, 9 is an external bus, 6 is a bus interface that connects this internal bus 8 and external bus 9, and 7 is MPUI data R.
It is AM. The program ROM 2 holds a program divided into independent tasks TSK, each assigned a task number, and the MPU 1 performs switching according to the sequence table ST held in the EXCR 4 of the designated task number. Executes task TSK processing. Here, the sequence table ST is a table in which task numbers are arranged in the order of the tasks TSK to be activated (that is, in the order of sequence numbers). Sequence table ST is created by a host not shown, and is connected to external bus 9 and EXC.
The data is loaded into the EXCR 4 via the R controller 5. Job startup is performed by the host on the EXCR controller 5, and when one task is completed, the MPU
I issues the next processing request to the EXCR controller 5. As a result, the controller 5 increments the sequence number of EXCR4. In this way, when the execution of the task with the final sequence number in the sequence table ST is completed, the MPUI is configured to issue a completion notification to the host. A detailed example of the configuration shown in FIG. 1 is shown in FIG. 2, and the flow of the operation shown in FIG. 1 is shown in FIG. To explain Figures 2 and 3, M
In this example, the PUI has a program memory space for dKW, and the program ROM 2 holds programs divided into dKW units, that is, 16 tasks TSK with task number values 0 to 15. Here, the lower 12 bits of the address of program ROM2 (AO-All)
is connected to the address line ALI of MPU1, and the upper 4 bits (A12 to A15) are connected to the multiplexer 3.
Connect to the address line AL2 of the address line AL2 for task designation,
The address of ROM2 is determined using all 16 bits. Task TSK is specified by EXC from the host via external bus 9.
By giving a sequence start command to the R controller 5, the signal TNO indicating the task number (value 0 in this example) stored in the area of sequence number 1 in the sequence table ST of EXCR4 is changed from EXCR4 to EXC.
It is output to the multiplexer 3 via the R controller 5. Therefore, the multiplexer 3 sends an upper address (A12 to A
15) to the ROM 2, and the task to be executed is determined. At the same time, an MPU reset signal R3T is applied from the EXCR controller 5 to the MPU 1, and a program counter (not shown) in the MPUI is initialized. When the specified task finishes processing in this way,
EXCR controller 5 via internal bus 8 from MPUI
It issues a request to start the next sequence to and increments the sequence number of EXCR4. When all sequences are completed, the EXCR controller 5 outputs a completion notification to the host side, and the process ends.

【Effect of the invention】

According to the present invention, in order to use a high-speed signal processing processor to process in real time a variety of large-capacity programs that exceed the memory space of the processor, the program is divided into independent tasks and held in the ROM, and the execution register is Since the program is processed by switching tasks, the entire program is held in the program ROM, and the task is changed in real time by the EXCR sequence, so real-time processing is guaranteed. In addition, it becomes possible to design programs without being restricted by memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the detailed configuration of the main parts of FIG. be. l: High-speed signal processing processor (MPU), 2 Niprogram ROM, 3: Multiplexer, 4: Execute register (EXCR), 5: EXCR controller, 6: Bus interface, 7: RAM, 8: Internal bus, 9: External bus ,TSK:Task,STNIJ-l
Stable, TNO: Task number signal, R3T:
MPU reset signal, AL1, L2 near address line, DB: data bar to A11: lower focus, AI2 to A15: upper bit. Jo 2 diagram

Claims (1)

[Scope of Claims] 1) Individual programs (hereinafter referred to as tasks) are stored in each area of addresses for prescribed lower digits (hereinafter referred to as lower addresses) each having a prescribed address space accessible by the CPU. a first memory; a second memory storing the numbers of the tasks to be executed sequentially among the tasks in the order of execution; and a second memory storing the task numbers in the second memory based on a processing start command. They are read in the order of storage, and each time the first
an upper address output means for outputting an address on the upper digit side corresponding to the lower digit (hereinafter referred to as the upper address) as an address indicating the position of the address area in which the task is stored in the memory; For each output, the first memory is accessed using this upper address, the program counter of the CPU is reset, and the lower addresses of the first memory are sequentially accessed by the CPU to execute the corresponding task. The present invention is characterized by comprising task execution control means that determines the end of execution and causes the upper address output means to read the next task number in the order as described above. Program division control device.