JPS6116088B2 - - Google Patents

Info

Publication number
JPS6116088B2
JPS6116088B2 JP56003382A JP338281A JPS6116088B2 JP S6116088 B2 JPS6116088 B2 JP S6116088B2 JP 56003382 A JP56003382 A JP 56003382A JP 338281 A JP338281 A JP 338281A JP S6116088 B2 JPS6116088 B2 JP S6116088B2
Authority
JP
Japan
Prior art keywords
input
output
signal
terminal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56003382A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57117027A (en
Inventor
Toshio Oora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56003382A priority Critical patent/JPS57117027A/ja
Priority to DE8282300157T priority patent/DE3265920D1/de
Priority to EP82300157A priority patent/EP0057511B1/en
Priority to US06/339,223 priority patent/US4470113A/en
Publication of JPS57117027A publication Critical patent/JPS57117027A/ja
Publication of JPS6116088B2 publication Critical patent/JPS6116088B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Microcomputers (AREA)
JP56003382A 1981-01-13 1981-01-13 Signal sending and receiving circuit Granted JPS57117027A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56003382A JPS57117027A (en) 1981-01-13 1981-01-13 Signal sending and receiving circuit
DE8282300157T DE3265920D1 (en) 1981-01-13 1982-01-12 Information processing unit
EP82300157A EP0057511B1 (en) 1981-01-13 1982-01-12 Information processing unit
US06/339,223 US4470113A (en) 1981-01-13 1982-01-13 Information processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56003382A JPS57117027A (en) 1981-01-13 1981-01-13 Signal sending and receiving circuit

Publications (2)

Publication Number Publication Date
JPS57117027A JPS57117027A (en) 1982-07-21
JPS6116088B2 true JPS6116088B2 (enExample) 1986-04-28

Family

ID=11555798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56003382A Granted JPS57117027A (en) 1981-01-13 1981-01-13 Signal sending and receiving circuit

Country Status (4)

Country Link
US (1) US4470113A (enExample)
EP (1) EP0057511B1 (enExample)
JP (1) JPS57117027A (enExample)
DE (1) DE3265920D1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6414368B1 (en) 1982-11-26 2002-07-02 Stmicroelectronics Limited Microcomputer with high density RAM on single chip
US5243698A (en) * 1982-11-26 1993-09-07 Inmos Limited Microcomputer
US4704678A (en) * 1982-11-26 1987-11-03 Inmos Limited Function set for a microcomputer
DE3247834A1 (de) * 1982-12-23 1984-06-28 Siemens AG, 1000 Berlin und 8000 München Schaltkreis-baustein
JP2500801B2 (ja) * 1983-09-21 1996-05-29 株式会社日立製作所 端末処理装置
US4594654A (en) * 1983-11-04 1986-06-10 Advanced Micro Devices, Inc. Circuit for controlling external bipolar buffers from an MOS peripheral device
JPS60171520A (ja) * 1984-02-16 1985-09-05 Nec Corp 大規模集積回路
US4912723A (en) * 1984-06-28 1990-03-27 Westinghouse Electric Corp. Multipurpose digital IC for communication and control network
FR2568035B1 (fr) * 1984-07-17 1989-06-02 Sagem Procede d'interconnexion de microprocesseurs
FR2569290B1 (fr) * 1984-08-14 1986-12-05 Trt Telecom Radio Electr Processeur pour le traitement de signal et structure de multitraitement hierarchisee comportant au moins un tel processeur
JPS625465A (ja) * 1985-07-01 1987-01-12 Akira Nakano 情報処理ユニツトおよびマルチ情報処理ユニツトシステム
US4729095A (en) * 1986-05-19 1988-03-01 Ncube Corporation Broadcast instruction for use in a high performance computer system
EP0247604B1 (en) * 1986-05-30 1994-08-03 Bull HN Information Systems Inc. Apparatus and method for interprocessor communication
US5101498A (en) * 1987-12-31 1992-03-31 Texas Instruments Incorporated Pin selectable multi-mode processor
US4943984A (en) * 1988-06-24 1990-07-24 International Business Machines Corporation Data processing system parallel data bus having a single oscillator clocking apparatus
CA1318406C (en) * 1988-07-25 1993-05-25 Anthony Gerard Gibart Programmable controller module identification system
US5214760A (en) * 1988-08-26 1993-05-25 Tektronix, Inc. Adaptable multiple port data buffer
KR0136594B1 (ko) * 1988-09-30 1998-10-01 미다 가쓰시게 단일칩 마이크로 컴퓨터
US5125080A (en) * 1989-11-13 1992-06-23 Chips And Technologies, Incorporated Logic support chip for AT-type computer with improved bus architecture
US5493723A (en) * 1990-11-06 1996-02-20 National Semiconductor Corporation Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits
JPH0520278A (ja) * 1991-07-11 1993-01-29 Nec Corp マイクロコンピユータ
US5485585A (en) * 1992-09-18 1996-01-16 International Business Machines Corporation Personal computer with alternate system controller and register for identifying active system controller
US5392407A (en) * 1992-12-24 1995-02-21 Ncr Corporation Multi-port processor with peripheral component interconnect port and rambus port
JP3904244B2 (ja) * 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
US5621800A (en) * 1994-11-01 1997-04-15 Motorola, Inc. Integrated circuit that performs multiple communication tasks
DE19625042B4 (de) * 1996-06-22 2007-08-30 BSH Bosch und Siemens Hausgeräte GmbH Steuer- bzw. Regelvorrichtung
JP5050909B2 (ja) * 2008-02-20 2012-10-17 富士通モバイルコミュニケーションズ株式会社 携帯端末

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3470542A (en) * 1967-03-17 1969-09-30 Wang Laboratories Modular system design
GB1467726A (en) * 1974-05-02 1977-03-23 Solartron Electronic Group Interfaces for data transmission systems
US4028663A (en) * 1974-06-05 1977-06-07 Bell Telephone Laboratories, Incorporated Digital computer arrangement for high speed memory access
US4124891A (en) * 1976-11-18 1978-11-07 Honeywell Information Systems Inc. Memory access system
US4174536A (en) * 1977-01-21 1979-11-13 Massachusetts Institute Of Technology Digital communications controller with firmware control
US4212080A (en) * 1978-06-05 1980-07-08 Milliken Walter C Data transmission control system
US4229791A (en) * 1978-10-25 1980-10-21 Digital Equipment Corporation Distributed arbitration circuitry for data processing system
EP0016523B1 (en) * 1979-02-13 1984-09-26 The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Data processing unit and data processing system comprising a plurality of such data processing units

Also Published As

Publication number Publication date
EP0057511A1 (en) 1982-08-11
EP0057511B1 (en) 1985-09-04
US4470113A (en) 1984-09-04
DE3265920D1 (en) 1985-10-10
JPS57117027A (en) 1982-07-21

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