JPS6116085B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to programmable logic controllers (hereinafter referred to as PLCs), and more particularly to techniques for solving problems associated with monitoring two-word instructions stored in user program memory. As is well known, in a general PLC such as a ladder diagram type, many instructions such as a load instruction, an AND instruction, and a store instruction are composed of an instruction code and an element number (input/output address), for example, a 16-bit number. It is also expressed by one word of the command word, which is one word. On the other hand, in the case of a timer instruction or a counter instruction, in addition to the instruction code and the element number representing the timer number or counter number, there is numerical data representing the set time in the timer command or the set count number in the counter command, so there is a limit. This cannot be expressed with a single word instruction for the number of bits given, and many
In PLC, timer instructions and counter instructions are expressed as two-word instructions defined as follows.

[Table] As shown above, the instruction code and element number are placed in the first word to unify the format with normal one-word instructions such as the load instruction mentioned above, and the numerical data mentioned above is placed in the second word. There is. Furthermore, when storing the two-word instruction in the user program memory, the two words constituting one instruction are stored successively in the address scanning direction in the order of the first word → second word. That is, when the first word containing the instruction code is stored at address (N), the numerical data of the second word is stored at the next address (N+1). Such a system configuration is advantageous in terms of memory utilization efficiency, and is extremely advantageous in terms of simplifying and speeding up the process of sequentially reading, decoding, and executing user instructions. Furthermore, as is well known, an extremely important design element for PLCs is to enable users to fully utilize them even without knowledge of computer-like signal processing technology. For example, a ladder diagram
PLCs have been devised in various ways to make programming easier based on ladder diagrams written with symbols such as contacts, relays, timers, and counters. The same goes for program monitoring; user instructions converted to machine language and stored in program memory are not simply displayed on the monitor in the form of binary or hexadecimal codes, but are directly linked to the original ladder diagram. Efforts have been made to display the ladder diagram by converting it back to the format shown below, or by restoring and displaying the ladder diagram on a CRT. In this type of PLC, each circuit element on the ladder diagram is programmed in a predetermined order, but the program monitor not only monitors all user instructions sequentially in the above order, but also monitors the circuit elements necessary during program execution. It is common practice to monitor only user commands related to
After monitoring a certain user command, it is also common practice to monitor user commands before and after it. Here, the above-mentioned two-word instruction monitor will be explained. In the program memory, two-word instructions are arranged in the address scanning direction in the order of the first word containing the instruction code → the second word containing numerical data.
When the monitor advances in the address scanning direction and the first word of the two-word command stored at address (N) is taken into the monitor control section, the monitor control section
There is no particular problem because it can be identified from the instruction code of the word that these are two-word instructions, and at the same time it can be seen that the numerical data of the second word is stored at the next address (N+1). However, when the monitor advances in the opposite direction to the address scanning direction, the numerical data of the second word in the two-word instruction is first taken into the monitor control section. At that time, the numerical data of the second word must be structured in such a way that it can be distinguished from an instruction word that includes an instruction code, such as the first word of a normal one-word instruction or two-word instruction. Numerical data cannot be recognized as numerical data, and correct two-word commands cannot be displayed on the monitor. Due to the above-mentioned necessity, the following measures have been conventionally taken in order to distinguish between the second numerical data in a two-word instruction and an instruction word containing an instruction code. (b) When one command word is made up of 16 bits, one specific bit is assigned as an identification bit to determine whether or not it is numerical data. (b) Do not use the instruction code area for numerical data by setting all bits in the area where the instruction code in the instruction word is to "0" for numerical data. In the case of (a) above, only 15 bits can be effectively used as an instruction word, and the number of types of instruction codes is halved. In the case of (b) above, the number of bits that can be effectively used as numerical data is significantly reduced, and the setting range of numerical data is narrowed. In any case, the ability of the PLC to distinguish between numerical data had to be significantly reduced. I would like to add that in the method (a) above,
By adding 1 bit to the instruction word length to make it 17 bits and using the added 1 bit as the above-mentioned identification bit, the actual instruction word length remains 16 bits and does not lead to a decrease in performance. However, when actually configuring a PLC circuit, the instruction word length cannot be determined freely, and is largely restricted by the circuit elements used. As is well known, computers and
PLC command words are 8, 16, 24, 36, ......
It is customary to have a bit configuration that is an integer multiple of , and this has great significance. For this reason, microprocessors (used as arithmetic control units, etc., which are the core of program execution) that are generally on the market,
A nonvolatile PROM (EPROM) used as a user program memory has a bit configuration of 8 bits. Therefore, for example, in a PLC system configured with 16-bit processing, even if you try to set the instruction word length to 16 + 1 = 17 bits as described above, PROMs with 17 bits per word are generally not available.
If you dare to use this method, you will need 24 bits per word.
PROM will be used, which means that 24-17=7 bits will be wasted. The present invention has been devised in view of the conventional problems described above, and its purpose is to transfer two-word instructions in the reverse direction without substantially reducing the instruction word length determined by the PROM used as the program memory. An object of the present invention is to provide a PLC that can easily distinguish between numerical data and other command words required when monitoring data. To achieve the above object, the present invention provides a volatile read/write decision signal memory (RAM) with at least the same number of words as the user program memory (PROM) and each word of which is at least 1 bit, which is addressed in parallel with the user program memory. As an initialization process before program execution, each instruction in the user program memory is read out in order, and it is determined one by one whether or not the numerical data is the second word of a two-word instruction. The judgment result is written to the corresponding address of the judgment signal memory, and at the time of program monitoring, it is simultaneously checked whether the instruction read from the user program memory is the numerical data of the second word constituting the two-word instruction. It is characterized in that the identification is made based on data read out from the judgment signal memory. Hereinafter, one embodiment of the present invention will be described in detail based on the drawings. The program execution operation of sequentially decoding and executing user instructions stored in the user program memory 1 is performed mainly by the arithmetic control unit 2, and the operation of monitoring the contents of the program memory 1 and various data during program execution is performed by the keyboard 3 and This is performed mainly by the monitor control unit 5 to which the display device 4 and the like are connected. When a program is executed, the program counter 6 is sequentially incremented by a step signal from the arithmetic control section 2, and the user program memory 1 is scanned for addresses using the output of the counter 6. As a result, the user instructions read out in order from the program memory 1 are temporarily stored in the instruction register 7 and supplied to the arithmetic control unit 2 and monitor control unit 5, and the data of the above-mentioned element numbers in the user instructions are input. It is input to the output memory 8 and is addressed. The arithmetic control unit 2 decodes user commands input through the instruction register 7, performs logical operations based on the input/output data (external input/output status) read from the input/output memory 8, and executes the logical operations. The well-known program execution process of writing the result into the input/output memory 8 is performed. Furthermore, before starting one round of address scanning of the program memory 1, the arithmetic control unit 2
An activation signal (not shown) is sent to the input/output circuit 9 to cause high-speed data transfer between the input/output circuit 9 and the input/output memory 8 (this is referred to as an input/output data update operation). In other words, by updating input/output data,
The logic states of a large number of external input signals applied to the input/output circuit 9 are respectively written into corresponding areas of the input/output memory 8, and each output data of the input/output memory 8 is set to the corresponding external output terminal. While the interrupt signal IL, which will be described later, is not applied to the arithmetic control unit 2 from the monitor control unit 5, the above-mentioned input/output data updating operation and program execution operation performs one round of address scanning of the program memory 1).
is repeated. Note that the arithmetic control section 2 outputs a scan end signal SE to the monitor control section 5 every time one round of address scanning is completed, and the monitor control section 5 receives this scan end signal and proceeds with the monitor control. By the way, in this embodiment, the user program memory 1 consists of a ROM with 16 bits per word, and the user instructions stored therein include normal one-word instructions as described above, as well as timer instructions and counter instructions. Contains two-word instructions. Of course, as mentioned above, the first word of the two-word instruction includes the instruction code, and the second word is numerical data. However, in the present invention, in order to distinguish between the numerical data of the second word in a two-word instruction and the instruction word containing other instruction codes, the data structure as described in (a) or (b) above is used. No countermeasures have been taken, and the entire 16-bit instruction word length is effectively used. Therefore, when the program memory 1 of the present invention is monitored from the direction opposite to the address scanning direction, the numerical data constituting the two-word instruction cannot be recognized as numerical data. This is solved with the following configuration. Reference numeral 9 denotes a discrimination signal memory having one bit per word, the same number of words as the program memory 1, and this memory 9 is addressed in parallel with the program memory 1 by the output of the program counter 6. In other words, each 1-bit storage area of the discrimination signal memory 1 is in one-to-one correspondence with each 16-bit command word of the program memory 1, and by the initialization process performed by the monitor control section 5 when the power is turned on,
A 1-bit determination signal indicating whether each instruction word in program memory 1 is numerical data constituting a two-word instruction is written to the corresponding address in memory 9. That is, the monitor control section 5 executes the initializer routine shown in the flowchart of FIG. 2 while interrupting the arithmetic control section 2 when the power is turned on. First, in step (1), the program counter 6 is reset and the address output is set to "0". In the next step (2), the user instruction addressed by the output of the program counter 6 and read out to the instruction register 7 is taken into the monitor control unit 5, and whether the user instruction is a one-word instruction or a two-word instruction (timer instruction) is read out. or the first word of a counter instruction) from the instruction code. If it is a one-word command, the program proceeds to step (3) and writes a discrimination signal "0" into the discrimination signal memory 9 addressed by the output of the program counter 6. Next, in step (4), the program counter 6 is incremented (incremented by 1), and in the next step (5), the program counter 6 is incremented.
Determine whether the output of has reached the end address,
If the final address has not been reached, step (2)
Returning to , it is determined whether the user instruction read from the next address of the program memory 1 is a one-word instruction or a two-word instruction. If the instruction code for the first word of the two-word instruction is detected in step (2) (the output of the program counter 6 at this time is N), proceed to step (6),
Write the discrimination signal "0" to the address (N) of the discrimination signal memory 9. In the next step (7), the program counter 6 is incremented and the address output is (N+
1). Program memory 1 address (N
+1) stores the numerical data of the second word constituting the two-word instruction. Therefore, in the next step (8), a discrimination signal "1" indicating that the data is numerical data is written into the discrimination signal memory 9 addressed by the output (N+1) of the program counter 6. Thereafter, the address is incremented in step (4) mentioned above, and it is determined in step (5) whether or not it is the final address. When the above operations are performed up to the final address,
The determination in step (5) is YES and this initializer routine ends. Then, in the discrimination signal memory 9, "1" is written in the address area corresponding to the numerical data of the two-word instruction stored in the program memory 1, and "0" is written in the areas corresponding to the other instruction words. is written. This initializer routine only performs one round of address scanning and does not perform any particularly sophisticated processing, so it can be executed in an extremely short time. When the initializer routine is completed, the interrupt to the arithmetic control unit 2 is canceled, and the above-described operations of updating input/output data and executing the program are performed. As is well known, monitoring during program execution involves (a) inputting a user instruction to be monitored, (b) inputting a storage address of the user instruction to be monitored, and (c) monitoring (a) or ( There are cases where a certain user command is monitored by b), and user commands at addresses before and after that command are monitored. The monitor control unit 5 receives the address output of the program counter 6 during program execution, user instructions sequentially read into the instruction register 7, input/output data output from the calculation control unit 2, calculation progress data, etc. In addition, predetermined monitor control is performed by interrupting the arithmetic control unit 2 at a predetermined timing, presetting an arbitrary address in the program counter 6, or performing operations such as incrementing or decrementing the program counter 6. This is the translation. At that time, especially in the monitoring operation (c) above, when monitoring a user instruction at an address before a certain user instruction being monitored, that is, when advancing the monitor in the opposite direction to the address scanning direction, the program counter 6 is Decrement instruction register 7
At the same time, a determination signal read from the determination signal memory 9 is received into the monitor control section 5 via the register 10,
Two user commands read simultaneously from this discrimination signal
It is recognized whether the numerical data is the second word constituting a word command. Then, if the discrimination signal is "0". The user command is monitored and processed as it is, and if the determination signal is "1", the user command (which is numerical data) is temporarily stored, and the program counter 6 is further decremented to store the numerical data. The corresponding first command word is read out and monitored. As explained in detail above, the PLC according to the present invention
In this case, a determination signal memory consisting of a volatile read/write RAM that is addressed in parallel with the user program memory is provided, and as an initialization process before program execution, it is determined whether each user command is numerical data of a two-word command or not. A discrimination signal indicating whether the Using the instruction word length to identify two-word instructions,
This solves the conventional problem of significantly reducing the actual functionality. As is well known, many RAMs used as discrimination signal memories with various bit configurations are on the market. Further, in the present invention, as an initialization process before program execution, each instruction in the user program memory is read out in order, and it is determined one by one whether or not the numerical data is the second word of a two-word instruction. Since the judgment result is written to the corresponding address of the above judgment signal memory,
There is no need for expensive non-volatile memory such as PROM or EPROM as the judgment signal memory; an inexpensive RAM is sufficient. Furthermore, when defining an instruction such as a 3-word instruction or a 4-word instruction, the number of bits in the discrimination signal memory is increased and it is determined whether the instruction word is the first instruction word containing the instruction code or the second word of a multi-word instruction. A discrimination signal for distinguishing between the third word of a multi-word instruction, the fourth word of a multi-word instruction, etc. may be stored in the discrimination signal memory in the initialization process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a programmable logic controller according to an embodiment of the present invention;
The figure is a flowchart of initialization processing. DESCRIPTION OF SYMBOLS 1... User program memory, 2... Arithmetic control section, 5... Monitor control section, 6... Program counter, 7... Discrimination signal memory.

Claims (1)

[Claims] 1. In a programmable logic controller in which a two-word instruction is defined as one type of user instruction, in which the first word contains an instruction code and an element number, and the second word contains numerical data; A volatile read/write determination signal memory having at least the same number of words as the memory and each word of which is at least 1 bit is provided so as to be addressed in parallel with the user program memory; as an initialization process before program execution,
Each instruction in the user program memory is read out in order, and each instruction is judged one by one whether it is the numerical data of the second word constituting a two-word instruction, and the judgment result is written to the corresponding address in the judgment signal memory. When the program is monitored, the instructions read from the user program memory constitute a two-word instruction.
A programmable logic controller characterized in that whether or not the numerical data is a word is identified based on data simultaneously read out from the determination signal memory.