JPS6160443B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a programmable logic controller (hereinafter referred to as PLC), and particularly relates to a programmable logic controller (PLC) in which the input/output circuits constituting the PLC are configured as a unit in a plurality of main units, and each main unit is This invention relates to a PLC that is structured into input/output subunits that handle a fixed number of inputs or outputs, and that allows the input/output circuits to be increased, decreased, or changed in subunit or main unit units according to the user's control specifications.

As is well known, a general PLC includes an input/output updating means that writes input data obtained from an input circuit to an input/output memory, reads output data stored in the input/output memory, and transfers it to the output circuit;
The input/output memory basically consists of a program execution means for processing the data stored in the input/output memory according to an arbitrarily set user program, and rewriting the data in the input/output memory based on the processing results. The output update operation and program execution operation are alternately repeated.

By the way, one of the selling points of this type of PLC is how flexibly it can respond to the user's control specifications. That is, the marketability of this type of PLC is greatly influenced by how flexibly the ratio of input points to output points and the total number of these points can be changed for each user.

FIG. 1 shows an example of a unit-type PLC developed by the applicant to meet the above-mentioned demands.

This PLC is configured so that a maximum of four main units MU-0 to MU-3 can be connected to one device.

The controller main unit CU is composed of a program memory PM, an input/output image memory IM, and a central processing unit CPU. and,
The central processing unit CPU has input/output image memory IM
The user program stored in the program memory PM is executed based on the input/output data stored in the input/output image memory IM, and the execution results are transferred to the input/output image memory IM.
At the same time, the data stored in the output data area of the input/output image memory IM is written to the external data bus
Each main unit MU-0~MU- through DBM
3, and each main unit MU-0~
It is configured to write the input data taken in from the MU-3 into the input data area of the input/output image memory IM.

Two bus lines (bus line ADS for subunit address, bus line DBM for external data) are extended from the central processing unit CPU, and four connectors ( 1st connector group) CN10~
CN-13 is provided, and four connectors (second connector group) CN-20 to CN-23 are also provided on the external data bus line DBM. And the aforementioned main unit MU-0~
MU-3 has each connector (CN-10,
CN-20) ~ (Connector CN-13, CN-2
3), it is configured so that it can be freely connected. In addition, connector CN-10 to connector CN
-13 indicates each decode line of the decoder DEC1 installed in the controller main unit CU.
US0 to US3 are supplied together with the bus line ADS. In addition, each main unit MU-0~
An internal data bus DBS is provided in the MU-3, and this internal data bus DBS is connected to the connector.
It is connected to the external data bus line DBM leading to the controller main unit CU mentioned above via the connectors CN-20 to CN-23, respectively. And on the internal data bus line DBS,
Four connectors CN-30 to CN-33 are provided, and these connectors CN are connected to subunits.
SU-0 to SU-3 are configured to be connectable.
Each of the subunits SU-0 to SU-3 is configured to handle eight external terminals T. Also, subunit SU(OUT) is configured as an output subunit, and subunit SU(IN)
is configured as an input subunit. Here, the output subunit is an interface circuit composed of a so-called output data latch circuit, etc., and the input subunit is a so-called I/V converter and a gate circuit provided on its output side. It is composed of
And for each connector CN-30 to CN-33,
Each decode line IS0 to IS3 of the decoder DEC2 connected to the connectors CN-10 to CN-13 is supplied.

Thus, connectors CN-10 to CN-13 are
As mentioned above, the controller main unit CU
Addresses are assigned by the output of decoder DEC1 in the connector CN-30~
CN-33 connects each decode line IS0 to IS0 of the decoder DEC2 built in each main unit MU.
Address assignment is done by IS3.

In this example, the subunit address bus line ADS is the upper two bits of lines A0 to A3 output from the central processing unit CPU.
The external data bus line DBM is composed of lines D0 to D7 output from the central processing unit CPU. Further, the lower two bit lines A2 and A3 of lines A0 to A3 are decoded by the decoder DEC1 as described above, and selectively drive the decode lines US0 to US3 provided on the output side of the decoder DEC1. .

According to the above configuration, the line US
When one of 0 to US3 is driven, the corresponding line US
Connectors CN-10 to CN-1 specified by
The decoder DEC2 connected to 3 is activated. When the decoder DEC2 is activated, at that moment the bus line for the subunit address
The subunit address signal sent to ADS is decoded by decoder DEC2,
As a result, one of the decode lines IS0 to IS3 is selectively driven. In this way, the line IS0~
When IS3 is driven alternatively, connectors CN-30 to CN-33 corresponding to the driven line IS
One of the subunits SU-0 to SU-3 connected to the subunit SU-0 to SU-3 is alternatively activated. As a result, if the activated subunit SU is an output subunit, for the eight external terminals T connected to the subunit SU,
Output data stored in the input/output image memory IM is transferred via bus lines DBM and DBS. On the other hand, if the activated subunit is an input subunit, the eight external terminals T connected to the subunit SU
The data is written to the corresponding input area in the input/output image memory IM via the bus lines DBS and DBM.

In this way, according to this PLC, when the number of input/output points exceeds 32, the main unit
This can be achieved by increasing the number of MUs, or if you want to change the ratio between the number of output points and the number of input points within each main unit MU, you can change the number or type of subunit SUs by changing the number or type of subunit SU (OUT). This can be handled freely by changing the input subunit SU(IN).

Also, in this PLC, connector CN-1
0~CN-13 and connector CN-30~CN-3
3, line US0 to US3 or line
Since the configuration is such that addresses are assigned via IS0 to IS3, addressing for each unit can be done without installing a unique code setting machine or code matching judgment circuit inside each subunit SU or each main unit MU. can perform actions. As a result, it is possible to prepare many subunits SU or main unit MU with the same configuration in advance, which has various advantages from the manufacturer's point of view, such as the possibility of cost reduction due to mass production effects. Yes.

However, when this PLC is viewed from the user's side, it has the following disadvantages. For example, as shown in Figure 1, address bus lines for subunits
Four connectors CN-10 to CN-13 and four connectors CN-20 to CN-23 are provided on the ADS and external data bus line DBM, respectively, which means four main units MU-0 to MU-3.
It is assumed that a large number of connections can be made. Assume that the non-controlled objects are divided into four devices, such as the first to fourth devices, and main units MU-0 to MU-3 are assigned to each device. In such a case, main unit MU-0~
Each MU-3 can be connected with 32 input/output points, but not all input/output points are necessarily required for each device. Therefore, as shown in Figure 1, the main unit
Assuming that the equipment corresponding to MU-0 does not require 16U input/output points, the subunit SU-
2. SU-3 will not be connected. Also,
If a device compatible with main unit MU-2 is not yet installed, connect connector CN-
12. Nothing is connected to the connector CN-22, which is what is called an empty state.

On the other hand, in this PLC, a memory of 8 bits per word, for example, is used as the input/output image memory IM, and as shown in FIG. 2, each potential external terminal T0 to T127 is connected to the input/output image memory IM. Addresses are allocated in advance so as to correspond sequentially one byte at a time starting from the first address. As a result, as mentioned above, the external terminals T16 to T3
6. If the connectors corresponding to external terminals T64 to T95 are empty, the input/output image memory IM
As shown in FIG. 2, the area corresponding to the series of external terminals T becomes empty.

Further, the address of the input/output image memory IM in this type of PLC directly corresponds to a numerical value attached to an input command normally used in a user program. Therefore, as mentioned above, the external terminal T
16 to T31 and external terminals T61 to T95 are empty, which means that the external input/output numbers used in the user program are discontinuous.

By the way, when programming in this type of PLC, it is preferable that the external input/output number and the internal input number (internal relay number) are consecutive numbers, and in this way, the external output or input number is If they are continuous, programming errors may occur when designing a user program.

This invention was made in order to solve the above problem, and its purpose is to be able to flexibly respond to a wide range of uses by users, and to allow users to connect external devices to external terminals. The object of the present invention is to provide a PLC in which the input/output numbers are arranged in consecutive numbers according to user instructions even when the PLCs are connected discontinuously.

That is, the present invention includes an input/output updating means for writing input data obtained from an input circuit into an input/output memory, reading out output data stored in the input/output memory, and supplying the output data to the output circuit; and program execution means for performing arithmetic processing on stored data according to an arbitrarily set user program and rewriting data in the input/output memory based on the processing results; the input circuit and the output circuit each have The unit consists of a main unit that handles only a fixed number of subunits, including both input subunits and output subunits that handle a fixed number of inputs or outputs; the main unit is provided with an internal data bus line and an address decoder for the subunits. The address decoder in the main unit is
The internal data bus lines in the main unit can be connected to the first group of connectors, each of which is individually assigned an address, on the address line for the subunits of the controller body without having to specify the position; can be arbitrarily connected to a second group of connectors provided on an external data bus line of the main unit; each subunit in the main unit is individually assigned an address on the internal data bus line by the output of the address decoder; The input/output updating means can be arbitrarily connected to the provided third connector group without receiving position designation; is configured to address a connector of said input subunit to write input data to said input/output memory, or read output data from said input/output memory to said respective output subunit. In the programmable logic controller: Each of the main units includes a subunit identification circuit that outputs subunit identification data indicating whether each subunit in the main unit is connected to an input subunit, an output subunit, or no subunit. A connection switching circuit is provided to be connected to the internal data bus line, and to switch the internal data bus line to either the subunit side or the subunit identification circuit side in response to a switching signal sent from the controller main body; and, on the controller main body side, an identification data memory for storing the subunit identification data taken in from each main unit via internal and external data bus lines in a predetermined format; While scanning each of the main units in address order, at the same time sending a switching signal to each main unit, switching the switching connection circuit to the subunit identification circuit side, and transmitting each subunit identification data to the controller main body side via the internal and external data bus. and subunit configuration scanning means for reading the identification data into the identification data memory; and when the input/output updating means sequentially accesses each storage area of the input/output memory in units of subunits, the identification data is scanned for each area. Each subunit identification data stored in memory is searched for each subunit in a fixed address order, and for the address of a subunit whose subunit identification data sequentially detected by the search indicates an "output subunit", the input/output Read the data in the accessed area of the memory and transfer it to the subunit at the detected address; Regarding the address of the subunit whose subunit identification data sequentially detected by the search indicates "input subunit" , the data from the address of the detected subunit is written into the accessed area of the input/output memory.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing the electrical configuration of the PLC according to the present invention. In addition, in this figure, the same reference numerals are given to the parts having the same configuration as those of the conventional example shown in FIG. 1, and the explanation thereof will be omitted.

As shown in the figure, the hardware features of the PLC of this invention are as follows.

First, each main unit MU is provided with a code setter CODE for setting data representing the configuration, ie, number and type, of subunits SU within the main unit MU, and this code setter CODE is connected to the internal data bus DBS via the interface circuit IFC, and the controller main unit CU
A switching circuit is provided for switching the decode line US outputted from the decoder DEC1 of the controller unit CU to the interface circuit IFC side or the decoder DEC2 side in response to a switching signal RES2 sent from the controller main unit CU; The switching signal sent from the controller main unit CU is supplied to each subunit SU as a deactivation signal.

On the controller main unit CU side, for sending the switching signal to the signal line RES2,
A switching signal sending circuit is provided. This switching signal sending circuit is composed of a power-on detection circuit PRES and an OR gate, and the operation of these circuits is shown in the timing chart of FIG.

On the other hand, the contents of each bit of the code setter CODE in the main unit MU mentioned above are determined as follows.

UNT: When on, there is a unit; when off, there is no unit.

INU: On indicates input subunit, off indicates output subunit.

MIX: When on, indicates a mixed unit of output subunit and input subunit. However, in this embodiment, the proportion units have the same number of output units and input units, and the output subunits are always connected first in each main unit MU.

N1: On indicates that there is one 8-point subunit SU in the main unit.

N2: On indicates that there are two 8-point subunits SU in the main unit MU.

N3: On indicates that there are 3 8-point subunits SU in the main unit MU.

N4: On indicates that there are 4 8-point subunits SU in the main unit MU.

On the other hand, a table memory as shown in FIG. 4 is provided in the working area of the central processing unit CPU constituting the controller main unit CU. As shown in the figure, this table memory has eight address areas from address 0 to address 7. Then, two consecutive addresses are assigned to the subunit SU in each main unit MU.
Data indicating the configuration of is stored. That is, 0-1, 2-3, 4-5, 6- in the table memory
At each address of 7, there are main units MU-0 to MU.
-3, data representing the configuration of each subunit SU is stored. Then, the address after each two consecutive addresses contains the main unit MU.
When there are subunits with multiple inputs and outputs within each main unit MU, the data regarding the output subunit SU (OUT) that exists within each main unit MU is stored, and the later address contains the data for each main unit MU.
Data regarding the input subunit SU(IN) present within the MU is stored.

Also, each address of the table memory is
IM address storage field, unit number storage field, I/O
It is divided into four columns consisting of a memory column and a SU presence/absence memory column. The first IM address storage column contains the output subunit SU (OUT) group or input subunit SU existing in each main unit MU.
(IN) In the group, the input/output image memory to which the data of the first subunit SU of each group is to be corresponded.
The address in IM will be remembered. In the unit number storage column, the number of all subunits SU constituting the input or output subunit SU group is stored for each input/output subunit. The I/O storage column stores data indicating whether the subunit SU group is an input subunit or an output subunit. The SU presence/absence memory column shows the connectors CN-30 to CN- corresponding to each subunit SU.
33 stores data indicating whether or not the subunit SU is connected.

Next, FIG. 7 is a flowchart for explaining the operation of the PLC according to the present invention. The contents of each step constituting this flowchart are enumerated in sequence as follows.

Step (1); Based on the input/output data stored in the input/output image memory IM, execute the user program stored in the program memory PM,
The execution result is stored again in the output data area of the input/output image memory IM.

Step (2): Set the contents of the address register for table memory to 0.

Step (3): Read the contents of the address specified by the table memory address register from the table memory.

Step (4): Determine whether "1" exists in the SU presence/absence column of the data read in step (3), and if the determination result is YES, proceed to step (5).
If NO, proceed to step (17).

Step (5): Set the contents of the first IM address column of the data read in step (3) in the address register for input/output image memory IM.

Step (6): Set the contents of the unit number storage column of the data read in step (3) in a predetermined unit number storage register.

Step (7); Based on the contents of the address register for table memory at that time,
Determine the US number and store it in a designated register.

Step (8): Determine whether the contents of the table memory address register are even numbers. If the determination result is YES, proceed to step (9); if NO, proceed to step (10). Proceed to.

Step (9): Set the contents of the IS number register to 0.

Step (10): Determine whether "1" is present in the I/O storage column of the data read in step (3), and if the determination result is YES, proceed to step (11). If NO, proceed to step (12).

Step (11): Address the input/output image memory IM based on the contents of the address register for the input/output image memory IM at that time, and store the current US number and IS number in the designated storage area. Retrieves input data from the input subunit SU specified by .

Step (12); Input/output image memory at that time
The input/output image memory IM is addressed based on the contents of the address register for IM, and the stored contents of the address are transferred to the output subunit SU specified by the US number and IS number at that time.

Step (13): Update one content of the address register for input/output image memory IM.

Step (14): Update one content of the address register for IS number.

Step (15): Subtract 1 from the contents of the unit number storage register.

Step (16): Determine whether the contents of the unit number storage register have become 0 or not. If the determination result is YES, proceed to step (17); if NO, return to step (10). .

Step (17): Update one content of the address register for table memory.

Step (18): Determine whether the table memory has been read to the final address. If the determination result is YES, return to step (1); if NO, return to step (3).

Next, the operation of the PLC having the above configuration will be systematically explained based on the flowcharts of FIGS. 5 and 7.

When commercial power AC is applied to the controller main unit CU and the power-on detection circuit PRES, the power-on detection circuit PRES outputs a desired reset signal on the signal line RESO for a predetermined period of time as shown in FIG. This signal is input to the reset input of the central processing unit CPU and to the OR gate OR. When the signal on signal line RESO is released, the central processing unit
The CPU starts initial processing and immediately inputs a signal to the OR gate OR via the signal line RES1. Therefore, the signal on the output signal line RES2 of the OR gate OR remains active. When the signal on the signal line RES2 becomes active, the AND gate AND1 becomes an active condition;
The AND gate AND2 becomes inactive due to the output signal of the inverting gate NOT1. Also, signal line
The subunit SU in each main unit MU is initially reset by the signal on RES2.

During the initial processing, the central processing unit CPU
Decoder address signals via lines A2A3
Output to DEC1 and select in the order of main unit MU-0 to main unit MU-3.

First, when a signal is output on line USO and main unit MU-0 is selected, the output of the AND gate AND1 of the first unit placed in main unit MU-0 becomes active, and the interface circuit IFC is activated. Make it. When the interface circuit IFC becomes active, the code setter CODE
The setting contents are taken into the central processing unit CPU along lines D0 to D7.

The first unit located in main unit MU-0
In the unit example, UNT (on), MIX (on), and N2 (on) are set, and all other bits are turned off. That is, it represents a six-point mixing unit in which input and output subunits SU are mixed.

Next, the controller main unit CU is
Select US1, and similarly select main unit MU-1.
The code setting device of the second unit located in
Load the contents of CODE into the central processing unit CPU.

In the same way, the code setting devices are sequentially installed up to the third unit located in main unit MU-3.
The contents of CODE are taken into the central processing unit CPU.

Then, when the outputs of the code setters CODE of all units are taken in by the central processing unit CPU, the signal on the signal line RES1 is made active after a time T, and the execution of the user program is started. In addition, each code setting device taken into the central processing unit CPU in the above process
The data from CODE is subjected to predetermined editing in a working area within the central processing unit CPU, and is finally stored in a table memory in the form of a table as shown in FIG.

First, when the power is turned on, initial processing is executed as shown in the basic flowchart of FIG. 5, prior to program execution. Through this initial processing, the subunits SU within each main unit MU are sequentially scanned as shown in FIG.
At the scanned timing, the line
Each connector CN-3 through UNT and line INU
Data indicating whether a subunit SU is connected to 0 to CN-33 and whether the connected subunit SU is an input subunit or an output subunit is sequentially sent to the central processing unit.
captured by the CPU. Next, each piece of data taken in is edited in a working area within the central processing unit CPU, and finally stored in each address area within the table memory, as shown in FIG.

Next, when step (1) shown in FIG. 7 is executed, the user programs stored in the program memory PM are sequentially executed based on the input/output data of the input/output image memory IM at that time. The result is stored again in the output area of the input/output image memory IM.

Next, when steps (2) and (3) are executed sequentially, 0 of the table memory is stored in the central processing unit CPU.
The contents of the address are imported. Since "1" is stored in the SU presence/absence column of this imported data, the execution result of step (4) is YES, and then step (5) is executed and the data is imported from table memory. Address 0 of the input/output image memory IM is specified based on the contents of the first IM address field of the data.

Next, when step (6) is executed, the predetermined unit number storage register in the central processing unit CPU is set to the numerical value 1 stored in the unit number storage column at address 0 of the table memory.

Next, when step (7) is executed, US number 0 is specified corresponding to address 0 of the table memory. Also, at this time, since address 0 of the table memory is an even number, the execution result of step (8) is
YES, step (9) is executed,
The IS number is set to 0. As described above, address 0 of the input/output image memory IM is addressed, address 0 is addressed in the table memory, and furthermore, address 0 of the input/output image memory IM is addressed, and
SU-0 is addressed.

Then, when step (10) is executed, step
I/I at address 0 of the table memory read in (3)
It is determined whether the contents of the O storage column are "1". In this case, the determination result in step (10) is NO, so step (12) is executed. When step (12) is executed, the data D0 to D7 stored at address 0 of the input/output image memory IM are transferred to the external data bus line DBM and the internal data bus line
It is sent to subunit SU-0 via DBS and output from external terminals T0 to T7.

Next, when step (13) and step (14) are executed, the contents of the address register for the input/output image memory IM are set to 1, and the contents of the address register for the input/output image memory IM are set to 1.
The address register for the number is also set to one.

Next, when step (15) is executed, 1 is subtracted from the contents of the above-mentioned unit number storage register. In this case, the result of the subtraction is 0, so the execution result of step (16) is YES, and then step (17) is executed and the address register for table memory is set to 1. continue,
Step (17) is executed, but in this case, the table memory address has not yet been completed, so the execution result is NO, and step (3) is executed again.
is executed, and the contents of address 1 of the table memory are taken into the central processing unit CPU. Since “1” is stored in the SU presence/absence storage column at address 1 of the table memory, the execution result of step (4) is
YES. Then, step (5) is executed, and the value 1 stored in the first IM address storage column at address 1 of the table memory is set in the address register for the input/output image memory IM.

Next, when step (6) is executed, the number 1 stored in the unit number storage column at address 1 of the table memory is set in the unit number storage register.

Next, when step (7) is executed, the US number 0 is specified corresponding to address 1, which is the address of the table memory at that time.

Next, when step (8) is executed, the address of the table memory is 1 and an odd number, so the execution result of step (8) is NO, and step (10) is executed.

Next, when step (10) is executed, it is determined whether "1" exists in the I/O storage column at address 1 of the table memory. In this case, since “1” exists, the judgment result is YES, and the step
(11) is executed. When step (11) is executed, the input subunit SU-1 in the main unit MU-0 is addressed based on the current US number 0 and the current IS number 1. The input data fetched from the input subunit SU-1 is stored at address 1 of the input/output image memory IM as shown in FIG.

Then step (13) and step (14)
When this is executed, the value 2 is set in both the address register for the input/output image memory IM and the address register for the IS number. Next, when step (15) is executed, 1 is subtracted from the contents of the unit number storage register, and the result of this subtraction becomes 0, so step (17) is executed following execution of step (16). , the value 2 is set in the table memory address register.
In this case, since the address of the table memory has not yet been completed, the execution result of step (18) is NO again, and the process returns to step (3). Then, when step (3) is executed, the contents of address 2 of the table memory are taken into the central processing unit CPU. Since "1" is stored in the SU presence/absence storage column at address 2 of the table memory, the execution result of step (4) is YES, and then step (5) and step (6) are executed. Input/output image memory IM
The contents of the address register for
Also, the contents of the register for storing the number of units are set to 4.

Next, when step (7) is executed, US number 1 is specified corresponding to address 2, which is the address of the table memory at that time.

Next, when step (8) is executed, since the address of the table memory at that time is an even number, step (9) is executed and the IS number is specified as 0.

Next, when step (10) is executed, it is determined whether the contents of the I/O storage column at address 2 of the table memory is "1", and since the determination result is NO, step (12) is executed. ) is executed. Step(12)
When executed, the input/output image memory IM 2
The output data stored at the address is
It is transferred to subunit SU-0 in main unit MU-1 designated by US number 1 and IS number 0, and output to external terminals T32 to T39.

Next, when steps (13) and (14) are executed in sequence, the number 3 is set in the address register for the input/output image memory IM, and at the same time, the number 1 is set in the register for the IS number.

Next, when step (15) is executed, the numerical value 4 stored in the above-mentioned unit number storage register is
1 is subtracted from , and the contents of the unit number storage register become 3. As a result, the execution result of step (16) becomes NO and the process returns to step (10).

In this way, steps (10) to (16) are repeated three times, and as a result, as shown in FIG.
The output data stored in addresses 2 to 5 of the IM will be sequentially output.

Next, while the contents of the table memory address register increase from 3 to 5, the execution result of step (4) becomes NO, and as a result, the incrementation of the address of the input/output image memory IM is stopped. will be maintained.

Next, when the contents of the address register for the table memory become 6 by executing step (17), the execution result of step (4) becomes YES again, and the contents of the address register for the input/output image memory IM become 6. It is now address 6, an increase of one from the previous address 5. At the same time, the numerical value 4 stored in the unit number storage column at address 6 of the table memory is set in the unit number storage register.

Next, when step (7) is executed, the US number is specified as 3 based on address 6, which is the address of the table memory at that time. Thereafter, in the same way as described above, the execution result of step (8) becomes YES, and then step (9) is executed and the IS number is specified as 0. Next, when step (10) is executed, step (12) is executed based on the contents of the I/O storage column at address 6 of the table memory, and as shown in FIG. The stored data at the address is transferred to subunit SU-0 within main unit MU.

Next, when steps (13), (14), and (15) are executed sequentially, the contents of the address register for input/output image memory IM and the contents of the IS number register are each incremented by one, and memory
Address 7 in IM and subunit SU-1 in main unit MU-3 are respectively addressed, and the contents of the unit number storage register are subtracted by 1 to 3. As a result, steps (10) to (16) are repeated three times until the contents of the unit number storage register become 0 in the same way as described above. As a result, the input/output image memory IM
, the address is incremented one by one from address 6 to address 9, and at the same time the main unit MU-
In 3, subunits SU-0 to SU-3 are specified one by one, and the input/output image memory
Output data is transferred from IM to subunit SU.

Thus, according to the PLC according to this embodiment, even if the main unit MU-2 is not connected to the connector CN-n2, as shown in FIG. , CN-33, even if the subunits SU-2 to SU-3 are not connected, each subunit is connected in order from the first address in the input/output image memory IM, as shown in Figure 8.
Data input/output related to SU is performed sequentially.

Therefore, when specifying each subunit SU in a user program, it is possible to specify them sequentially according to the serial number of the IM address, which frees up external terminal connections unlike in conventional PLCs of this type. This makes it possible to reliably solve the problem of discontinuous input/output designation numbers in the user program.

In addition, in the PLC according to this embodiment, the subunit SU in each main unit MU
Although the configuration of the subunit SU in each main unit MU is encoded and stored in two consecutive addresses in the table memory, the format for storing the configuration of the subunit SU in each main unit MU is not limited to this. Of course, each subunit SU may be assigned to each address of the table memory, and the presence or absence of a subunit SU and input/output status may be encoded and stored in each address.

As is clear from the description of the embodiments above, the PLC according to the present invention writes input data obtained from the input circuit to the input/output memory, and reads output data stored in the input/output memory to the output circuit. input/output updating means for supplying input/output updating means; and program execution means for performing arithmetic processing on the data stored in the input/output memory according to an arbitrarily set user program, and rewriting the data in the input/output memory based on the processing results. The input circuit and the output circuit are configured into a main unit that handles input subunits or output subunits that handle a fixed number of inputs or outputs, respectively, and a fixed number of subunits including both; , an internal data bus line and an address decoder for the subunit; the address decoder in the main unit is:
The internal data bus lines in the main unit can be connected to the first group of connectors, each of which is individually assigned an address, on the address line for the subunits of the controller body without having to specify the position; can be arbitrarily connected to a second group of connectors provided on an external data bus line of the main unit; each subunit in the main unit is individually assigned an address on the internal data bus line by the output of the address decoder; The input/output updating means can be arbitrarily connected to the provided third connector group without receiving position designation; is configured to address a connector of said input subunit to either write input data to said input/output memory or read output data from said input/output memory to said respective output subunit. In the programmable logic controller: Each of the main units includes a subunit identification circuit that outputs subunit identification data indicating whether each subunit in the main unit is connected to an input subunit, an output subunit, or no subunit. A connection switching circuit is provided to be connected to the internal data bus line, and to switch the internal data bus line to either the subunit side or the subunit identification circuit side in response to a switching signal sent from the controller main body; and, on the controller main body side, an identification data memory for storing the subunit identification data taken in from each main unit via internal and external data bus lines in a predetermined format; While scanning each of the main units in address order, at the same time sending a switching signal to each main unit, switching the switching connection circuit to the subunit identification circuit side, and transmitting each subunit identification data to the controller main body side via the internal and external data bus. and subunit configuration scanning means for reading the identification data into the identification data memory; and when the input/output updating means sequentially accesses each storage area of the input/output memory in units of subunits, the identification data is scanned for each area. Each main unit identification data stored in memory is searched for each subunit in a fixed address order, and for the addresses of subunits whose subunit identification data sequentially detected by the search indicates "output subunit", the above entry is performed. Read the data of the accessed area of the output memory and transfer it to the subunit of the detected address; Regarding the address of the subunit whose subunit identification data sequentially detected by the search indicates "input subunit" is designed to write data from the address of the detected subunit to the area of the input/output memory that is being accessed, so this type of unit consists of a main unit MU and a subunit SU.
Even if either the main unit MU or subunit SU does not exist in the corresponding connector in the PLC, each external terminal T can always be handled by sequential number in the user program, giving the user extensive control. While allowing manufacturers to respond flexibly to specifications, it is possible to reliably maintain ease of programming on the user's side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the PLC according to the present invention, FIG. 2 is a memory map showing the contents of the input/output image memory IM in a conventional PLC of this type, and FIG. 3 is a block diagram showing the configuration of the PLC according to the present invention. FIG. 4 is a block diagram showing the electrical configuration; FIG. 4 is a memory map showing the contents of the table memory used in the present invention; FIG. 5 is a flowchart showing the initial processing performed after power is turned on; FIG. 7 is a timing chart for explaining the initial processing, FIG. 7 is a flowchart for explaining the operation of the PLC according to the present invention, and FIG. 8 is the contents of the input/output image memory IM of the PLC according to the present invention. This is a memory map showing the CU: controller main unit, PM: program memory, IM: input/output image memory, CPU: central processing unit, DEC1: decoder, DEC2: decoder, MU: main unit, SU: subunit, T ...external terminal,
ADS...Bus line for subunit address,
DBM...external data bus line, DBS...internal data bus line, CN-10 to CN-13...first connector group, CN-20 to CN-23...second
Connector group, CN-30 to CN-33...Third connector group, PRES...Power on detection circuit, OR
...OR gate, AND1...AND gate,
AND2...and gate, SL...switching circuit,
IFC...Interface circuit, CODE...Code setting device.

Claims (1)

[Scope of Claims] 1. Input/output updating means for writing input data obtained from an input circuit into an input/output memory, reading out output data stored in the input/output memory, and supplying the output data to the output circuit; and program execution means for performing arithmetic processing on the data stored in the memory according to an arbitrarily set user program, and rewriting the data in the input/output memory based on the processing results; the input circuit and the output circuit are , each of which handles a fixed number of inputs or outputs, is configured into a main unit that handles a fixed number of subunits, including both input subunits and output subunits that handle a fixed number of inputs or outputs; The main unit includes an internal data bus line and an address decoder for the subunits. an address decoder in the main unit;
The internal data bus lines in the main unit can be connected to the first group of connectors, each of which is individually assigned an address, on the address line for the subunits of the controller body without having to specify the position; can be arbitrarily connected to a second group of connectors provided on an external data bus line of the main unit; each subunit in the main unit is individually assigned an address on the internal data bus line by the output of the address decoder; The input/output updating means can be arbitrarily connected to the provided third connector group without receiving position designation; is configured to address a connector of said input subunit to either write input data to said input/output memory or read output data from said input/output memory to said respective output subunit. In the programmable logic controller: Each of the main units includes a subunit identification circuit that outputs subunit identification data indicating whether each subunit in the main unit is connected to an input subunit, an output subunit, or no subunit. A connection switching circuit is provided to be connected to the internal data bus line, and to switch the internal data bus line to either the subunit side or the subunit identification circuit side in response to a switching signal sent from the controller main body; and, on the controller main body side, an identification data memory for storing the subunit identification data taken in from each main unit via internal and external data bus lines in a predetermined format; While scanning each of the main units in address order, at the same time sending a switching signal to each main unit, switching the switching connection circuit to the subunit identification circuit side, and transmitting each subunit identification data to the controller main body side via the internal and external data bus. and subunit configuration scanning means for reading the identification data into the identification data memory; and when the input/output updating means sequentially accesses each storage area of the input/output memory in units of subunits, the identification data is scanned for each area. Each subunit identification data stored in memory is searched for each subunit in a fixed address order, and for the address of a subunit whose subunit identification data sequentially detected by the search indicates an "output subunit", the input/output Read the data in the accessed area of the memory and transfer it to the subunit at the detected address; Regarding the address of the subunit whose subunit identification data sequentially detected by the search indicates "input subunit" , a programmable logic controller configured to write data from the detected subunit address to the accessed area of the input/output memory.