JP2530810B2 - Storage element and method of using the same - Google Patents

Description

The present invention relates to a memory element such as a mask ROM used in a one-chip microcomputer and the like and a method of using the same.

[Outline of Invention]

The present invention relates to a memory element and a method of using the same, and has a built-in large-capacity mask ROM and small-capacity programmable ROM, and outputs programmable ROM data instead of mask ROM output data at a specific address. Yotsutte
This is to enable compensation of mask ROM data.

[Conventional technology]

For example, a one-chip micro computer is constructed as shown in FIG. In the figure, (31) is a CPU that processes data, (32) is a ROM in which a program for the operation of this CPU (31) is written, and (33) is an I / O that inputs and outputs data. Then, the address from the CPU (31) is supplied to the ROM (32), and I / O (3
The data from 3) is processed and this processed data is I
It is output to / O (33).

In such a device, the ROM (32) is further configured as shown in FIG. That is, (41) is, for example, a 16-bit address input terminal, and this terminal (4
1) is connected to the address input of the built-in ROM (42). The 8-bit data output of the ROM (42) is output through the gate circuit (43) to the data output terminal (44).
Connected to. Further, the output control terminal (45) is connected to the output control section of the gate circuit (43).

Therefore, in this ROM (32), address input terminals (4
According to the address (A _{0 to} A ₁₅ ) supplied to 1), ROM (4
The data (D _{0 to} D ₇ ) in 2) is read, this data is supplied to the gate circuit (43), and is output to the data output terminal (44) according to the control signal OE from the output control terminal (45). It

By the way, there is a case where such a one-chip micro computer is further incorporated into a device and used. In that case, a program, data, etc. are created in accordance with the operation of the device etc., and the program etc. is written in the ROM (32).

In that case, in order to mass-produce the ROM in which the program or the like is written, it is advantageous to use a so-called mask ROM in terms of manufacturing cost. Ie mask ROM
A part of the mask in the ROM manufacturing process is modified according to a program or the like, and the program or the like is written by performing the process using this mask. Therefore, once the mask is created, thereafter, a ROM in which a program or the like is written can be manufactured in a large amount at low cost only by the normal ROM manufacturing process.

However, such mask ROMs generally require a period before mass production, and it takes several weeks from ordering to delivery.
It took a few months. For this reason, the creation of the program precedes the design of the device, and it is necessary to change the program after placing an order, and the ROM has a large capacity (eg 16 to 64K
If the amount of programs etc. to be written is increased, the phenomenon that program errors, so-called bugs, etc. are not discovered before ordering has started to occur.

Therefore, problems such as delays in delivery due to reordering, eventually delays in manufacturing and sales of equipment, and extra hardware and manufacturing processes are needed to compensate for bugs by installing hardware around them. As a result, there have been problems such as an increase in the manufacturing cost of equipment.

On the other hand, using a so-called programmable ROM, it is conceivable to write the program etc. after the program etc. has been thoroughly examined in the final stage of device manufacturing, but such a programmable ROM is generally compared to a mask ROM. It is several times more expensive and extremely disadvantageous in terms of manufacturing cost.

[Problems to be solved by the invention]

The conventional mask ROM has a problem that it is extremely difficult to compensate for an error such as a program, and the programmable ROM is expensive and extremely disadvantageous in terms of manufacturing cost.

[Means for solving problems]

The present invention provides an I / O (33) for inputting / outputting data, a CPU (31) for processing data and outputting an address, and the above CPU.
A memory element (ROM) (32) from which a program read by supplying an address from (31) to an input terminal is output from a data output terminal, and from the output terminal to the CPU (31) I above according to the program supplied
A one-chip microcomputer in which the data input from the / O (33) is processed and the processed data is output from the I / O (33), and the address input terminal (1 ) Is connected to the address input of the mask ROM (2) and is connected to the programmable logic array (7), and the output of the programmable logic array (7) is connected to the address input of the programmable ROM (9). The data output of the ROM (2) is connected to the data output terminal (4) via the first gate circuit (3), and the programmable ROM is also provided.
The data output of (9) is connected to the data output terminal (4) through a second gate circuit (10) whose conduction direction can be switched by a control signal, and is connected to the programmable logic array (7) or the writing circuit. By controlling the conduction of the first and second gate circuits (3) and (10) by the output, the signal supplied from the write circuit is written to the programmable ROM (9) when data is written. Therefore, the conduction direction of the second gate circuit (10) is reversed, and
From the data output terminal (4) to the programmable ROM
1 to supply write data to (9)
It is a chip microcomputer.

[Action]

According to this, the error of the data written in the mask ROM can be compensated by the programmable ROM, so that the compensation of the program or the like can be easily performed.

[Embodiment] In FIG. 1, a mask ROM (2) whose address (A _{0 to} A ₁₅ ) from the address input terminal (1) is, for example, 32 Kbytes.
8 bits of data (D _{0 to} D ₇ ) from the data output of the ROM (2) is supplied to the data output terminal (4) through the gate circuit (3).
The control signal OE from the output control terminal (5) is supplied to the output control section of the gate circuit (3) through the AND circuit (6).

Further, addresses (A _{0 to} A ₁₅ ) from the input terminal (1) are supplied to the programmable logic array (PLA), and signals (O _{0 to} O) from, for example, 32 output terminals of this PLA (7) are supplied.
₃₁ ) is supplied to the encoder (8). The 5-bit encoded signal is supplied to the address input of, for example, a 32-byte programmable ROM (9). Further, for example, 8-bit data from the ROM (9) is supplied to the data output terminal (4) through the gate circuit (10).

Also, 32 output signals from the PLA (7) are OR circuits (11).
Is supplied to the gate circuit (10) via the AND circuit (12) with the OR output and the control signal OE from the control terminal (5).
Is supplied to the output control unit of the. Further, the output of the OR circuit (11) is supplied to the AND circuit (6) through the inverter (13).

Therefore, according to this device, the wrong address such as the program of the mask ROM (2) is set in the PLA (7), and when this address is supplied to the address input terminal (1), the PLA
A signal is output from an arbitrary output terminal of (7). Then, this signal is made into a predetermined 5-bit address by the encoder (8), and this address is programmable ROM (7).
The data which is supplied to and compensates for the erroneous program is output. Further, the output of the signal to the output terminal of the PLA (7) is detected by the OR circuit (11), and this OR output is supplied to the AND circuit (12) and the gate circuit (10) is output from the output control terminal (5). To the AND circuit (6) through the inverter (13) and the control signal OE to the gate circuit (3) is cut off.

As a result, when a wrong address such as a program in the mask ROM (2) is found, data for compensating for it is output from the programmable ROM (9) and output to the data output terminal (4) through the gate circuit (10). It At this time, the data from the mask ROM (2) is cut off by the gate circuit (3).

Further, the setting of the address of the PLA (7) and the writing of the data to the programmable ROM (9) for this device are performed as follows.

That is, the device is provided with a write control terminal (14), and this terminal (14) is connected to a write circuit (15) built in the device. The write circuit (15) is provided with 32 output terminals that are sequentially shifted each time the control signal WE is supplied, and these output terminals are connected to the 32 output terminals of the PLA (7), respectively. .

Further, the conduction direction of the gate circuit (10) can be switched by the control signal, and the writing circuit (15) is connected to the direction control section of the gate circuit (10). Furthermore, the writing circuit (15) is PLA
(7) and the write control section of the programmable ROM (9).

When writing, mask the address input terminal (1)
The address of the incorrect data is supplied to the ROM (2), and the compensating data is supplied to the data output terminal (4). Further, the control signal WE is supplied to the write control terminal (14). As a result, the write circuit (15) first sets any one of the 32 output terminals to a high potential, and this high potential is set to PL.
It is supplied to the corresponding output terminal of A (7) and is also supplied to the encoder (8), and the encoded address is supplied to the programmable ROM (9). Also, write circuit (1
The signal from 5) inverts the conduction direction of the gate circuit (10), and the compensation data supplied to the data output terminal (4) is supplied to the data output of the programmable ROM (9).

Therefore, the address to be compensated is supplied to the address input of the PLA (7), the signal to be formed at that time is supplied to the output terminal, and the encoded address is supplied to the address input of the programmable ROM (9). Compensation data is provided at the data output. And in this state PLA
(7) and the programmable ROM (9) are supplied with signals to the write control unit, so that the signals to be formed and the compensation data are PLA (7) and programmable ROM.
Written in (9).

As a result, the address of the erroneous data in the mask ROM (2) is set in the PLA (7), and the compensation data is written in the programmable ROM (9).

 The PLA (7) is specifically as shown in FIG. 2, for example.
It is composed of Address input terminal A in the figure₀, A₁......
Is the inverter I₀, I₁...... connected to these input terminals
And the output terminal O orthogonal to the line from the inverter₀, O₁
A line connected to ... is provided. B₀, B₁...... ha
It is a tour circuit. In addition, a diode at each intersection of the line
D₀₀, D_Ten…… D ▲ ▼ 、 D ▲ ▼ …… is provided
You.

 In this device, burn out any diode
The address is set by. That is, for example, the output end
Child O₀Against diode D₀₀And D ▲ ▼ and D ▲
Burn out ▼, D ▲ ▼ and D_TenAnd D₂₀If you make use of
(A₀, A₁, A₂) = (0,1,1) Output terminal O₀Out
You will gain power. And this input terminal and output terminal
The desired signal is applied to the child, and the control signal is sent to the write control section described above.
The corresponding diode is burnt out when supplied
Is.

In addition, this PLA has various configurations such as a programmable ROM application.

Further, in the above device, if the programmable ROM (9) can directly accept 32 addresses, the encoder (8) becomes unnecessary.

Furthermore, the capacity of programmable ROM is 1/1000 of mask ROM.
A degree is enough.

Therefore, since the capacity of the programmable ROM is extremely small, even if such a programmable ROM is provided, the cost of the element does not increase so much, and it is extremely cheap compared to the case where the entire programmable ROM is used.

〔The invention's effect〕

According to the present invention, the error in the data written in the mask ROM can be compensated by the programmable ROM, so that the compensation of the program or the like can be easily performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of the present invention, FIG. 2 is a diagram for explaining the same, and FIGS. 3 and 4 are diagrams for explaining a conventional technique. (1) is an address input terminal, (2) is a mask ROM,
(3) (10) is a gate circuit, (4) is a data output terminal,
(5) is an output control terminal, (6) and (12) are AND circuits,
(7) is a programmable logic array, (8) is an encoder, (9) is a programmable ROM, (11) is an OR circuit, (13) is an inverter, (14) is a write control terminal, and (1)
5) is a writing circuit.

Claims (1)

(57) [Claims] 1. An I / O for inputting / outputting data, a CPU for processing data and outputting an address, and a program read by supplying an address from the CPU to an input terminal from a data output terminal. One chip that has a storage element that is output, and that processes the data input from the I / O according to the program supplied to the CPU from the output terminal and outputs the processed data from the I / O A microcomputer, wherein the address input terminal of the storage element is connected to an address input of a mask ROM and is also connected to a programmable logic array, and the output of the programmable logic array is connected to an address input of a programmable ROM. The data output of the mask ROM is connected to the data output terminal via the first gate circuit, and The data output of the bull ROM is connected to the data output terminal via a second gate circuit whose conduction direction can be switched by a control signal, and the first and second gates are output by the output of the programmable logic array or write circuit. The conduction direction of the circuit is controlled so that the conduction direction of the second gate circuit is inverted according to the signal supplied from the writing circuit when writing data to the programmable ROM, and the data output terminal is also provided. A one-chip microcomputer, which supplies write data to the programmable ROM from the above.