JPS62293585A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To relieve the processing load of a main device by controlling the operation of a memory array according to a specific bit of designated address data read prior to function execution requested externally. CONSTITUTION:A memory array M-ARYF is provided in correspondence to a function control bit DF and memory arrays M-ARY0-M-ARY7 are provided in correspondence to input/output data D0-D7. A function control bit df supplied from an external device is fed as another input to a function control bit comparison circuit FC. The circuit FC compares a function control bit of the array M-ARYF stored in a FF read prior to the normal write or read with the bit df, outputs an output signal fm to a timing control circuit TEF when both the function control bits are coincident and gives an output to an external main device via an external terminal FM. Thus, the function of the semiconductor storage device is autonomously controlled to relieve the load on the main device.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor memory device, for example, a static RA that is accessed in units of multiple bits.
This article relates to techniques that are effective when used for M, etc.

(Prior Art) Regarding various semiconductor memory devices such as static RAM that are accessed in units of multiple bits such as bytes, ζ is as follows.
For example, in September 1983, ■rHitachi 1 published by Hitachi, Ltd.
0 Memory Data Book J226 Negative to pages 232.

(Problems to be solved by the invention) In recent years, semiconductor memory devices have become increasingly high in JM.
Even though its storage capacity has increased, it still only has a passive function as a semiconductor storage device rod. In other words, even the function control of the storage device itself, such as distortion protection and read restrictions corresponding to the storage area, is performed under the management and control of the main device, so it is necessary to have a memory map on the main device side. or require complex software processing by the main device.

An object of the present invention is to provide a semiconductor memory device having new functions.

The above and other objects and novel features of this invention are:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief explanation of four representative inventions among the inventions disclosed in this application is as follows. In other words,
A specific bit for function control is provided corresponding to each address or each memory area of the semiconductor storage device, and the specific bit for function control corresponding to the specified address is inserted before executing the function requested from the outside. It performs control such as executing or prohibiting required functions according to the content.

[For production]

According to the above-mentioned means, the functions of the semiconductor memory device can be autonomously controlled by the function control bits, and the processing load on the main device can be reduced.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applied.
A block diagram of one embodiment of M is shown. The circuit elements constituting each circuit block in the figure are formed on a solid semiconductor substrate such as single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In the static type RAM of this embodiment, one hint for a function control focus is provided for each address, and in combination with 8-bit data, one word consists of 9 bits. This function control bit is not particularly limited, but
It is used to perform write protection in the static RAM's overheating operation mode, and to perform read restriction in the read operation mode. In other words, information that is essentially a keyword is stored in the function control pin, and when accessing the memory, function control bits are supplied from the external main device, and prior to execution of the requested function, information is stored at the specified address. The stored function control beat/beat is read out.

The function control bit given from the external device and the function control focus extracted from the specified address are compared by the function control bit comparison circuit FC, and both h&
A data write or read operation is executed only when the performance control bits match.

The result of the comparison operation by the function control focus comparison circuit FC is output to the main device of the external 01S as a function control bit match signal FM.

In FIG. 1, memory array ! corresponds to function control bit DF! vi -A l ("1'F" is provided,
Memory array M − corresponds to input/output data DO to v7.
ARYO to M-ARY 7 are provided. These memory arrays are composed of a plurality of word lines arranged horizontally in FIG. 1, a plurality of complementary data lines arranged vertically in FIG. - They are arranged in an r-shape and are each composed of a plurality of memory cells.

Word lines forming each memory array are selected and designated by an X address decoder XDCR.

This X address decoder XDCR is supplied with a plurality of complementary internal address signals 1x~ formed by an address buffer A1)B that receives external address signals AO-Ai, and is supplied with a timing signal φC from a timing 1↑] control circuit 'rC. Pi is supplied. X address decoder XDC
R is a word that is activated by the high level of the timing signal φCQ, and is used to decode complementary internal address signals ax~ supplied from the address buffer ADB and select one word line specified by these address signals. A line selection signal is formed and the memory array M-
Supply to ARY F and ~1-ARYO~M-ARY7.

On the other hand, complementary data lines constituting each memory array are connected to a column switch C3W provided corresponding to each memory array.
F□ and cswo to C3W7 are connected to unillustrated switches 1-7 and i0S FET, respectively. A data line selection signal is supplied to these switches MO3FET from a Y address decoder YDCR. The Y address decoder YDCH is supplied with a plurality of complementary internal address signals y~ from the address buffer ADB, and is also supplied with a timing signal φce from the timing control circuit rC. Y address decoder YDCR
is activated by the high level of the timing signal φce, and is a complementary internal address signal ! supplied from the address buffer ADB. y~ to form a data III selection signal for selecting a set of complementary data lines specified by these address signals, and supply it to column switches C3WF and C3WO to C3W7.

Column switches C3WF and cswo to C5W7 respectively select - sets of data lines according to data line selection signals supplied from the Y address decoder YDCR,
Connected to corresponding complementary common data lines CDF and CDO to CD7.

The address buffer ADB receives address signals AO-Ai supplied from the main device via the address bus, and generates complementary internal address signals 1x to 1x consisting of an internal address signal in phase with these address signals and an internal address signal in opposite phase.
and By~ are formed and supplied to the X address decoder XDCR and the Y address decoder YDCk, respectively.

Through the selection operations by the above X address decoder XDCR, Y address decoder Yl) CI (and each column switch), nine memory cells arranged at common addresses designated as addresses 18 AO to Ai from each memory array are selected and connected to the corresponding complementary common data line.

The complementary common data lines CDF and CDO to CD7 are coupled to the input terminals of corresponding bits of the data output buffer 7FA DOB, and to the corresponding output terminals of the data input buffer 1υIB. The data output buffer DOB is supplied with a timing signal φr from a timing control circuit '1'C, which will be described later.
are supplied respectively.

In the read operation mode of the static RAM, the data output buffer DOB operates as a timing control circuit 'r.
The memory arrays M-ARYF and M-ARYO-M-AR are activated by the high level of the timing signal φr supplied from C and are transmitted to each complementary common data line.
The read signal from the selected memory cell Y7 is amplified and output to the data bus as output data DF and DO~D7. Further, the read signal from the selected memory cell of the memory array M-ARYP, that is, the function control bit, is transmitted to the launch flip-flop FF,
Retained for the duration of memory access. The output signal of the buffer FF is supplied as one input signal of the function control bit comparison circuit FC.

On the other hand, the data input cover 7 is a static type R.
In the write operation mode of AM, it is activated by the high level of the timing signal φW supplied from the timing control circuit TC, and input data DO to D7 supplied from the external main device via the data bus are used as complementary write signals. , corresponding complementary common data lines CD0-CD7
Write to the selected memory cell of memory array M-ARYO to M-ARY7 via In the function control hint write operation mode, the timing signal φ is transmitted from the timing control 911 circuit TC.
According to the revision, the function control hint supplied via the input/output terminal DF is written into the selected memory cell of the memory array M-ARYF.

The function control bit DF supplied from an external device is supplied as the other input signal of the function control pin 1 comparison circuit FC. The function control bit comparison circuit 1lIFc is used to compare the function bits of the memory array M, -ARYF, which are read out and held in the memory array M, -ARYF, before a normal write operation or read operation. Compare with the performance control bit 1-DF supplied from the outside. As a result, when both function control bits match, the output signal fm of the function control bit comparison circuit FC becomes high level, and when they do not match, it becomes low level. The output signal rm of this function control bit comparison circuit FC
is input to the timing control circuit TC, and is also output to the external main device via the external terminal FM.

The timing control circuit 'rC uses the chip selection signal C3, write enable signal WE and function control enable signal T1 supplied from an external main device as control signals, and the output signal fm of the function control bit comparison circuit FC.
The various timing signals mentioned above are formed and supplied to each circuit. Among these timing signals, the timing signal φc
e is formed by the fall of the chip selection signal σ, and timing signals φW and φr are formed by the function control bits and memory array supplied from the outside in normal memory access when the function control enable signal r is at high level. Each bit is formed when the function control bit read from M-ARYF matches. Further, these timing signals φW or φr are respectively formed in a write operation or a read operation regardless of the machine $jl [Yanagawa bit] in an unconditional access in which the function control enable signal 100 is set to a low level. In this case, the timing signal f is generated simultaneously with the timing signal φW, and one signal is supplied to the data driver cover sofa DIB. Unconditional access is to memory array M-ARY
It is used to write and read function control bits to F.

FIG. 2 shows a typical one of the static RAM shown in FIG.
An example of a timing diagram in a write mode of operation is shown. This figure shows the i! of the static RAM of this embodiment. An overview of the loading operation will be explained below.

In FIG. 382, the static type RAM is activated by changing the chip selection signal σ from high level to low level. In synchronization with the low level of this chip selection signal, the write enable signal WE for specifying the write operation mode is changed from high level to low level, and the address signals AO to At are set to high level or low level in combination for specifying address As. It is considered to be low level.

In addition, write data is input to the input/output terminals DO to D7, and a function control bit, which is a keyword, is input to the input/output terminal DF.The 0 function control enable signal rπ specifies normal memory access. It is said to remain at a high level.

In a static type RAM, the timing signal φc is first triggered by the fall of the chip selection signal C8 to a low level.
e is formed and supplied to the X address decoder XDCR and the Y address decoder YDCH. Each of these address decoders is supplied with complementary internal address signals lX~ and By~ formed by an address buffer 80B receiving address signals AO~Ai. The X address decoder XDCR is a complementary internal address signal! X~
is decoded, one word line corresponding to address As is selected, and the word line selection level is set to high level.

As a result, read signals according to the stored data are outputted from all memory cells coupled to the selected word line of each memory array, and transmitted to the corresponding column switch.

On the other hand, the Y address decoder YDCR decodes the complementary internal address signal Qy~, forms a data line selection signal for selecting a set of complementary data lines corresponding to the address AS, and selects the column switch C3WF and cswo~C3.
Send to W7. In each column switch, the data line selection signal selects the complementary data line corresponding to the address As of each memory array, and connects it to the corresponding complementary common data lines CDF and CD0-CD7. This results in
Read signals from memory cells to which address A3 of each memory array is applied are output to corresponding complementary common data lines. In addition, the memory array (Function': A-purpose bit stored in the memory cell corresponding to the address As of M-ARYF) output to the complementary common data line CDF is launched to the Bunnopfronob FF, and its output signal is further used to control the function. The la function input is input to one input terminal of the bit comparison circuit FC for functional side fhII.The other input terminal of this bit comparison circuit FC for functional side control bin) df is input.

The function control bit comparison circuit FC compares the function control bit df supplied from the external main device with the memory array M-A.
Compare the focus for function control read from RYF,
When these match, the output signal fm is set to high level. Further, if the two function control bits do not match, the output signal fm remains at a low level. The high level output signal of this function control bit comparison circuit FC is output to the external main device via the external gH3 child FM, and the requested memory access is performed by the static RAM.
Reports to the main device that it will be executed.

The timing control circuit `rC' executes the write operation.
The output signal f of the function control bit comparison circuit FC is set at the timing when the timing signal φW for performing the
After confirming the high level of m, a timing signal φW is formed and supplied to the data driver sofa DIB. If the output signal fm of the function control bit comparison circuit FC is at a low level at this point, the timing signal φW is not generated.

The data person cover 7 sore DIB is the timing control circuit T'
The ζ operation is set to the low state by the timing signal φW supplied from C, and the 8-bit blue write data supplied via the input/output terminals DO to D7 is used as a complementary write signal, and complementary common data lines CDO to CD7 are set. writes to selected memory cells of each memory array via the memory array.

In the case of a normal read operation in which the write enable signal remains high level, the timing No. 18 ψr is determined by the output signal fm of the function control bit comparison circuit FC.
selectively formed to control read operations. Also,
In the case of unconditional access in which function 1j input pulley S' E is set to low level, the evening/1' timing signal φ
Along with W and pr, a timing signal φwf is generated regardless of the output signal fm of the function control bit comparison circuit FC, and a write or read operation to each memory array including the function control beat/bit is unconditionally executed.

As described above, in the static RAM of this embodiment, a function control bit is provided corresponding to each address of the memory array, and the function control bit is set before executing a write operation or a read operation requested from the outside. The bits are read and compared with an externally applied input function control focus. As a result, a write operation or a read operation is executed only when both function control bits match. These write protection or read control 17
! The function can be used to protect the program area of the memory, restrict reading of the vicarious area, etc. Furthermore, these function control bits can be used not only for write protection and read restriction, but also for many purposes by adding specific attributes to these function control bits. .

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a static RAM, the following effects can be obtained. In other words, (1) A function control via is provided corresponding to each address of the semiconductor memory device, and prior to executing a function requested from the outside, the function control focus corresponding to the designated address is read out, and the request is executed according to the contents. By performing control such as executing or prohibiting the functions to be executed, it is possible to achieve the effect that the functions of the semiconductor memory device can be autonomously controlled using the function control bits.

(2) According to the above item (1), it is possible to reduce the processing load on the main device to which such a static RAM or the like is connected.

(3) By giving various attributes to the function control focus described in item (1) above, it is possible to realize a semiconductor memory device such as a multifunctional static RAM that performs various autonomous controls. It will be done.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment shown in FIG. 1, a function control bit is provided corresponding to each address, but the memory array is divided into multiple memory areas, and a common function control bit is provided corresponding to each memory area. It is also possible to set a focus point and control the function for each memory area.Also, the protection function can be implemented by configuring the function control bit with multiple focus points to identify more functions, or by making the keywords more complex. Furthermore, the access unit is not limited to 9 bits (for example, it may be possible to access in units of 17 bits or 36 bits, including function control bits, or A plurality of bits may be allocated to a single memory array.This method may be modified depending on the block configuration of the static RAM, the combination of control signals, etc., such as providing each address decoder for each memory array.
Various embodiments can be explored.

The above explanation will mainly focus on the static type RA, which is the field of application that was the background of the invention made by the present inventor.
The present invention is applicable to a semiconductor memory device that is accessed in multiple focus units at least. can be used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a function control bit is provided corresponding to each address or memory area of the semiconductor storage device, and prior to executing a function requested from the outside, the function control bit corresponding to the designated address is read out, and the requested function is executed according to the contents. By performing controls such as executing or prohibiting functions, the functions of the semiconductor storage device can be autonomously controlled by the function control focus, and the processing load on the main device can be reduced. .

[Brief explanation of the drawing]

Figure 1 shows a static type RAM to which this invention is applied.
FIG. 2 is a block diagram showing an embodiment of the write operation in the static RAM shown in FIG. 1. Frimbufrosov circuit, M-ARYF, M-ARYO~M-
ARY7 = --Memory array, C3WF, C3WO
~C3W7... Column swifter, X D CR...
X address decoder, YDCR...Y address decoder, ADB...address decoder, DOB...data output buffer, DIB...data buffer, T
C...timing control circuit.

Claims (1)

[Claims] 1. It has a memory array that stores data consisting of a plurality of bits, and its operation is controlled according to specific bits of the data at a specified address read out prior to execution of a function requested from the outside. A semiconductor memory device characterized in that it is a semiconductor memory device. 2. The semiconductor memory device performs a comparison to compare a specific bit of input data supplied from the outside upon access to the specific bit of the storage data at a specified address read out prior to execution of the required function. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a circuit, and executes a required function only when a match signal is obtained by the comparison circuit. 3. The semiconductor memory device according to claim 1 or 2, wherein the comparison operation of a specific bit by the comparison circuit can be inhibited by a control signal supplied from the outside.